JPH10173573A - Adaptive equalizer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an adaptive equalizer which can secure the excellent equalization characteristic despite the timing offset given to a sampling clock. SOLUTION: The received input signal undergoes a convolutional operation with a tap coefficient via a filter 61 of the preceding stage, so that the sampling timing is controlled. A viterbi algorithm circuit 37 outputs a decision signal via the maximum likelihood series estimation and also outputs a complex symbol series candidate with an error signal, i.e., the difference between the output of the filter 61 and the replica signal of a replica signal generation means 62 used as the likelihood information. A filter 62 convolutes the transmission line characteristic estimation value to the complex symbol series candidate to produce a replica signal. A parameter estimation circuit 47 estimates the tap coefficient and the transmission line characteristic estimation value so as to minimize the average square of the error signal under the constraint condition that fixes a specific element of the transmission line characteristic estimation value based on the input signal and the decision signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an adaptive equalizer for suppressing deterioration of transmission characteristics due to intersymbol interference in digital radio communication.

[0002]

2. Description of the Related Art In digital radio communication, especially in digital mobile communication, a propagation path is a multiplex wave propagation path in which a plurality of delay waves having different delay times are present, which causes deterioration of transmission characteristics due to intersymbol interference. There is an equalizer as a technique for suppressing the transmission characteristic deterioration. Maximum likelihood sequence estimation is one of the equalizers with high equalization capability.
nce Estimation (MLSE) is known. This equalizer calculates the likelihood corresponding to the possible signal sequence,
In the signal determination, the signal sequence having the largest value is selected.
As the signal sequence lengthens, the number of all possible signal sequences increases exponentially. Therefore, a Viterbi equalizer that performs MLSE by a Viterbi algorithm in order to reduce the number of sequences and suppress the amount of calculation is known.

FIG. 3 shows a configuration of a conventional receiver including a Viterbi equalizer. First, a received wave received from the antenna 11 is amplified by the low-noise amplifier 12 and then branched into two by the hybrid 13. The one signal is input to a low-pass filter 16 after being multiplied by a multiplier 15 by a carrier signal output from a carrier signal generator 14. The output of the low pass filter 16 is sampled every sampling period T _s by the A / D converter 17 is converted into a digital signal. The other signal of the hybrid 13 is
The carrier signal whose phase is rotated by 90 degrees is multiplied by a multiplier 21, input to a low-pass filter 22, sampled by an A / D converter 23, and converted into a digital signal.

The above operation is quasi-synchronous detection, and the outputs of the A / D converters 17 and 23 correspond to the in-phase component and the quadrature component of the quasi-synchronous detection signal, respectively. I will call it. In the following description, all signals have an in-phase component and a quadrature component, and the signal will be represented using a complex representation that displays the in-phase component as a real part and the quadrature component as an imaginary part. The received signal has waveform distortion caused by intersymbol interference in the transmission path, and is input to the Viterbi equalizer 25 through the input terminal 24. The Viterbi equalizer 25 suppresses deterioration of transmission characteristics due to the waveform distortion, performs signal determination, and outputs a determination signal from an output terminal 26.

FIG. 4 shows the configuration of the Vidabi-type equalizer 25.
Here, the sampling period T _s of the A / D converters 17 and 23 to a symbol period T of the modulation. The replica signal generation circuit 31 performs a convolution operation on the complex symbol sequence candidate input from the input terminal 32 and the transmission path characteristic estimation value input from the input terminal 33, and outputs the operation result from the output terminal 34 as a replica signal. . Complex subtractor 35
Outputs the difference between the received signal input from the input terminal 24 and the replica signal from the terminal 34 as an error signal. 2
The multiplication operation circuit 36 inputs a value obtained by multiplying the absolute value square of the error signal by a negative constant to the Viterbi algorithm circuit 37 as likelihood information, that is, a branch metric. The Viterbi algorithm circuit 37 outputs a complex symbol sequence candidate and performs signal determination by maximum likelihood sequence estimation using the Viterbi algorithm. Specifically, a log likelihood function, that is, a path metric, is calculated as the cumulative value of the branch metric for each complex symbol sequence candidate, and a complex symbol sequence candidate that maximizes the path metric is obtained by the Viterbi algorithm. Then, the selected complex symbol sequence candidate is output to the output terminal 26 as a determination signal. The determination signal is delayed from the present time by a determination delay described later.

The configuration of the replica signal generation circuit 31 is a transversal filter as shown in FIG. 5A, and takes into account the influence of a delay wave up to a delay time 1T.
Considering the influence of the delay wave up to the delay time NT (N is a natural number), the number of delay elements of the transversal filter is N
The number of taps, that is, the number of complex multipliers is N + 1. The complex symbol sequence candidate input from the input terminal 32 is supplied to the delay element 42 having a delay amount of one symbol period T, and the input signal and the output signal of the delay element 42 and the transmission path characteristic estimated value input from the input terminal 33 are output. Are multiplied by complex multipliers 41 and 43, respectively, and after the multiplication, they are added by a complex adder 44. This operation is a convolution operation, and the operation result is output from the output terminal 34.

Next, a description will be given of the parameter estimating means 45 in FIG. In the following, it is assumed that the signal is transmitted in a burst configuration including a training signal 48 as shown in FIG. The switch circuit 51 selects the training signal output from the training signal memory 52 in the section of the training signal 48, and selects and outputs the determination signal output from the Viterbi algorithm circuit 37 in the section of the data signal 49 following the training signal 48. The replica signal generation circuit 53 performs a convolution operation on the output of the switch circuit 51 and the transmission path characteristic estimation value output from the parameter estimation circuit 47, and outputs the operation result as a replica signal. Similarly, the switch circuit 54 selects the received signal from the input terminal 24 in the training signal section, and selects and outputs the received signal delayed by the determination delay from the delay circuit 55 in the data signal section. This is because the determination signal is delayed from the current time by the determination delay. The complex subtractor 56 outputs a difference between the output signal of the switch circuit 54 and the replica signal. This difference is a current error signal in the training signal section and an error signal delayed from the current time by the determination delay in the data signal section. The parameter estimation circuit 47 receives the difference signal and the output signal of the switch circuit 51 as inputs, and obtains and outputs a transmission path estimation value such that the root mean square of the error signal is minimized, that is, based on the least square method. As the least-squares algorithm, an RLS algorithm that strictly and sequentially solves a normal equation, an LMS algorithm that has good characteristics and a small amount of computation are generally used, and various other algorithms are also known (Haykin, S. “Adaptive Filter Theory”, 2nd, Ed. P
rentice-Hall, 1992).

Next, the above-mentioned Viterbi algorithm circuit 37
The following describes the Viterbi algorithm used by. For state estimation by the Viterbi algorithm, the modulation method is BP
The SK modulation will be specifically described as an example. First, the state will be described. When the maximum delay time of the delay wave in the transmission path is QT, {a _m (q) | k−Q + 1 < q < k} is called a state. Here, a _m (q) is a complex symbol candidate for the complex symbol a (q). In this case, the number of states is 2 ^Q next,
The complex symbol sequence can be described as this state sequence. FIG. 6A shows a state transition diagram of Q = 1, that is, a trellis diagram. Let the s-th state at time kT be σ _s (k)
And Here, 0 < s < 1, and the state changes when the time advances from kT to (k + 1) T. The state transition is
Complex symbol candidate a for complex symbol a (k + 1)
Since it depends on the value of _m (k + 1), two transitions occur from one state. As shown in the figure, the state branches from one state to two states, and merges from two states to one state. 1 from two transitions to be merged at the transition destination
Σ _{s ′} (k) to σ _s (k +
Transition metric J _{k + 1} [σ corresponding to the transition to 1)
_s (k + 1), σ _s' (k)].

The metric in the transition from the state σ _{s ′} (k) to σ _s (k + 1) is calculated as J _{k + 1} using the branch metric BR [σ _s (k + 1), σ _{s ′} (k)] for each transition. _{[σ s (k + 1)} , σ s' (k)] = J k [σ s' (k)] + BR is calculated by _{[σ s (k + 1)} , σ s' (k)] (1). J _k [σ _{s ′} (k)] is a path metric at time point k and corresponds to likelihood. State transition σ
_{s' (k) → σ s} (k + 1) complex symbol sequence candidates in is expressed by _{{a m (k), a} m (k + 1)}. J corresponding to two transitions to be merged in the Viterbi algorithm
_{k + 1} [σ _s (k + 1), σ _{s ′} (k)] is compared to select a larger transition, and the metric of the selected transition is determined as a path metric J _{k + 1} [σ _s ( k +
1)]. Then, the time series of the state connected to the selected transition, that is, only the path is left as the maximum likelihood sequence candidate. When this operation is repeated thereafter, the paths survive the number of states. This pass is called the surviving pass. Note that due to memory constraints, the time series of states is past (D−Q +
1) Only up to T is stored, and if the surviving paths do not merge at the time of the past (D−Q + 1) T, the maximum likelihood becomes the current likelihood. That is, signal determination is performed based on the path having the maximum path metric. The signal determined at this time is a signal delayed by DT from the present time, and this DT is called a determination delay time (G. Ungerboeck, “Adaptive maximum likelihood re
ceiver for carrier-modulated data-transmission sys
tems, ”IEEE Trans. Commum, vol.COM-22, pp.624-63
6, 1974). Here, D > Q.

Next, the sampling clock and the equalization characteristics will be described. FIG. 6B shows the waveform of the in-phase component or the quadrature component of the received signal without waveform distortion and noise. Here, the sampling period T _s is equal to the symbol period T of the modulation, a dashed line 58 denote the threshold signal determination. FIG. 6A shows a received signal waveform, and the timing offset of the sampling clock with respect to the received signal is 0.
Corresponds to sampling 1 in FIG.
The case where the timing offset is T / 2 corresponds to the sampling 2 in FIG. When the timing offset is 0, the level of the received signal sampling value is always constant, but when the timing offset is about T / 2, the level may be extremely small. When the level of the received signal sampling value decreases in the presence of noise, the characteristics of the equalizer deteriorate. Therefore, the characteristics of the equalizer deteriorate due to the timing offset of the sampling clock.

As described above, in the receiver configuration including the conventional Viterbi equalizer, since the sampling period coincides with the symbol period, the equalization characteristics are significantly deteriorated due to the timing offset of the sampling clock. There were drawbacks.

[0012]

SUMMARY OF THE INVENTION An object of the present invention is to provide a Viterbi-type adaptive equalizer capable of obtaining excellent equalization characteristics even when a sampling clock has a timing offset.

[0013]

As shown in FIG. 1, the adaptive equalizer according to the present invention comprises: (1) pre-filter means 61 for performing a convolution operation of a received signal and a tap coefficient;
(2) a convolution operation of the complex symbol sequence candidate and the transmission path estimation value, and a replica signal generation filter means 62 for outputting as a replica signal; and (3) a difference between the output of the pre-stage filter means and the replica signal as an error signal. A maximum likelihood sequence estimating means 63 for performing signal determination based on the error signal and outputting a determination signal and a complex symbol sequence candidate; (4) tap coefficients and transmission path characteristic estimation values with the received signal and the determination signal as inputs; And a parameter estimating means 64 for estimating.

When performing diversity reception, the pre-filter unit can be expanded so as to perform a convolution operation on received signals from a plurality of antennas with different tap coefficients and add and output them. [Operation] The basic operation of the present invention is as follows. (1) The pre-filter unit adjusts the sampling timing by performing a convolution operation on the received signal and the tap coefficient, and outputs the operation result.
(2) The replica signal generation filter means performs a convolution operation between the complex symbol sequence candidate and the transmission path estimation value, and outputs a replica signal that is an estimated value of the received signal. (3) The maximum likelihood sequence estimating means uses the difference between the output of the pre-filter means and the replica signal as an error signal, performs signal determination by maximum likelihood sequence estimation using this error signal as likelihood information, Output candidates. (4) The parameter estimating means receives the received signal and the determination signal as inputs, and fixes a specific element of the transmission path characteristic estimation value under a constraint condition that:
The tap coefficient and the estimated channel characteristic value are estimated so that the mean square of the error signal is minimized.

The pre-filter means performs sampling timing adjustment by performing convolution operations on the received signals from a plurality of antennas with different tap coefficients, and outputs the sum of the plurality of operation results at the time of diversity reception. It is also possible. The following points are different from the prior art. (1) Sampling timing is adjusted by performing a convolution operation of the received signal and the tap coefficient in the pre-filter unit, and likelihood information is obtained using the operation result. (2) The tap coefficient of the pre-filter means and the estimated value of the transmission path characteristic are estimated such that the average square of the error signal is minimized under the constraint that a specific element of the estimated value of the transmission path characteristic is fixed.

[0016]

Embodiment 1 FIG. 1 shows the structure of Embodiment 1 of the present invention (claim 1).
A received signal having a sampling period T / 2 is input from the input terminal 24. It is known that the deterioration due to the timing offset of the sampling clock can be compensated by using a transversal filter whose delay time of the delay element is 1T or less (Ungerboeck, G., “Fractional tap-spacing”.
equalizer and consequence for clock recovery in d
ata modems ”,“ IEEE Trans. on Commun. Vol.COM-24,
No. 8, pp. 856-864, August 1976). Therefore, in the present invention, the pre-filter 61 of the transversal filter is provided for the input received signal with a delay time smaller than 1T.
That is, the pre-filter 61 corresponding to the pre-filter means
Is a transversal filter having two stages of delay elements 71 having a delay time T / 2, as shown in FIG. 3, which performs a convolution operation of the received signal from the terminal 24 and the tap coefficient input from the terminal 72, and Output the operation result. The convolution operation has a function of selecting a signal having an optimum timing from received signals at different timings, and can adjust sampling timing adaptively.

The replica signal generation filter 62 corresponding to the replica signal generation means has a delay time T as shown in FIG.
And performs a convolution operation between the complex symbol sequence candidate and the transmission path characteristic estimation value input from the terminal 33, and outputs the result as a replica signal. Here, the fading amplitude of the preceding wave is fixed to 1 with the tap coefficient of the complex multiplier 41 to which the complex symbol sequence candidate to be input to the delay element 42 is input as 1. This fading amplitude corresponds to a specific element of the transmission path characteristic estimation value. The complex subtractor 35 outputs the difference between the output of the pre-filter 61 and the replica signal from the replica signal generation filter 62 as an error signal. The squaring operation circuit 36 inputs a value obtained by multiplying the absolute value square of the error signal by a negative constant to the Viterbi algorithm circuit 37 as likelihood information, that is, a branch metric. The Viterbi algorithm circuit 37 outputs a complex symbol sequence candidate and performs signal determination by maximum likelihood sequence estimation using the Viterbi algorithm. Specifically, a log likelihood function, that is, a path metric, is calculated as the cumulative value of the branch metric for each complex symbol sequence candidate, and a complex symbol sequence candidate that maximizes the path metric is obtained by the Viterbi algorithm.
Then, the selected complex symbol sequence candidate is output to the output terminal 26 as a determination signal. Here, the complex subtractor 3
5, square operation circuit 36 and Viterbi algorithm circuit 63
Corresponds to the maximum likelihood sequence estimation means 63.

The parameter estimating means 64 comprises a training signal memory 52, a delay circuit 55, switch circuits 51 and 54, a pre-filter 74, a complex subtractor 56, a replica signal generating filter 53, and a parameter estimating circuit 47. The signal and the determination signal are input, and the tap coefficient of the pre-filter 61 and the estimated value of the transmission path characteristic are estimated and output. Next, the parameter estimating means 64 will be described. The switch circuit 51 selects the training signal output from the training signal memory 52 in the training signal section, and selects and outputs the determination signal output from the Viterbi algorithm circuit 37 in the data signal section following the training signal. The replica signal generation filter 53 performs a convolution operation on the output of the switch circuit 51 and the transmission path characteristic estimation value output from the parameter estimation circuit 47, and outputs the operation result as a replica signal. Similarly, the switch circuit 54 selects the reception signal of the input terminal 24 in the training signal section, and selects and outputs the reception signal delayed by the determination delay from the delay circuit 54 in the data signal section.
This is because the determination signal is delayed by the determination delay. The pre-filter 74 performs a convolution operation on the output signal of the switch circuit 54 and the tap coefficient which is the output signal of the parameter estimation circuit 47, and outputs the operation result. The complex subtractor 56 calculates and outputs the difference between the output signal of the pre-filter 74 and the replica signal. This difference is a current error signal in the training signal section and an error signal delayed from the current time by the determination delay in the data signal section. The parameter estimating circuit 47 receives the difference and the output signals of the switch circuits 51 and 54 as inputs and, under the constraint that the fading amplitude of the preceding wave is fixed at 1 (constant), the mean square of the error signal is minimized. That is, the tap coefficient and the estimated value of the transmission path characteristic are obtained and output based on the least square method. Here, the fading amplitude of the preceding wave corresponds to a specific element of the estimated channel characteristic value.

Without the above constraint, the pre-filter 7
In the least-squares estimation with 4 provided, the tap coefficients and the estimated values of the transmission path characteristics are all 0, and the equalization characteristics are significantly degraded. Restraints are needed to prevent this. The least-squares method under the constrained condition is an algorithm for minimizing the output power of the adaptive array with the constrained condition by "Adaptive antennas" by RTJr. Compton (Pr.
As described in Chapter 6 of entice Hall (1988), if a complex symbol candidate of a preceding wave is regarded as a reference signal, an ordinary least squares algorithm can be applied.

In this embodiment, a received signal having a sampling period T / 2 is used, and sampling timing adjustment is performed by performing convolution of the received signal and the tap coefficient in the pre-filter means 61 and 74. Therefore, even when there is a timing offset of the sampling clock, the deterioration of the equalization characteristics can be suppressed. Although the sampling period is set to T / 2 here, it can be easily extended to other sampling period values (less than the symbol period T). As described above, the sampling period of the input signal is shorter than one symbol period, but the processing in the replica signal generation filter 62, the maximum likelihood sequence estimating unit 63, and the parameter estimating unit 64 may be performed for each one symbol period T.

Although the fading amplitude of the preceding wave is fixed, it is also possible to fix the fading amplitude of the delayed wave. In this case, a fixed value is set in the other complex multiplier of the replica signal generation filter. For example, in the replica signal generation filter 62, the tap coefficient of the complex multiplier 43 is fixed to 1. Furthermore, the Viterbi algorithm circuit 2
The Viterbi algorithm used in 7 can be replaced with a simple algorithm such as DDFSE that reduces the number of states compared to the original Viterbi algorithm in order to reduce the amount of computation. Embodiment 2 FIG. 2 shows the configuration of another embodiment of the present invention (claim 2). This configuration is an extension of the first embodiment in the case of diversity reception, and FIG. 1 shows two branches as an example. First, the received signal from each of the two antennas from the input terminal 24 ₁ and 24 ₂ is inputted. Here, the sampling period of the received signal is T / 2. Input terminal 24 ₁
Received signal from is convolved with tap coefficients in the preceding stage filter 61 _1, the received signal from the input terminal 24 ₂ is convolved with different tap coefficients in the preceding stage filter 61 _2. Complex adder 81 outputs the sum of the output signals of the preceding stage filter 61 ₁ and 61 _2. Front filter 61 ₁ and 61 _2, as with the previous stage filter 61 in FIG. 1 is a transversal filter having delay elements 71 of delay time T / 2. The convolution operation has a function of selecting an optimum timing from received signals of different timings, and can adjust sampling timing adaptively. Here, the first-stage filters 61 ₁ and 61 ₂ and the complex adder 81 correspond to the first-stage filter means 61. The replica signal generation filter 62 corresponding to the replica signal generation means has the same configuration as that shown in FIG. 1, performs a convolution operation on the complex symbol sequence candidate and the transmission path characteristic estimation value input from the terminal 33, Output as a signal. The complex subtractor 35 outputs a difference between the output signal of the complex adder 81 and the replica signal as an error signal. The square operation circuit 36 inputs a value obtained by multiplying the absolute value square of the error signal by a negative constant to the Viterbi algorithm circuit 37 as likelihood information, that is, a branch metric. The Viterbi algorithm circuit 37 outputs a complex symbol sequence candidate, performs signal determination based on maximum likelihood sequence estimation, and outputs a determination signal to the output terminal 26, as in the case of FIG. Here, the complex subtractor 35, the square operation circuit 36, and the Viterbi algorithm circuit 37 correspond to the maximum likelihood sequence estimation unit 63.

The parameter estimating means 64 includes a training signal memory 52, delay circuits 55 ₁ and 55 ₂ , switch circuits 51, 54 ₁ and 54 ₂ , and pre-filters 74 ₁ and 74.
4 _2, the complex subtractor 56, a complex adder 82, is composed of a replica signal generating filter 53 and the parameter estimation circuit 47, as input the received signals and the determination signal input from the input terminal 24 ₁ and 24 _2, front estimating the tap coefficients of the filters 61 ₁ and 61 ₂ and the channel estimation value and outputs. Next, the parameter estimating means 64 will be described. The switch circuit 51 selects a training signal output from the training signal memory 52 in a training signal section, and selects and outputs a determination signal in a data signal section following the training signal. The replica signal generation filter 53 performs a convolution operation on the output of the switch circuit 51 and the transmission path characteristic estimation value output from the parameter estimation circuit 47, and outputs the operation result as a replica signal. Similarly, each of the switch circuits 54 ₁ and 54 ₂ selects a received signal in a training signal section, and selects and outputs a received signal delayed by a determination delay in a data signal section.
This is because the determination signal is delayed by the determination delay. Each front filter 74 ₁ and 74 ₂ performs an output signal of the switch circuit 54 ₁ and 54 _2, the convolution operation of the tap coefficient which is the output signal of the parameter estimation circuit 47, and outputs the result of operation. The complex adder 82 adds the output signals of the pre-stage filters 74 ₁ and 74 ₂ , and the complex subtractor 56 subtracts and outputs the replica signal therefrom. This difference is a current error signal in the training signal section and an error signal delayed from the current time by the determination delay in the data signal section. Parameter estimation circuit 4
7 is input with the output signal of the difference and the switch circuit 51, 54 _1, 54 _2, under the constraint that the same manner as in Example 1, to fix the fading amplitude of preceding wave to 1,
A tap coefficient and a transmission path characteristic estimated value are obtained and output so that the root mean square of the error signal is minimized, that is, based on the least square method.

In this embodiment, a received signal having a sampling period of T / 2 is used, and pre-filter means 61 ₁ and 61 ₁ are used.
_2, 74 _1, by performing a convolution operation between the received signal and the tap coefficient at 74 _2, is performed sampling timing adjustment. Therefore, similarly to the first embodiment, it is possible to suppress the deterioration of the equalization characteristics due to the timing offset of the sampling clock. In addition, complex adder 8
The outputs of a plurality of pre-stage filters are synthesized at 1, 82,
It has a function equivalent to diversity combining. Therefore,
Even when a delayed wave with a long delay time that cannot be equalized arrives, it can be removed by diversity combining in the pre-filter means, so that equalization characteristics can be maintained.

[0024]

As described above, since the timing of the received signal is adjusted in the pre-filter means, the equalizer operates well even when the sampling clock has a timing offset. Also, in the extended configuration for diversity reception, even when a delayed wave having a long delay time that cannot be equalized arrives, diversity combining is performed in the pre-filter means, so that equalization characteristics can be maintained.

Therefore, the present invention is effective for a high-speed transmission system in digital radio communication in which transmission characteristics are significantly degraded due to intersymbol interference.

[Brief description of the drawings]

FIG. 1 is a functional configuration diagram of a first embodiment of the present invention.

FIG. 2 is a functional configuration diagram according to a second embodiment of the present invention.

FIG. 3 is a configuration diagram of a receiver including a conventional Viterbi equalizer.

FIG. 4 is a functional configuration diagram of a conventional Viterbi equalizer.

5A is a functional configuration diagram of a replica signal generation circuit 31 in FIG. 4, and FIG. 5B is a configuration diagram of a frame of a transmission signal.

FIG. 6A is a state transition diagram of the Viterbi algorithm, and FIG. 6B is an explanatory diagram of a received signal and sampling timing.

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Claims (2)

[Claims] 1. A pre-filter means for performing a convolution operation with a tap coefficient using a received signal having a sampling period shorter than one symbol period as an input, and outputting the result of the convolution, and estimating a transmission path characteristic using a complex symbol sequence candidate as an input A convolution operation with a value, a replica signal generation filter means for outputting the operation result as a replica signal, and a difference between the output of the pre-filter means and the replica signal as an error signal, and the error signal as likelihood information Maximum likelihood sequence estimating means for performing signal determination by maximum likelihood sequence estimation and outputting a determination signal and the complex symbol sequence candidate, and fixing the specific element of the transmission path characteristic estimation value with the received signal and the determination signal as inputs. The tap coefficients and the transmission path characteristic estimation so that the mean square of the error signal is minimized under the constraint that the An adaptive equalizer characterized by comprising parameter estimating means for estimating and outputting a value. 2. Receiving signals from a plurality of antennas each having a sampling period shorter than one symbol period are input, convolution operations are performed on these received signals with different tap coefficients, and a plurality of operation results are obtained. Pre-filter means for outputting the sum, replica signal generation filter means for performing a convolution operation with a transmission path characteristic estimation value with a complex symbol sequence candidate as input, and outputting the operation result as a replica signal; A difference between the output of the means and the replica signal as an error signal, performing a signal decision by maximum likelihood sequence estimation using the error signal as likelihood information, and outputting a decision signal and the complex symbol sequence candidate; When the plurality of received signals and the determination signal are input, and a specific element of the transmission path characteristic estimation value is fixed. Parameter estimating means for estimating and outputting the tap coefficient and the transmission path characteristic estimation value such that the mean square of the error signal is minimized under the constraint condition. Equalizer.