JP2001044838A - D/a converting device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the scale of a decoder block by constituting a decoding means by means of a second noise shaper and a sub-decoder. SOLUTION: A D/A converting device is constituted of a digital filter, first noise shapers, a decoder, a one-bit D/A converter string and a first adding means. Among decoder among them, a holding value (Z) of a delay means constituting a filter is outputted from the first shaping filter 206 of the second noise filter 203. The output of the second noise shaper 204 is inputted to the sub-decoder 207. The output is converted into the signal of one bit (binary) by a second converting means 208. At least q (q>=k-1) sub-noise shapers are arranged in the sub-decoder 207, when the gradation of the first noise shaper is made to be k. The third adding means having n outputs executes addition of each m every n pieces, concerning the second noise shaper 203 and the sub- noise shaper and executes n outputs.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital-to-analog (D / A) converter for converting a digital signal to an analog signal. D / A conversion device.

[0002]

2. Description of the Related Art A digital-to-analog (D / A) converter that performs oversampling and bit compression of an input digital signal using a digital filter and a noise shaper converts the amplitude accuracy of the input signal into time-axis accuracy, thereby providing a circuit. High conversion accuracy can be realized without high-precision trimming.

Hereinafter, a conventional D / A converter will be described with reference to the drawings.

FIG. 9 is a block diagram showing the configuration of a conventional D / A converter. 10, 1001 is an input terminal, 1002 is a digital filter, and 1003 is a first terminal.
Noise shaper, 1004 is a decoder, 1005 is 1
A bit D / A converter sequence, 1006 is an adder, 1007
Is an output terminal.

FIG. 10 is a block diagram showing a detailed configuration of the decoder 1004 of the D / A converter shown in FIG.
10, 1101 is an input terminal, 1102 is a converter, 1103 is a second noise shaper, 1104 is an adder, 1105 is a quantizer, 1106 is a shaping filter, and 1107 is a converter.

The operation will be described below.

First, a digital signal input from an input terminal 1001 is filtered by a digital filter 1002.
It is converted to a p-fold (p is an integer of 2 or more) sampling frequency, and attenuates an unnecessary band of fs / 2 or more (fs is an input sampling frequency). Next, the first noise shaper 1003 limits the word length of the output signal of the digital filter 1002, and changes the frequency characteristics of the requantization noise generated when the word length is limited to predetermined characteristics. That is, in the first noise shaper 1003, the input signal is converted into a signal having a high sampling frequency and a small word length having the same accuracy as the original signal in a frequency band of fs / 2 or less.

First, the decoder 1004 converts the output (k value) of the noise shaper 1003 into at least (k-1) 1-bit (binary) signal strings. Then, the (k-1) 1-bit signal strings are extracted and added m every n signals, and the added value is again converted into a 1-bit signal string and output (n≤k-1). , K ≦ m × n +
1).

[0009] A 1-bit D / A converter array 1005 converts the output of the decoder 1004 into an analog signal. Then, the adding means 1006 outputs the 1-bit D / A converter
05 are added, and a signal is output via an output terminal 1007.

Next, the operation of the decoder 1004 will be described with reference to FIG.

First, the converter 1102 is connected to the input terminal 110.
1 (a first noise shaper 1)
003) is converted to a continuous positive integer value starting from 0. This means that, for example, if the input from the input terminal 1101 is a quinary signal of -2 to +2, 2 is added to this signal to convert it to a quinary signal of 0 to 4.
The signal thus converted is converted into a 1-bit signal sequence by (k−1) second noise shapers 1103.

Next, the operation of the second noise shaper 1103 will be described. The adder 1104 adds the output of the converter 1102 and the output of the shaping filter 1106. Then, the quantizer 1105 quantizes the output of the adder 1104 and feeds back the quantization error to the shaping filter 1106.

Here, the quantizer 1105 includes an adder 11
04 is divided by (k-1), and the division result is converted to an integer. Further, (k-1) second noise shapers 110
The output value of the quantizer is controlled so that the sum of the quantization noise generated in step 3 becomes a constant value. Specifically, the initial value of the shaping filter 1106 starts from 0 (k−
1) independent and continuous positive integer values, and quantization noise is (k-1) independent and continuous values starting from 0. Thus, the quantizer 1105 quantizes the output of the adder 1104.

Next, the converter 1107 converts the outputs of the (k-1) noise shapers 1103 into n 1-bit signal strings and outputs the same. The operation of the converter 1107 will be described.

First, (k-1) signals are input to the converter 1107 at each output timing of the noise shaper 1103. From the (k-1) input signals, for example, the noise shaper 0 shown in FIG. 10 is used as a reference and n input signals are skipped (1≤n≤k-1), and m input signals are extracted (k≤mx).
n + 1) and add it. Similarly, m input signals are extracted at intervals of n with respect to the noise shaper 1 and added.
That is, one output is the noise shapers 0, n, 2n,
, M (n-1), and the other outputs are noise shapers 1, n + 1, 2n + 1, ..., m (n
The sum of the outputs of -1) +1 is obtained, and n signals are output for each input sample of the input signal of the converter 1107. Through the above processing, the (k-1) input signals to the converter 1107 are converted into n signals obtained by adding m signals each. Further, the added signal is converted into a 1-bit (binary) signal and then output.

After being converted into an analog signal by the 1-bit D / A converter train 1005, the signal is added by the adding means 1006 and output from the output terminal 1007.

As described above, the input signal is subjected to band limitation, oversampling, word length limitation and frequency characteristic conversion of quantization noise by a digital filter and a noise shaper, and the data is converted into a plurality of 1-bit data by a decoder. The output of the noise shaper is converted into one signal using a PWM (Pulse Width Modulation) or the like by converting the signal into a signal string, converting the signal into an analog signal with a 1-bit D / A converter string, adding the signal with an adder and outputting the signal. Since there is no need to convert to a bit signal sequence, a high clock is not required. Therefore, the effect of reducing the generation of unnecessary radiation noise can be obtained.

[0018]

However, in the above conventional configuration, at least (k-
1) There is a problem that two second noise shapers are required, and the circuit scale becomes very large.

The present invention solves the above-mentioned conventional problems. The same performance is obtained, and the scale of the decoder block is reduced, so that a high-performance and small-scale D / A is achieved.
It is an object to provide a conversion device.

[0020]

In order to achieve this object, a D / A converter according to the present invention attenuates an unnecessary band of an input digital signal and increases the sampling frequency p times (p ≧ 2). A first noise shaper that limits the word length of the output signal of the digital filter, and converts the requantization noise generated when the word length is limited into a predetermined frequency characteristic; Decoding means for converting the output signal of the shaper into a plurality of 1-bit signal strings; a 1-bit D / A conversion string for converting each 1-bit signal string of the decoding means into an analog signal; and an output of the 1-bit D / A conversion string And first decoding means for converting k values (k is a positive integer) output by the first noise shaper into an integer value of 0 or more; The first A second noise shaper for limiting the output of the conversion means to a word length and converting requantization noise generated at the time of the word length limitation into a predetermined frequency characteristic; and an output of the first conversion means and a second noise It has a sub-decoder that performs predetermined arithmetic processing on the output of the shaper, and a second conversion unit that converts the output of the sub-decoder into a 1-bit signal sequence.

Thus, since the decoding means is composed of the second noise shaper and the sub-decoder, a high-performance D / A converter can be realized while reducing the circuit scale.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A first invention of the present invention is to provide a digital filter for attenuating an unnecessary band of an input digital signal and for increasing a sampling frequency p times (p ≧ 2), and a digital filter for the digital filter. A first noise shaper for limiting the word length of the output signal and converting requantization noise generated at the time of limiting the word length into a predetermined frequency characteristic; Decoding means for converting to a bit signal sequence;
1-bit D / A for converting a bit signal sequence into an analog signal
A conversion sequence, and first addition means for adding the output of the 1-bit D / A conversion sequence, wherein the decoding means outputs k kinds of values (k is a positive integer) output by the first noise shaper. ) Is converted to an integer value of 0 or more, and the output of the first conversion means is limited in word length, and the requantization noise generated when the word length is limited is converted into a predetermined frequency characteristic. A second noise shaper for conversion, a sub-decoder for performing predetermined arithmetic processing on the output of the first conversion means and the output of the second noise shaper, and conversion of the output of the sub-decoder into a 1-bit signal sequence And second conversion means for performing the conversion.

The second noise shaper includes a first shaping filter having at least one delay unit, a second shaping filter for adding an output of the first conversion unit and an output of the first shaping filter. An adder, and a first quantizer that quantizes an output of the second adder and outputs a quantization error together with a quantized output, and inputs the quantization error to the first shaping filter. Things.

The sub-decoder further comprises q (q ≧ k−1) sub-noise shapers each having as inputs the output of the first conversion means and the output of the delay means of the second noise shaper. A second noise shaper and a third addition means for adding m pieces of outputs from the q number of sub-noise shapers and outputting n pieces of addition results, wherein the sub-noise shaper comprises: It has the same characteristics as the noise shaper, gives an independent offset i (1 ≦ i ≦ q) to the output value Z of the delay means of the first shaping filter, and modulates (Z + i) by (q + 1) A second shaping filter that sets the output value of the first delay means and the output of the second shaping filter as the output value of the virtual delay means;
And the second quantizing means for quantizing the output of the fourth adding means.

According to a second aspect of the present invention, in the first aspect, the sub-decoder has q as an input to each of the output of the first conversion means and the output of the delay means of the second noise shaper. × (n−1) / n (q ≧ k−1) sub-noise shapers, and q / n virtual noise shapers added to the q × (n−1) / n noise shapers to obtain q Fifth adding means for extracting m noise shapes every n when adding the noise shapers, adding outputs other than the virtual noise shaper, and outputting n-1 addition results, and the first conversion means And a sixth adder for subtracting the sum of the outputs of the fifth adder from the sub-noise shaper, the sub-noise shaper having the same characteristics as the second noise shaper, and a delay means for the first shaping filter. Offset i (1 ≦ i ≦ q), and (Z + i) is given by (q
+1) a second shaping filter having a remainder obtained by dividing the remainder by virtual delay means, and a fourth adding means for adding an output of the first converting means and an output of the second shaping filter. , Having the same characteristics as the first quantizing means, and a second quantizing means for quantizing the output of the fourth adding means.

According to a third aspect of the present invention, in the above-mentioned aspect, the first shaping filter has a transfer characteristic described by z ⁻¹ , and the first quantizing means includes a first quantizing means. If the input of the quantization means is negative, 0 is output as a quantization output, and if it is positive, 1 is output as a quantization output, and the remainder obtained by dividing the input of the first quantization means by (q + 1) is output as a quantization error output. , The second shaping filter outputs a remainder obtained by dividing (Z + i) by (q + 1), where Z is the output value of the delay means of the first shaping filter in the second noise shaper. The quantization means outputs 0 if the input of the second quantization means is negative, and outputs 1 if it is positive.

According to a fourth aspect of the present invention, in the above-mentioned aspect, the first shaping filter is 2z ^-1 -z ^-2.
And the first quantizing means sets -1 if the input of the first quantizing means is negative, and sets the input of the first quantizing means to (q + 1 ) Is output as a quantized output if the quotient divided by 2 is 2 or more, and a value obtained by adding (q + 1) if the input of the first quantizing means is negative, , If positive, input (q +
The remainder divided by 1) is output as a quantization error output.
When the output value of the term z ^-1 and the output value of the term z ^-2 of the delay means of the first shaping filter in the second noise shaper are Z1 and Z2, respectively, the (Z1 + i) Remainder M divided by (q + 1)
The remainder M2 obtained by dividing 1 and (Z2 + i) by (q + 1) is obtained, and 2 × M1−M2 is output. The second quantization means is −1 if the input of the second quantization means is negative. Is positive, the quotient obtained by dividing the input of the second quantization means by (q + 1) is 2 or more, and if less than 2, the quotient is output as the quantized output.

According to a fifth aspect of the present invention, in the third aspect, the second shaping filter in the i-th (1 ≦ i ≦ q) sub-noise shaper is the first shaping filter in the second noise shaper. When the output value of the delay means of the shaping filter is Z, i is output if Z <(q + 1-i), and S = 2 if Z ≧ (q + 1-i).
Assuming that a minimum integer satisfying ^t ≧ q + 1 (t is a positive integer) is S, first comparing means for outputting S− (q + 1) + i, and an output of the first converting means and the first comparing means Eighth addition means having a t-bit word length for adding the outputs of the means is provided, and the operation result of the eighth addition means is output.

According to a sixth aspect of the present invention, in the fourth aspect, the second shaping filter in the i-th (1 ≦ i ≦ q) -th sub-noise shaper is the first shaping filter in the second noise shaper. When the output values of the delay means of the shaping filter are Z1 and Z2, Z1 <
In the case of (q + 1-i), i is output, and Z1 ≧ (q + 1-i)
In the case of i), a second comparing means for outputting S− (q + 1) + i when S is the smallest integer satisfying S = 2 ^t ≧ q + 1 (t is a positive integer), and Z2 <(q + 1−i) ) For i
And if Z2 ≧ (q + 1−i), then S = 2 ^t ≧ q
A third comparing means for outputting S- (q + 1) + i, where S is a minimum integer which becomes +1 (t is a positive integer), and an output Z1 of the delay means and an output of the third comparing means. Ninth adding means having a word length of t bits to be added, tenth adding means having a word length of t bits for adding the output Z2 of the delay means and the output of the fourth comparing means, And an eleventh adding means for subtracting the output of the tenth adding means from the output of the ninth adding means doubled, and outputting the output of the eleventh adding means.

According to a seventh aspect of the present invention, in the above-mentioned aspect, the sub-decoder includes an output of the first conversion means and a second output.
And a storage means for storing in advance the result of the arithmetic processing based on the output of the delay means of the noise shaper as data.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(Embodiment 1) FIG. 1 is a block diagram showing a configuration of a D / A converter according to Embodiment 1 of the present invention. In FIG. 1, 101 is an input terminal, 102 is a digital filter, 103 is a first noise shaper, 10
4 is a decoder, 105 is a 1-bit D / A converter train, 10
Reference numeral 6 denotes a first adding means, and 107 denotes an output terminal. These are the same as the conventional example in overall operation.

FIG. 2 is a block diagram showing a detailed configuration of the decoder 104 in the present embodiment of the D / A converter shown in FIG. 2, reference numeral 201 denotes an input terminal, 202 denotes a first conversion unit, 203 denotes a second noise shaper, 204 denotes a second addition unit, 205 denotes a first quantization unit, 206 denotes a first shaping filter, 207
Is a sub-decoder, and 208 is a second conversion means.

The first conversion means 202 and the second noise shaper 203 have the same arithmetic functions as those of the first converter 1102 and the second noise shaper 1103 of the prior art, and therefore detailed description is omitted. 2 noise shaper 2
03 differs from the prior art in that the value (Z) of the delay means constituting the filter is output from the first shaping filter 206 in FIG. The output of the second noise shaper 203 is input to the sub-decoder 207, and the output of the sub-decoder 207 performs the same operation as the conventional group of second noise shapers 1103 by the configuration described later, 208, one bit (2
Value) and output.

FIG. 3 shows an example of the configuration of the sub-decoder 207.

In FIG. 3, the first conversion means 202 and the second noise shaper 203 are the same as those shown in FIG. Reference numeral 301 denotes a sub-noise shaper, which has at least q (q ≧ k−1) when the gradation of the first noise shaper 103 is k. Reference numeral 302 denotes a third adding means having n outputs.
3 and the sub-noise shaper 301, adding m by n every n, and outputting n outputs.

In FIG. 3, the gradation of the first noise shaper 103 is 11 (k = 11), and the sub-noise shaper 301
Is 11 (q = 11), n = 3, m = 4
Is shown.

FIG. 5 shows a second noise shaper 203,
FIG. 3 is a block diagram illustrating a configuration of a sub-noise shaper 301.

In FIG. 5, the second noise shaper 20
3 is a second adder 204 and a first quantizer 20
5 and a first shaping filter 206 having a delay unit 501 of one sample period. The sub-noise shaper 301 includes a fourth adding unit 502, a second quantizing unit 503, and a second shaping filter. 504. That is, the sub-noise shaper 301 has the above-described configuration when the second noise shaper 203 has a first-order characteristic as shown in FIG.

The second noise shaper 203 is a conventional noise shaper 203.
The same operation as the second noise shaper having the following characteristics is performed, and the first shaping filter 206
It has a characteristic of Z ^{-1 in} the configuration consisting of only 01, and the output of the delay means 501 is output as Z.

The fourth addition means 502 adds the output of the first conversion means 202 and the output of the second shaping filter 504 having a function to be described later, and outputs the addition result to the second quantization means 503. Is quantized and output.
The second quantization means 503 is used for the second noise shaper 20.
3 is performed in the same way as the first quantization means 205, but may not have a function for outputting a quantization error.

Of the q sub-noise shapers 301, i
The second (1 ≦ i ≦ q) sub-noise shaper
The shaping filter 504 has an arithmetic function of outputting a remainder obtained by dividing Z + i by q + 1 when the value Z held by the delay unit 501 in the first shaping filter 206 is input.

As described above, according to the present embodiment, a plurality of conventional second noise shapers are integrated into one, and the other is configured by a sub-noise shaper. Therefore, the circuit scale can be reduced while maintaining the same performance. Can be.

(Embodiment 2) FIG. 4 is a block diagram showing a configuration of a decoder of a D / A converter according to Embodiment 2 of the present invention. This embodiment is different from Embodiment 1 in the configuration of the decoder 104 (sub-decoder 207).

In FIG. 4, the first conversion means 202 and the second noise shaper 203 are the same as those shown in FIG. Reference numeral 301 denotes a sub-noise shaper, 401 denotes fifth adding means, and 402 denotes sixth adding means. The sub-noise shaper 301 has the same configuration as that shown in the first embodiment (FIG. 5), but assumes a virtual sub-noise shaper (a block indicated by a dashed line) every nth unit.
The fifth adding means 401 adds m pieces every n pieces, but since there is no virtual sub-noise shaper, the number of the fifth adding means is n-1.

In FIG. 4, n = 3 and m = 4, there are seven actual sub-noise shapers 301, and the output of the fifth adding means 401 is two, p1 and p2.

Here, since the total sum of the decoder outputs of the D / A converter in the first embodiment is controlled to be the same as the output of the first conversion means 202, the sixth addition means 402 The result obtained by subtracting the sum p1 + p2 of the outputs of the fifth adding means 401 from the output of the first converting means 202 is equivalent to adding a virtual sub-noise shaper. That is, the output of the sixth adder 402 can be used as the n-th (p3) output of the sub-decoder.

As described above, according to the present embodiment, the number of sub-noise shapers can be further reduced as compared with the first embodiment, so that the circuit size can be further reduced.

(Embodiment 3) In Embodiments 1 and 2, the second noise shaper 203 is of the first order as shown in FIG. A case where the order of the second noise shaper 203 is set to the second order will be described as a third embodiment.

FIG. 6 shows D / D according to the third embodiment of the present invention.
FIG. 9 is a block diagram illustrating a configuration of a second noise shaper and a sub-noise shaper of the A-converter.

Except for the configuration of the second noise shaper and the sub-noise shaper, the configuration is the same as that of the first and second embodiments, and the description is omitted.

In FIG. 6, the second noise shaper 20
3 is a second adder 204 and a first quantizer 20
5 and a first shaping filter 206. The first shaping filter 206 includes delay means 601 and 602 for one sample period, and a seventh adding means 6.
03, and subtracting the output of the delay unit 602 from the value obtained by doubling the output of the delay unit 601 to obtain 2Z ^-1 -Z
^-2 characteristics. Therefore, the second noise shaper 203
Is the second order. Further, the first shaping filter 206 outputs the output of the delay means 601 and 602 to Z1,
Output as Z2. That is, the second noise shaper 20
3 to the sub-noise shaper 301 have an order of 1
What was Z in the following case, but Z if the order is second order
1, Z2.

The sub-noise shaper 301 has a fourth adder 502, a second quantizer 503, and a second shaping filter 604. Fourth adding means 5
02 adds the output of the first conversion means 202 and the output of the second shaping filter 604. The result of the addition is output by the second quantization means 503 to the first quantization means 2.
Quantization is performed in the same way as 05. The second quantization means 503 is
It may be considered that the function of outputting the quantization error of the first quantization means 205 is omitted.

The second shaping filter 604
When the i-th (1 ≦ i ≦ q) of the q numbers is considered, the value Z1 + Z2 of the delay means 601 and 602 is used as an input, and Z1 + i is twice the remainder of the division by q + 1.
The value of the remainder obtained by dividing 2 + i by q + 1 is subtracted and output to the fourth adding means 502.

As described above, according to the present embodiment, even if the order of the second noise shaper is set to the second order,
The same effect as that of No. 2 can be obtained.

(Embodiment 4) FIG. 7 is a block diagram showing a configuration of a second shaping filter of a D / A converter according to Embodiment 4 of the present invention. In this embodiment,
The second shaping filter 504 of the sub-noise shaper 301 according to the first and second embodiments is realized by a different configuration. Other configurations are described in the first and second embodiments.
Therefore, only the differences will be described.

In FIG. 7, the second shaping filter 504 has a first comparing means 701 and an eighth adding means 702.

The operation of the second shaping filter 504 in the i-th sub-noise shaper 301 of the q filters will be described below as an example. The first comparing means 701 constituting the second shaping filter 504 receives the input of the second shaping filter 504, that is, the first shaping filter 20 in the second noise shaper 203.
6, the hold value Z of the delay means 501 is Z <(q + 1−i)
In the case of, i is output, and in the case of Z ≧ (q + 1−i),
Assuming that the smallest integer satisfying S = 2 ^t ≧ q + 1 (t is a positive integer) is S, S− (q + 1) + i is output, and the input is performed by the eighth adding means 702 having a word length of t bits. And the output of the first comparing means 701 are added and output.

As a result, the second shaping filter can be realized by the comparing means and the adding means instead of the remainder operation, and the circuit size can be further reduced.

(Embodiment 5) FIG. 8 is a block diagram showing a configuration of a second shaping filter of a D / A converter according to Embodiment 5 of the present invention. In this embodiment,
Second Embodiment of Sub-Noise Shaper 301 in Third Embodiment
Is realized by a different configuration. The other configuration is the same as that of the third embodiment, and therefore only the differences will be described.

In FIG. 8, the second shaping filter 604 includes a second comparing means 801, a ninth adding means 802, a third comparing means 803, a tenth adding means 804, and an eleventh adding means. And an adder 805.

Hereinafter, the operation of the second shaping filter 604 in the i-th sub-noise shaper 301 of the q filters will be described as an example. The second comparing means 801 constituting the second shaping filter 604 has one input of the second shaping filter 604, that is, the second comparing means 801.
The value Z1 held by the delay means 601 of the first shaping filter 206 in the noise shaper 203 of FIG.
+ 1−i), i is output and Z1 ≧ (q + 1−
In the case of i), when the minimum integer satisfying S = 2 ^t ≧ q + 1 (t is a positive integer) is S, S− (q + 1) + i is output. Similarly, the third comparison unit 803 determines that the other input of the second shaping filter 604, that is, the holding value Z2 of the delay unit 602 of the shaping filter 206 in the second noise shaper 203 is Z2 <(q + 1-i).
In the case of, i is output. In the case of Z2 ≧ (q + 1−i), when the minimum integer satisfying S = 2 ^t ≧ q + 1 (t is a positive integer) is S, S− (q + 1) + i Is output.

The ninth adding means 802 adds the second comparing means 801 and the input held value Z1. Also, the third comparing means 803 and the input held value Z2 are
The value is added by the adding means 804 of 0. Then, in the eleventh adding means 805, the output M1 of the ninth adding means 802 is output.
From the value obtained by doubling the output M2 of the tenth adding means 804
Is subtracted and output.

As a result, even in the second-order filter, the second shaping filter can be realized by the comparing means and the adding means in place of the remainder operation, and the circuit scale can be further reduced.

Although the above embodiments have been described in detail up to the level of the adding means, the present invention is not limited to the above circuit configuration, but can be realized by an equivalent circuit configuration. Needless to say,

Also, in each of the above embodiments, the sub-decoder is based on the output of the first conversion means 202 and the output of the delay means of the second noise shaper 203 (the configuration requirement of the first shaping filter 206). ROM (Read Only Memor) that stores the result of arithmetic processing as data in advance
It may be constituted by a semiconductor memory such as y).

[0067]

As described above, according to the present invention, instead of a plurality of second noise shapers constituting a decoder,
By providing a sub-noise shaper in which the quantization means and the shaping filter are simplified, it is possible to reduce the circuit scale while maintaining the same performance as the conventional one.

Also, the number of sub-noise shapers can be reduced by subtracting some of the sub-noise shapers from the input without having all the sub-noise shapers and outputting the result instead of the sum of the other sub-noise shapers. As a result, the circuit size can be further reduced.

Further, the configuration of the shaping filter in the sub-noise shaper is not calculated by performing the remainder operation, but by changing the value to be added according to the result of comparison between the input value and a fixed value. Is performed, the circuit scale can be further reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a D / A conversion device according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a decoder of the D / A converter.

FIG. 3 is a block diagram showing a configuration of a sub-decoder in the decoder of the D / A converter.

FIG. 4 is a block diagram showing a configuration of a sub-decoder in a decoder of a D / A converter according to a second embodiment of the present invention.

FIG. 5 is a block diagram showing a configuration of a second noise shaper and a sub-noise shaper in a decoder of the D / A converter according to the first and second embodiments of the present invention.

FIG. 6 is a block diagram showing a configuration of a second noise shaper and a sub-noise shaper in a decoder of the D / A converter according to the third embodiment.

FIG. 7 is a block diagram showing a configuration of a second shaping filter in a sub-noise shaper according to the fourth embodiment;

FIG. 8 is a block diagram showing a configuration of a second shaping filter in a sub-noise shaper according to the fifth embodiment.

FIG. 9 is a block diagram showing a configuration of a conventional D / A converter.

FIG. 10 is a block diagram showing a configuration of a decoder of a conventional D / A converter.

[Explanation of symbols]

 Reference Signs List 102 digital filter 103 first noise shaper 104 decoder 105 1-bit D / A converter sequence 106 first addition means 202 first conversion means 203 second noise shaper 207 sub-decoder 208 second conversion means 301 sub-noise Shaper

Claims (9)

[Claims] 1. An unnecessary band of an inputted digital signal is attenuated, and a sampling frequency is multiplied by p (p ≧ 2).
A first noise shaper that limits a word length of an output signal of the digital filter, and converts requantization noise generated when the word length is limited into a predetermined frequency characteristic; Decoding means for converting an output signal of the noise shaper into a plurality of 1-bit signal strings; a 1-bit D / A conversion string for converting each 1-bit signal string of the decoding means into an analog signal; First adding means for adding the output of the conversion sequence, wherein the decoding means converts k values (k is a positive integer) output by the first noise shaper into an integer value of 0 or more. A first transforming means, a second noise shaper for limiting a word length of an output of the first transforming means, and transforming requantization noise generated at the time of the word length limitation into a predetermined frequency characteristic; The first change A D / A conversion device comprising: a sub-decoder for performing a predetermined arithmetic processing on the output of the means and the output of the second noise shaper; and second conversion means for converting the output of the sub-decoder into a 1-bit signal sequence. . 2. The method according to claim 1, wherein the second noise shaper includes at least one noise shaper.
A first shaping filter having the above delay means, a second adding means for adding an output of the first converting means and an output of the first shaping filter,
3. The D / D converter according to claim 1, further comprising: first quantization means for quantizing an output of said addition means and outputting a quantization error together with a quantization output, and inputting said quantization error to said first shaping filter. A conversion device. 3. The sub-decoder comprises: q (q ≧ k−1) sub-noise shapers each having an input of an output of the first conversion means and an output of a delay means of the second noise shaper; A second noise shaper and the third sub-noise shaper, the output of the q number of sub-noise shapers, and m additions, and a third addition means for outputting n addition results. It has the same characteristics as the noise shaper, and has an offset i (1 ≦ i ≦ 1) independent of the output value Z of the delay means of the first shaping filter.
q), a second shaping filter having a remainder obtained by dividing (Z + i) by (q + 1) as an output value of the virtual delay means, an output of the first conversion means and a second shaping filter. A fourth adding means for adding the output and a second quantizing means having the same characteristics as the first quantizing means and for quantizing the output of the fourth adding means. The D / A converter according to claim 2, wherein 4. The sub-decoder has q × (n−1) / n (q ≧ k−1) inputs of the output of the first conversion means and the output of the delay means of the second noise shaper, respectively. , And q / n virtual noise shapers are added to the q × (n−1) / n noise shapers, and when viewed as q noise shapers, m out of every n are taken out, Fifth addition means for adding outputs other than the virtual noise shaper and outputting n-1 addition results, and sixth means for subtracting the sum of outputs of the fifth addition means from the first conversion means. The sub-noise shaper has the same characteristic as the second noise shaper, and has an independent offset i (1 ≦ i ≦ 1) with respect to the output value Z of the delay means of the first shaping filter.
q), a second shaping filter having a remainder obtained by dividing (Z + i) by (q + 1) as an output value of the virtual delay means, an output of the first conversion means and a second shaping filter. A fourth adding means for adding the output and a second quantizing means having the same characteristics as the first quantizing means and for quantizing the output of the fourth adding means. The D / A converter according to claim 2, wherein 5. The first shaping filter has a transfer characteristic described by z ⁻¹ , and the first quantizing means sets 0 if the input of the first quantizing means is negative, In this case, 1 is output as a quantization output, and the remainder obtained by dividing the input of the first quantization means by (q + 1) is output as a quantization error output. The second shaping filter outputs the second noise When the output value of the delay means of the first shaping filter in the shaper is Z, a remainder obtained by dividing (Z + i) by (q + 1) is output, and the second quantization means outputs the input of the second quantization means. 5. The method according to claim 2, wherein 0 is output as a quantized output when is negative and 1 is output when it is positive.
/ A converter. 6. The first shaping filter is 2z ⁻¹
−z ⁻² , and the first quantizing means is -1 if the input of the first quantizing means is negative, and is -1 if the input of the first quantizing means is positive. Input (q
If the quotient divided by +1) is 2 or more, 2 is output as the quantized output if it is less than 2, and (q + 1) is added if the input of the first quantizing means is negative. If the result is positive, the remainder obtained by dividing the input by (q + 1) is output as a quantization error output. The second shaping filter outputs z of the delay means of the first shaping filter in the second noise shaper.
^Assuming that the output value of the ^-1 term is Z1 and the output value of the z ^-2 term is Z2, the remainder M1 obtained by dividing (Z1 + i) by (q + 1) and the remainder M2 obtained by dividing (Z2 + i) by (q + 1). And outputs 2 × M1−M2. The second quantizing means outputs −1 when the input of the second quantizing means is negative, and outputs the input of the second quantizing means when the input is positive. To (q
5. The D / A converter according to claim 2, wherein the quotient divided by +1) is 2 or more, and the quotient is outputted as a quantized output if it is less than 2. 7. A second shaping filter in an i-th (1 ≦ i ≦ q) sub-noise shaper, wherein Z is an output value of delay means of the first shaping filter in the second noise shaper. If <(q + 1−i), i is output, and if Z ≧ (q + 1−i), S = 2
Assuming that a minimum integer satisfying ^t ≧ q + 1 (t is a positive integer) is S, a first comparing unit that outputs S− (q + 1) + i, and an output of the first converting unit and the first comparing unit The D / A converter according to claim 5, further comprising: an eighth adding means having a word length of t bits for adding outputs of the means, and outputting an operation result of the eighth adding means. 8. A second shaping filter in an i-th (1 ≦ i ≦ q) sub-noise shaper, when output values of delay means of the first shaping filter in the second noise shaper are Z1 and Z2. , Z1 <
In the case of (q + 1-i), i is output, and Z1 ≧ (q + 1-i)
In the case of i), a second comparing means that outputs S− (q + 1) + i when the minimum integer satisfying S = 2 ^t ≧ q + 1 (t is a positive integer) is S, and Z2 <(q + 1−i) ), I is output, and Z2 ≧ (q
+ 1-i), S = 2 ^t ≧ q + 1 (t is a positive integer)
A third comparing means for outputting S− (q + 1) + i when the minimum integer that becomes is S, and a word length of t bits for adding the output Z1 of the delay means and the output of the third comparing means is A ninth adding means having; a tenth adding means having a word length of t bits for adding the output Z2 of the delay means and the output of the fourth comparing means; and an output of the ninth adding means being 2 7. The D / A conversion according to claim 6, further comprising: eleventh adding means for subtracting the output of said tenth adding means from the multiplied result, and outputting the output of said eleventh adding means. vessel. 9. The sub-decoder is configured by a storage unit that stores in advance as a data a result of an arithmetic processing based on an output of the first conversion unit and an output of the delay unit of the second noise shaper. Item 9. A D / A converter according to any one of Items 1 to 8.