JP2001022315A - Opto-electronic device, driving method and electronic device therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate the need for providing each pixel with capacitance of a large capacity value, and realize gradation display in each pixel unit, by providing this device with plural drive signal generating circuits which generate driving signals of time lengths according to analog gradation voltages corresponding to plural pixels and supply them to each pixel. SOLUTION: A drive signal generating circuit 16 is comprised of a sampling circuit 20, a level judgment circuit 30, and an on-off selecting circuit 40. And, the drive signal generating circuit 16 generates a driving signal Vij of a time length according to an analog gradation voltage VAij, and supplies it to a pixel electrode 13 for gradation display. Here, in order for each pixel Qij to obtain a drive signal Vij of a time length according to an analog gradation voltage VAij, a time constant comprised of a capacitor 22 and a resister 23 has only to be one frame period or so, therefore the capacitor 22 does not need to have a large capacity value. Namely, it is possible to display gradation for each pixel without providing each pixel with large capacitance.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an electro-optical device and an electronic apparatus using the electro-optical device for a display device.

[0002]

2. Description of the Related Art As is well known, an active matrix type liquid crystal display, which is an example of an electro-optical device, has a liquid crystal sandwiched between an element substrate and a counter substrate. Here, on the element substrate, a plurality of data lines, a plurality of scanning lines intersecting these data lines, and pixels located at intersections of the respective data lines and the respective scanning lines are formed. Each pixel is composed of a pixel electrode and a switching element. The switching element in each pixel conducts when a selection voltage is output to a scanning line corresponding to the pixel, and plays a role of applying a data signal supplied to a data line corresponding to the pixel to a pixel electrode.

In such a configuration, for example, a selection voltage is applied to a scanning line in each horizontal scanning period within one frame (one vertical scanning) period, and the selection voltage is sequentially supplied to a plurality of scanning lines in one frame period. You. Then, while the selection voltage is being output to each scanning line, an analog grayscale voltage corresponding to the display grayscale of each pixel is sequentially output to the plurality of data lines, and a series of pixels arranged along the scanning line are output. An analog gradation voltage is applied to the pixel electrode.

In this manner, during one frame period, an analog gray scale voltage corresponding to the display gray scale of each pixel is applied to the pixel electrodes of all the pixels, and a display gray scale corresponding to the analog gray scale voltage is applied. Is performed.

[0005] In many liquid crystal display devices, it is general that an analog gray scale voltage is applied to each pixel electrode once in one frame period. The analog gray scale voltage applied to the pixel electrode is constituted by the pixel electrode, the counter electrode, the liquid crystal sandwiched between the pixel electrode and the storage capacitor formed as needed with the pixel electrode. It is stored in a capacitor (hereinafter referred to as a pixel capacitor for convenience).

However, after the application of the analog gray scale voltage, the leak current flows out from the pixel electrode to the other, so that the holding voltage of the pixel capacitance gradually decreases. If the holding voltage of the pixel capacitor seems to decrease too much during one frame period, a problem such as a decrease in contrast occurs.

In order to solve this problem, a configuration in which a storage capacitor is formed on an element substrate and connected to each pixel electrode is generally adopted.

According to this configuration, since the analog gray scale voltage applied to the pixel electrode is held by the combined capacitance of the pixel capacitor and the storage capacitor, the rate of decrease of the held voltage due to the leak current is reduced, and A reduction in the holding voltage of the pixel electrode during the frame period can be suppressed.

[0009]

In order to perform accurate gradation display in the above-described electro-optical device, it is necessary to suppress a decrease in the analog gradation voltage held in each pixel electrode. For that purpose, it is necessary to increase the capacitance value of the above-mentioned storage capacitance. However, it is sometimes difficult to provide a storage capacitor having such a large capacitance value due to restrictions on the size of pixels, the pitch between pixels, and the like. Particularly, when a liquid crystal display device is formed by forming fine pixels on a semiconductor substrate by a semiconductor manufacturing process such as an LSI, it is difficult to form a storage capacitor having a large capacitance value. Further, in the above-described conventional liquid crystal display device, the charge and discharge of the storage capacitor are performed each time an analog grayscale voltage is applied to each pixel electrode, which causes a problem of increasing power consumption of the liquid crystal display device. Was.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-described circumstances, and does not require providing a large capacitance value for each pixel, and provides an electro-optical device capable of performing gradation display for each pixel. It is an object to provide an electronic device using the electro-optical device.

[0011]

According to the present invention, there are provided a plurality of pixels, an analog gradation voltage generating means for outputting an analog gradation voltage corresponding to a gradation represented by the plurality of pixels, and a plurality of the plurality of pixels. A plurality of drive signal generation circuits provided for each of the pixels, each of which generates a drive signal having a time length corresponding to an analog gray scale voltage corresponding to the pixel and applies the drive signal to each of the pixels. An electro-optical device is provided.

According to another aspect of the present invention, there is provided a method of driving an electro-optical device including a plurality of pixels, wherein each of the plurality of pixels generates an analog gradation voltage corresponding to a gradation represented by the plurality of pixels. An object of the present invention is to provide a driving method of an electro-optical device, wherein a driving signal having a time length corresponding to an analog gradation voltage corresponding to each of the driving signals is generated and applied to each of the pixels.

According to the present invention, the drive signal generation circuit provided for each pixel generates a drive signal having a time length corresponding to the analog gray scale voltage, thereby controlling the display gray scale for each pixel. be able to. Here, the drive signal generation circuit can be composed of a circuit having a time constant of, for example, about one frame period and a level determination circuit, but the capacity for constituting the time constant circuit may be relatively small. Therefore, according to the present invention, it is possible to perform gradation display for each pixel without providing a large capacitance value for each pixel.

In the present invention, the analog gradation voltage generating means includes a memory for storing a plurality of pixel data for designating a display gradation of the plurality of pixels, a control means for reading the pixel data from the memory, and the memory. And D / A conversion means for converting the pixel data read out from the pixel data into an analog gradation voltage. Therefore, it is not necessary to provide a memory circuit for each pixel, and the pixel can be miniaturized.

The drive signal generation circuit may include a sampling circuit that captures and holds the analog grayscale voltage, and a level that outputs a drive signal during a period when the analog grayscale voltage held by the sampling circuit exceeds a threshold value. It can be constituted by a judgment circuit. Therefore, the number of circuit elements provided in the pixel can be small.

Each pixel includes, for example, a pixel electrode, a counter electrode, and an electro-optical material sealed between the pixel electrode and the counter electrode. In this case, the drive signal generation circuit supplies the drive signal to the pixel electrode.

In addition, the pixel may be provided with a reflection mirror and a reflection mirror driving section for driving the reflection mirror by receiving a drive signal and performing pixel display by the reflection mirror. In this case, the drive signal generation circuit supplies a drive signal to the reflection mirror drive unit.

The electro-optical device according to the present invention is manufactured and sold by itself, and is used as a display device of various electronic devices such as a projector and a computer.

[0019]

Embodiments of the present invention will be described below with reference to the drawings.

A. First Embodiment (1) Overall Configuration FIG. 1 is a block diagram showing the configuration of an electro-optical device according to a first embodiment of the present invention. As shown in FIG. 1, the electro-optical device includes a liquid crystal panel 1 and a frame memory 2.
, A D / A converter 3, a selection circuit 4, and a controller 5 as control means.

Here, the liquid crystal panel 1 is an example of an electro-optical device, and specifically, is a reflection type liquid crystal panel in which liquid crystal as an electro-optical material is sealed between an element substrate and a counter substrate. As liquid crystal, besides twisted nematic liquid crystal,
Various liquid crystals such as a liquid crystal of a horizontal alignment type without a twist, a liquid crystal of a vertical alignment type, a memory type liquid crystal such as a ferroelectric liquid crystal, and a polymer dispersed type liquid crystal can be used.

This liquid crystal panel 1 has pixels Qij (i = 1 to M, j = 1 to N) composed of M rows and N columns. Each of these pixels includes a pixel electrode provided on an element substrate, a liquid crystal interposed between the pixel electrode and a counter substrate, and a drive signal generation circuit that generates a drive signal and applies the signal to the pixel electrode. It is configured. The configuration of each pixel will be described later in detail.

In the liquid crystal panel 1, M parallel data lines 11-1 to 11-M and N parallel selection lines 12-1 to 12-N crossing the M data lines 11-1 to 11-M are formed. . Here, each data line 11-i is a wiring for transmitting an analog gradation voltage for determining a display gradation in a pixel, and is connected to N pixels Qij (j = 1 to N) in the same row. Have been. Each selection line 12-j is a wiring for transmitting a selection pulse Jj for instructing writing of an analog grayscale voltage, and includes M pixels Qij in the same column.
(I = 1 to M).

Each pixel Qij (i = 1 to M, j = 1)
To N) include an on-voltage VO for turning on the pixel.
N and an off voltage VOFF for turning off the pixel are supplied.

The drive signal generating circuit provided in each pixel Qij receives the selection pulse Jj via the selection line 12-j, thereby sampling the analog gradation voltage from the data line 11-i, A drive signal having a time length corresponding to the adjustment voltage is generated and applied to the pixel electrode. The voltages VON and VOFF are voltages for driving the pixels to the display ON state and the OFF state, and correspond to the active level and the deactive level of the drive signal, respectively.

The frame memory 2 is a storage device for storing image data of an image for one screen to be displayed by the liquid crystal panel 1. The image data for one screen is composed of M × N pixel data Pij (i = 1 to M, j) corresponding to the pixels Qij (i = 1 to M, j = 1 to N) of the liquid crystal panel 1.
= 1 to N). Each pixel data Pi
j is digital data of a predetermined number of bits that specifies the display gradation of the pixel Qij. These pixel data Pij
Is supplied from the outside, is stored in each storage area of the frame memory 2, and is supplied with pixel data Pi newly supplied from the outside in response to a request for rewriting the display image on the screen.
j is stored in the storage area corresponding to the pixel to be rewritten.

The frame memory 2 has M data ports, through which M pixel data Pij (i = 1 to M) in the same column can be read out in parallel. Is possible. In the present embodiment, under the control of the controller 5, the pixel data P
ij (i = 1 to M, j = 1 to N) are sequentially read from the frame memory 2 in column units during one frame period. More specifically, in each frame period, first, M pixel data Pi1 (i = 1 to M) in the first column are read, and then M pixel data Pi2 (i) in the second column. = 1
M) is read, and finally, the M pixel data PiN (i = 1 to M) in the Nth column are read, and so all the pixel data takes one frame period. It is read from the memory 2. Note that even if the frame memory 2 does not have M data ports, L (L <
M) data ports, the M pixel data is divided and sequentially output from the L ports, and this is sequentially stored in a register capable of holding the M pixel data, and the M pixel data is You may be comprised so that output is possible simultaneously.

The D / A converter 3 is composed of M D / A converters (hereinafter abbreviated as DACs) 3-i (i = 1 to M). Each of the DACs 3-i (i = 1 to M) stores pixel data Pij (i) read from the frame memory 2.
= 1 to M) into an analog voltage and output as an analog gradation voltage VAij (i = 1 to M). Each DAC3-
i (i = 1 to M), the analog gradation voltage VA output from
ij (i = 1 to M) are the data lines 11-of the liquid crystal panel 1.
i (i = 1 to M).

If it is costly to have M DACs 3-i, the number of data ports of the frame memory 2 is set to L and only the number of DACs 3-i is provided.
The M pieces of pixel data are divided and sequentially output from the L ports, and are converted into analog gradation voltages by the L DACs 3-i. Then, the L analog gradation voltages are converted into the M analog gradation voltages. The voltage may be sequentially held by a sample and hold circuit, so that M analog gray scale voltages can be simultaneously output. The selection circuit 4 sequentially generates selection pulses Jj (j = 1 to N) at regular time intervals during one frame period under the control of the controller 5,
This is a circuit for supplying to each of the selection lines 12-j (j = 1 to N) of the liquid crystal panel 1. The selection circuit 4 can be constituted by, for example, a shift register that sequentially shifts a selection pulse. When this shift register is used, a configuration may be adopted in which a selection pulse obtained from each stage of the shift register is supplied to a selection line 12-j (j = 1 to N).

The controller 5 is a device for controlling the operation of the entire electro-optical device in accordance with a command from a host device such as a host computer. The main control performed by the controller 5 is to rewrite the pixel data Pij in the frame memory 2 and to store the pixel data Pij (i = 1 to M,
There is a read control for reading j = 1 to N), a control for driving the selection circuit 4 at the beginning of each frame period, and sequentially generating selection pulses Jj (j = 1 to N) for N columns. .

The overall configuration of the electro-optical device according to the present embodiment has been described above.

(2) Configuration Example of Pixel Qij FIG. 2 shows a configuration example of the pixel Qij. Each pixel Qij has a pixel electrode 13, a counter electrode 14, a liquid crystal 15, and a drive signal generation circuit 16. The liquid crystal panel of the present invention is configured by bonding an element substrate and a counter substrate with a gap therebetween, and sealing a liquid crystal 15 into the gap. As the element substrate, a semiconductor substrate or an insulating transparent substrate such as glass is used, and as the counter substrate, a transparent substrate is used. When the element substrate is a semiconductor substrate, a circuit element constituting the drive signal generation circuit 16 of each pixel can be formed by a MOS transistor, a resistor, and a capacitor, which will be described later, formed on the semiconductor substrate. In the upper layer, the reflective pixel electrodes 13 can be arranged in a matrix so as to cover the circuit elements. When a transparent substrate is used, the circuit element can be formed by a thin film transistor formed of a metal or silicon thin film formed on the substrate, a resistor, and a capacitor. In the case of a transparent substrate, a reflection type liquid crystal panel is provided with a reflection type pixel electrode above the circuit element, and a transmission type liquid crystal panel is formed of a transparent conductive film such as ITO in a region having no circuit element. It is configured by arranging pixel electrodes.

In this embodiment, the reflective pixel electrode 13
As an example, an electrode was used in which an Al layer was formed on an element substrate as a semiconductor substrate, and the Al layer was patterned. Note that a configuration in which a transparent conductive film is used as the pixel electrode 13 and a reflective film made of a dielectric multilayer film or the like is disposed below the transparent conductive film may be used. The counter electrode 14 is made of a transparent conductive film such as ITO provided on the above-described counter substrate, and faces the pixel electrode 13 at a predetermined interval. This counter electrode 14 has
An off voltage VOFF is supplied. The liquid crystal 15 is sandwiched between the pixel electrode 13 and the counter electrode 14.

Here, the drive signal generating circuit 16 includes an FET (Field) formed on the element substrate together with the pixel electrode 13.
Effect Transistor: field effect transistor), capacitance,
It is composed of a resistor.

The drive signal generation circuit 16 is connected to the pixel Q
An analog gray scale voltage corresponding to ij is received via the data line 11-i, and a drive signal Vij having a time length corresponding to the analog gray scale voltage is generated and supplied to the pixel electrode 13.

To fulfill this role, the drive signal generation circuit 16 includes a sampling circuit 20 and a level determination circuit 30.
And an ON / OFF selection circuit 40.

The sampling circuit 20 includes an N-channel transistor 21, a capacitor 22, and a resistor 23. Here, the source (or the drain) of the N-channel transistor 21 is connected to the data line 11-i, and the drain (or the source) is the capacitor 22 and the resistor 2.
3 is grounded. A selection line 12-j formed by stacking polycrystalline silicon or a high melting point metal on the polycrystalline silicon forms a gate of the N-channel transistor 21.

The N-channel transistor 21 is connected to the selection line 1
While the high level voltage of the selection pulse Jj is applied to the gate via 2-j, the transistor is turned on. During this time, the analog gradation voltage output to the data line 11-i is applied to the capacitor 22 via the N-channel transistor 21 and is held by the capacitor 22. The capacitor 22 may be formed by laminating two conductive layers on an element substrate via an insulating film, or, in the case of a semiconductor substrate, a diffusion layer and a conductive layer opposed to each other via the same insulating film as a gate insulating film. And can be constituted by With the resistor 23, the voltage VHij at the connection point between the drain of the N-channel transistor 21 and the capacitor 22
Can be reduced to reduce power consumption by charging and discharging in the capacitor 22, but the resistor 23 may not be provided.

The level determination circuit 30 is composed of an N-channel transistor 31 and a resistor 32. Here, the source of the N-channel transistor 31 is grounded, the drain is pulled up to the power supply Vcc by the resistor 32, and the gate is connected to the drain of the N-channel transistor 21.

A leak resistance (not shown) is interposed between the gate of the N-channel transistor 31 and the ground line.
Therefore, the electric charge held in the capacitor 22 of the sampling circuit 20 is discharged to the ground line through the leak resistance. Therefore, the voltage VHi held in the capacitor 22
Thereafter, j gradually decreases. In addition,
Even if a leak resistance is not used, a time constant circuit using the high resistance and the capacitor 22 may be formed by using a polycrystalline silicon layer not doped with an impurity as a high resistance.

The level judgment circuit 30 is a circuit for judging the level of the analog gradation voltage held in the capacitor 22. That is, when the voltage VHij held in the capacitor 22 of the sampling circuit 20 exceeds a predetermined threshold, the N-channel transistor 31 is turned on, and the output signal Sij of the level determination circuit 30 becomes low. On the other hand, when the voltage held in the capacitor 22 is equal to or lower than the threshold, the N-channel transistor 31 is turned off, and the output signal Sij of the level determination circuit 30 becomes high.

The ON / OFF selection circuit 40 includes transmission gates 41 and 42 and an inverter 43. Transmission gates 41 and 42 have a well-known configuration combining a P-channel transistor and an N-channel transistor.
Inverter 43 is also a well-known CM using one P-channel transistor and one N-channel transistor.
It is an OS inverter.

Transmission gates 41 and 42
Are connected to a line for supplying the ON voltage VON and a line for supplying the OFF voltage VOFF, respectively.
Output terminals of the transmission gates 41 and 42 are commonly connected to the pixel electrode 13. The output signal Sij of the level determination circuit 30 is supplied to the gate of the P-channel transistor of the transmission gate 41, and the same signal Sij is supplied to the gate of the N-channel transistor.
Is inverted by an inverter 43. On the other hand, the signal obtained by inverting the output signal Sij of the level determination circuit 30 by the inverter 43 is supplied to the gate of the P-channel transistor of the transmission gate 42, and the same signal Sij is supplied to the gate of the N-channel transistor as it is. Therefore, when the output signal Sij of the level determination circuit 30 is at a low level, the transmission gate 41 is turned on, the transmission gate 42 is turned off, and the on-voltage VON passes through the transmission gate 41, so that the drive signal Vij It is applied to the pixel electrode 13. On the other hand, when the output signal Sij of the level determination circuit 30 is at a high level, the transmission gate 42
Is turned on, the transmission gate 41 is turned off, and the off voltage VOFF is applied to the pixel electrode 13 via the transmission gate 42. Note that a buffer for driving the transmission gates 41 and 42 may be additionally provided.

(3) Operation of the present embodiment FIG. 3 is a time chart showing the operation of the present embodiment.
FIG. 4 is a waveform chart showing waveforms at various parts in the pixel Qij. Hereinafter, the operation of the present embodiment will be described with reference to these drawings.

In the present embodiment, under the control of the controller 5, pixel data Pij (i = 1 to M, j
= 1 to N) are transferred from the frame memory 2 to the D / A conversion unit 3 in column units during one frame period. More specifically, in a certain frame period Fk, first, M
Pixel data Pi1 (i = 1 to M) are transferred, then M pixel data Pi2 (i = 1 to M) in the second column are transferred, and this is sequentially repeated, and finally the Nth column The M pieces of pixel data PiN (i = 1 to M) of the eye are transferred, so that all the pixel data for one screen is transferred from the frame memory 2 to the DAC 3-i (i = 1 to M) during one frame period.
M). The same applies to other frame periods.

The pixel data Pij (i = 1 to M, j = 1 to N) transferred to the DAC 3-i (i = 1 to M) is converted to an analog gradation voltage VAij (i = 1 to M, j = 1). To N) and the data line 11-i (i = 1 to 1) of the liquid crystal panel 1.
M).

In parallel with this, the selection circuit 4 sequentially generates selection pulses Jj (j = 1 to N) and supplies them to the selection lines 12-j (j = 1 to N) of the liquid crystal panel 1, respectively. Each of the selection pulses Jj has the analog grayscale voltage VAij (i = 1 to M) corresponding to M pixels (that is, one column) is connected to the data line 1.
1-i (i = 1 to M) and are output to the corresponding selection lines 12-j in synchronization with the output.

That is, when the analog gradation voltage VAi1 (i = 1 to M) corresponding to the M pixels in the first column is output to the data line 11-i (i = 1 to M), the selection pulse is output. J1 is output to the selection line 12-1, and the analog gradation voltage VAi2 (i = 1 to M) corresponding to the M pixels in the second column
Is output to the data line 11-i (i = 1 to M), the selection pulse J2 is output to the selection line 12-2, and this is sequentially repeated to correspond to the M pixels in the last Nth column. The analog grayscale voltage VAiN (i = 1 to M) is applied to the data line 1
1-i (i = 1 to M) when selected pulse J
N is output to the selection line 12-N.

In each of the pixels Qij, a drive signal Vij having a time length corresponding to the level is generated from the analog gradation voltage VAij thus applied, and applied to the pixel electrode 13. This operation will be described below with reference to FIG.

In each pixel Qij, one pixel Qij
The N-channel transistor 2 via the selection line 12-j
A selection pulse Jj is applied to one gate. While the selection pulse Jj is applied, the N-channel transistor 21
Is turned on, and the analog grayscale voltage VAij output to the data line 11-i is applied to the capacitor 22 via the N-channel transistor 21. The applied voltage is held by the capacitor 22 when the N-channel transistor 21 is turned off.

At this time, the voltage VHi held in the capacitor 22
When j exceeds the threshold value of the N-channel transistor 31, the N-channel transistor 31 is turned ON, and O
The ON voltage VON is selected by the N / OFF selection circuit 40 and applied to the pixel electrode 13 as a drive signal Vij.

Thereafter, the holding voltage VHij of the capacitor 22 is
It gradually decreases due to leak resistance or high resistance interposed between the gate of the N-channel transistor 31 and the ground line.

When the holding voltage VHij of the capacitor 22 becomes N
When the voltage falls below the threshold value of the channel transistor 31, the N-channel transistor 31 is turned off and turned on / off.
The OFF voltage VOFF is selected by the F selection circuit 40,
It is applied to the pixel electrode 13.

FIG. 4 shows a case where the analog gradation voltage VAij corresponding to the display gradation 100% is applied to the pixel Qij, and a case where the analog gradation voltage VAi corresponding to the display gradation 50%.
The waveform of each part is illustrated for each case where j is given to the pixel Qij.

As shown in this figure, a large analog gradation voltage VAij corresponding to a display gradation of 100% is applied to the pixel Qij.
, The voltage VH held in the capacitor 22
ij is large, and the period during which the holding voltage VHij exceeds the threshold value of the N-channel transistor 31 becomes long. Therefore, the ON voltage VON (drive signal Vij) is maintained for a long period of time.
Is applied to the pixel electrode 13. On the other hand, display gradation 5
When a small analog gradation voltage VAij corresponding to 0% is applied to the pixel Qij, the voltage VHij held in the capacitor 22 is small, and the period during which the held voltage VHij exceeds the threshold value of the N-channel transistor 31 is determined. It is shorter than in the case of 100% display gradation. Therefore, in this case, the time during which the ON voltage VON (drive signal Vij) is applied to the pixel electrode 13 is shorter than in the case where the display gradation is 100%.

In each pixel Qij, light from the counter electrode 15 side is incident on the pixel electrode 13 via the liquid crystal 14, and this incident light is reflected by the pixel electrode 13, and the reflected light passes through the liquid crystal 15 and the counter electrode 14. Output via In each pixel Qij, while the drive signal Vij is applied to the pixel electrode 13, the transmittance of the liquid crystal 15 held between the pixel electrode 13 and the counter electrode 14 changes from the initial state. Therefore, the effective intensity of light reflected by the pixel electrode 13 of each pixel Qij and emitted from the counter substrate side depends on the application time of the drive signal Vij to the pixel electrode 13 of the pixel Qij. In this way, display is performed for each pixel Qij at a display gradation corresponding to the pixel data Pij.

As described above, according to the present embodiment, each pixel Q
The drive signal generation circuit 16 provided for each ij generates a drive signal Vij having a time length corresponding to the analog grayscale voltage VAij, and the grayscale display is performed by the drive signal Vij. Here, the analog gradation voltage V in each pixel Qij
In order to obtain a drive signal Vij having a time length corresponding to Aij, the time constant constituted by the capacitor 22 and the resistor may be set to be about one frame period. There is no. That is, according to the present embodiment, gradation display can be performed for each pixel without providing a large capacitance in the pixel.

In the above description with reference to FIG.
Although the selection line 12-j is a column and the data line 11-i is a row,
This may be reversed. That is, the selection circuit 4 selects the selection line 12-j in the row direction, and supplies the pixel data Pij of one horizontal scanning line from the D / A conversion unit 3 to the data line 11-i in the column direction. Is also good.

(4) Driving Method for Performing AC Driving In the case of a liquid crystal panel, if driving is continuously performed with a DC voltage, dielectric polarization occurs in liquid crystal molecules, which causes deterioration in image quality. In order to avoid this problem, it is common to perform AC driving of the pixels.

Since the electro-optical device according to the present embodiment also uses liquid crystal as an electro-optical material, it is necessary to perform AC driving. Although various methods of this AC driving are conceivable, there are, for example, the following two methods.

<First Method> FIG. 5 is a time chart showing a first method for performing AC driving of each pixel of the liquid crystal panel 1.

In the first method, each time the frame period is switched, the ON voltage VON, which is the active level of the drive signal Vij, and the OFF voltage VOF applied to the common electrode.
Invert the polarity of F. That is, in FIG. 5, in a certain frame period Fk, a positive drive voltage is generated as the ON voltage VON, and a negative drive voltage is generated as the OFF voltage VOFF. At this time, what is applied to the counter electrode is a negative drive voltage, for example, used as the off voltage VOFF. Here, the polarity is based on the intermediate potential of the voltage amplitude applied to the pixel electrode. Then, in the next frame period Fk + 1, the ON voltage VON
The polarity of the OFF voltage VOFF is inverted, and a negative drive voltage is generated as the ON voltage VON and a positive drive voltage is generated as the OFF voltage VOFF. At this time, what is applied to the counter electrode is a positive drive voltage used as the off voltage VOFF. Thus, every time the frame period is switched, the polarity of the drive signal voltage (drive voltage) used as the ON voltage VON and the OFF voltage VOFF is inverted.

In each pixel Qij, the ON voltage VON is selected only for a period corresponding to the pixel data Pij and applied to the pixel electrode. This point is as described in the operation description section of the present embodiment.

If the polarity of the ON voltage VON and the polarity of the OFF voltage VOFF supplied to the selection circuit 40 are switched in accordance with the polarity inversion of the drive voltage, the number of circuit elements in the pixel can be reduced. For example, in the frame period Fk,
Positive drive voltage, off voltage VO as on voltage VON
A negative driving voltage is supplied as the FF, and the frame period F
At k + 1, a negative drive voltage is used as the ON voltage VON,
A positive drive voltage is supplied as the off voltage VOFF.

<Second Method> FIG. 6 is a waveform diagram showing a second method for performing AC driving of each pixel of the liquid crystal panel 1.

In the second method, 1/1 of the frame period
N (that is, the maximum time that can be used to drive one pixel) with an ON signal VON
Is supplied to each pixel Qij. Also, the on-voltage V
The DC voltage corresponding to the center potential of the ON amplitude is referred to as the OFF voltage V
It is supplied to each pixel Qij as OFF.
(A)).

The level determination circuit 30 of each pixel Qij (FIG. 2)
6), a signal Sij having a pulse width corresponding to the pixel data Pij is output (see FIG. 6B).
While j is maintained at the high level, the voltage VON is selected and applied to the pixel electrode 13 as the drive signal Vij (see FIG. 6C).

In this embodiment, the pixels are driven collectively in units of columns or rows, so that the driving time per pixel can be extended. Therefore, it is possible to perform AC driving as in the second method.

(5) Other Configuration Examples of Pixel Qij As for the pixel Qij, various configurations other than those shown in FIG. 2 are conceivable. FIGS. 7 to 9 show this pixel Q
ij shows another configuration example. In each of these drawings, the same reference numerals are given to portions corresponding to the respective portions in FIG. 2 described above, and description thereof will be omitted.

In the configuration example shown in FIG. 7, the N-channel transistor 21 in the first embodiment is replaced by a P-channel transistor 21A. When the selection pulse Jj supplied to the selection line 12-j is a negative pulse, the P-channel transistor 21A is used for the sampling circuit 20 as described above.

In the configuration example shown in FIG. 7, the level determination circuit 30 is composed of a P-channel transistor 33 and a resistor. Here, the source of the P-channel transistor 33 is connected to the power supply Vcc, the drain is pulled down by the resistor 34, and the holding voltage of the capacitor 22 is applied to the gate. Therefore, the selection pulse output from the selection circuit 4 to the selection line Jj is a low-level pulse.

When the hold voltage VHij of the capacitor 22 is high and the gate-source voltage of the P-channel transistor 33 is smaller than the threshold, the P-channel transistor 33 is turned off, and the low-level signal Sij is output from the level determination circuit 30. It is supplied to the ON / OFF selection circuit 40.

On the other hand, the discharge of the charge stored in the capacitor 22 proceeds, and the holding voltage VHij decreases, and the P-channel transistor 3
When the gate-source voltage of No. 3 becomes larger than the threshold value,
The P-channel transistor 33 is turned on, and a high-level signal Sij is output from the level determination circuit 30 to ON / OF.
It is supplied to the F selection circuit 40.

By such an operation, a drive signal Vij having a time length corresponding to the pixel data Pij is obtained as in the case shown in FIGS.

In the configuration example shown in FIG. 8, the level determination circuit 30 of the configuration shown in FIG.
It is replaced with an S inverter.

In this configuration, since the threshold level of the CMOS inverter is stable, the analog gradation voltage V
There is an advantage that the relationship between Aij and the pulse width of the drive signal Vij is stabilized. In addition, since the transistor is replaced with a transistor that turns on / off the resistor, the through current of the level determination circuit 30 can be reduced.

In the configuration example shown in FIG.
0 is configured by a source follower circuit including an N-channel transistor 31 and a resistor 32.

In this configuration, the holding voltage VAi of the capacitor 22
When j is high and exceeds the threshold value of the N-channel transistor 31, the N-channel transistor 31 is turned on, and a high-level signal Sij is supplied to the ON / OFF selection circuit 40.

The ON / OFF selection circuit 40 is provided with two inverters 44 and 45. The ON voltage VON is applied to the pixel electrode 13 via the transmission gate 41 while the signal Sij is at the high level, and the transmission gate 42 is applied during the low level.
Is applied to the pixel electrode 13 via the.

As described above, the same operation as that shown in FIG. 2 can be obtained in the structure shown in FIG. However, the configuration shown in FIG. 9 has a disadvantage that the number of inverters provided in the ON / OFF selection circuit 40 is one more.

The embodiments described above can be used in appropriate combinations as needed.

In each of the above embodiments, the ON voltage VON is applied to the pixel electrode from the front edge of the frame period. On the contrary, VOFF is applied to the front edge and VON is applied to the rear edge.
It may be set to ON. In this case, the driving signal (V
ON), the analog gray scale voltage V
Aij is low, and when shortening it, the analog grayscale voltage VAi is used.
Pixel data may be set so as to increase j.

In FIGS. 2, 7, 8, and 9, the capacitor 22 of the sampling circuit 20 is connected to the ground potential, but may be connected to the high potential Vcc. In that case, the waveform VHij in FIG. 2 changes in voltage to the negative side. Therefore, in this case, it is necessary to appropriately modify the circuit configurations of the level determination circuit 30 and the ON / OFF selection circuit 40 so that the time width of the Vij drive signal is the same as in the above embodiments. .

B. Second Embodiment In the first embodiment, the liquid crystal panel 1 is used as an electro-optical device. However, the application range of the present invention is not limited to such a liquid crystal panel. The present invention
The present invention can be applied to all electro-optical devices having pixels whose gradation can be controlled by pulse width modulation.

In the second embodiment of the present invention, the liquid crystal panel 1 in the first embodiment is replaced with a digital micro miller device (Digital Micro Miller Device;
MD (abbreviated as MD).

This DMD has a plurality of mirrors, each constituting a pixel, arranged in a matrix on a silicon substrate. FIG. 10 schematically shows the configuration of one pixel of the DMD. As shown in FIG. 10, one mirror 201 corresponding to one pixel is arranged on the surface of the silicon substrate 200. This mirror 20
Numeral 1 is fixed on the silicon substrate 200 so as to be able to turn around its center portion as a fulcrum, and in this example, it can turn by ± 10 ° from a horizontal state.
Adsorption electrodes 202A and 202B are formed on the silicon substrate 200 so as to face the left and right ends of the mirror 201, respectively. Each of the attracting electrodes 202A and 202B is provided with a driving unit 203A and a driving unit 203 formed on the silicon substrate 200.
3B, the mirror 20 is driven.
An electric field is generated that attracts the end of the first.

Each pixel is provided with a component corresponding to the drive signal generating circuit 16 (see FIG. 2) provided in each pixel of the first embodiment, in addition to that shown in FIG. Omitted). However, this drive signal generation circuit 16
It does not have an equivalent to the N / OFF selection circuit 40, and is constituted only by the sampling circuit 20 and the level determination circuit 30. Then, the output signal Sij from the level determination circuit 30 is supplied as it is as a drive signal or to the drive units 203A and 203B in FIG. 10 via a buffer circuit.

The driving section 203A applies a driving voltage to the attraction electrode 202A, and the driving section 203B applies a driving voltage to the attraction electrode 202A.
The application of the drive voltage to 2B is performed exclusively. That is, the drive signal Sij from the drive signal generation circuit 16 is at a low level only during a period corresponding to the pixel data Pij,
While the drive signal Sij is at a low level, a drive voltage is supplied from the drive unit 203A to the attraction electrode 202A. As a result, the end of the mirror 201 is attracted by the attracting electrode 202A, and the mirror 201 is inclined by 10 ° to the right in FIG. This is the state where the pixel Qij is on. Thereafter, when the drive signal Sij goes high, a drive voltage is supplied from the drive unit 203B to the attraction electrode 202B. As a result, the mirror 201 is moved by the attraction electrode 202B.
And the mirror 201 is tilted 10 ° to the left in FIG. This is the state where the pixel Qij is off.

FIG. 11 schematically shows the configuration of an optical system of an electro-optical device using this DMD. In addition, in this figure, in order to prevent complication, only one of the many mirrors 201 provided in the DMD is shown in an enlarged state. In FIG. 11, the DMD is irradiated with light. This light irradiation is performed from a direction inclined by 20 ° from the normal line of the DMD. Projection lens 210 in front of DMD
Is arranged. The mirror 201 of each pixel provided in the DMD, which is in the ON state, reflects the irradiation light in the direction of the normal line of the DMD, and projects the light through a lens 210 onto a screen (not shown). On the other hand, the mirror 201 of the pixel which is in the off state shifts the irradiation light by 40 degrees from the DMD normal line.
反射 Reflects in the inclined direction. In this manner, the projection of each pixel onto the screen is performed.

Each pixel is turned on for a time corresponding to the pixel data of the pixel, as in the first embodiment. Therefore, display gradation can be controlled for each pixel.

C. Third Embodiment Next, some examples in which the above-described embodiments are used for specific electronic devices will be described.

<Part 1: Projector> First, a projector using the electro-optical device in each of the above embodiments as a reflection type light modulator will be described. FIG. 12 is a plan view showing the configuration of this projector. As shown in this figure, inside the projector 1100, a polarized light illuminating device 1110 is arranged along the system optical axis PL. In the polarized light illumination device 1110, the lamp 111
The light emitted from the second integrator lens 2 is converted into a substantially parallel light beam by reflection by the reflector 1114, and the first integrator lens 11
20. As a result, the light emitted from the lamp 1112 is split into a plurality of intermediate light beams. The split intermediate light beam is converted by the polarization conversion element 1130 having the second integrator lens on the light incident side into one type of polarized light beam (s-polarized light beam) whose polarization direction is almost uniform,
The light is emitted from the polarized light illumination device 1110.

The s-polarized light beam emitted from the polarized light illumination device 1110 is reflected by the s-polarized light beam reflecting surface 1141 of the polarizing beam splitter 1140. Of the reflected light beam, the light beam of blue light (B) is the dichroic mirror 1
The light is reflected by the blue light reflection layer 151 and is modulated by the reflection type light modulation device 100B. Also, of the light flux transmitted through the blue light reflecting layer of the dichroic mirror 1151,
The luminous flux of the red light (R) passes through a dichroic mirror 1152
Of the reflection type light modulation device 10
Modulated by 0R. On the other hand, among the light beams transmitted through the blue light reflection layer of the dichroic mirror 1151, the light beam of green light (G) transmits through the red light reflection layer of the dichroic mirror 1152 and is modulated by the reflection type light modulation device 100G. .

Thus, the light modulators 100R, 100R,
The red, green, and blue lights, each of which is color-modulated by 00G and 100B, are output to a dichroic mirror 115.
2, 1151, and are sequentially synthesized by the polarizing beam splitter 1140, and then projected on the screen 1170 by the projection optical system 1160. It should be noted that dichroic mirrors 1151 and 1152 attach R, G, and B to the light modulators 100R, 100B, and 100G.
Since the luminous flux corresponding to each primary color is incident, a color filter is not required.

<Part 2: Mobile Computer> Next, an example in which the display device according to each of the above embodiments is applied to a mobile personal computer will be described.
FIG. 13 is a perspective view showing the configuration of this personal computer. In the figure, a computer 1200 includes a main body 1204 having a keyboard 1202 and a liquid crystal display unit 1206. The liquid crystal display unit 1206 is configured by adding a front light to the front surface of the liquid crystal panel 1 described above.

In this configuration, since the liquid crystal panel is used as a reflection direct-view type, for example, the pixel electrode 13 in the first embodiment does not need to be flat, but rather, the reflected light is scattered in various directions. It is desirable that the surface be uneven.

In addition to the electronic devices described with reference to FIGS. 12 and 13, the electronic devices include a liquid crystal television, a viewfinder type, a monitor direct-view type video tape recorder, and the like.
Car navigation devices, pagers, electronic organizers, calculators,
Word processors, workstations, video phones,
Examples include a POS terminal, a device equipped with a touch panel, and the like. It goes without saying that the electro-optical devices according to the first and second embodiments can be applied to these various electronic devices.

[0098]

As described above, according to the electro-optical device or the electronic apparatus according to the present invention, it is not necessary to provide a large capacitance value for each pixel, and gradation display can be performed for each pixel. .

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an electro-optical device according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a configuration example of a pixel in the embodiment.

FIG. 3 is a time chart showing the operation of the embodiment.

FIG. 4 is a waveform chart showing waveforms of various parts of the pixel in the same embodiment.

FIG. 5 is a time chart showing a first method for performing AC driving of pixels in the embodiment.

FIG. 6 is a waveform chart showing a second method for performing AC driving of pixels in the embodiment.

FIG. 7 is a diagram showing another configuration example of the pixel according to the embodiment.

FIG. 8 is a diagram showing another configuration example of the pixel according to the embodiment.

FIG. 9 is a diagram showing another configuration example of the pixel according to the embodiment.

FIG. 10 is a diagram illustrating a configuration of an electro-optical device according to a second embodiment of the invention.

FIG. 11 is a diagram showing a configuration of an optical system according to the embodiment.

FIG. 12 is a diagram showing a projector using the electro-optical device according to the invention.

FIG. 13 is a diagram showing a mobile computer using the electro-optical device according to the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Liquid crystal panel 2 ... Frame memory 3 ... D / A conversion part 4 ... Selection circuit 5 ... Controller Qij (i = 1-M, j = 1-N) ... Pixel 11-i (i = 1 to M) Data line 12-j (j = 1 to N) Selection line 20 Sampling circuit 30 Level determination circuit 40 ON / OFF selection circuit 13 Pixel electrode 14 Opposite Electrode 15: Liquid crystal

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G02F 1/1365 G09G 3/34 D G09G 3/34 3/36 3/36 G02F 1/136 500 F term ( (Reference) 2H091 FA05Z FA10Z FA14Y FA26Z FA41Z FD13 GA02 GA13 HA07 LA12 MA07 2H092 JA24 JB07 JB43 KA03 KA16 KB13 NA27 PA06 PA07 PA12 2H093 NA16 NA32 NA33 NA43 NA56 NC13 NC21 NC23 NC25 NC29 ND06 ND05 NE03 NB05 006 BF11 BF14 BF31 FA56 5C080 AA09 AA10 BB05 DD01 DD22 DD25 DD26 EE29 FF11 JJ02 JJ03 JJ04 JJ06

Claims (8)

[Claims] A plurality of pixels; an analog grayscale voltage generator for outputting an analog grayscale voltage corresponding to a grayscale represented by the plurality of pixels; and a plurality of analog grayscale voltage generators provided for each of the plurality of pixels. An electro-optical device comprising: a plurality of drive signal generation circuits for generating drive signals having a time length corresponding to an analog gray scale voltage corresponding to each of the pixels and applying the drive signals to each of the pixels. 2. The memory according to claim 2, wherein the analog grayscale voltage generation unit stores a plurality of pixel data specifying a grayscale represented by the plurality of pixels, a control unit that reads the pixel data from the memory, 2. The electro-optical device according to claim 1, further comprising: a D / A converter that converts pixel data read from the memory into an analog gray scale voltage. 3. A sampling circuit for acquiring and holding the analog gradation voltage, wherein the driving signal generation circuit outputs a driving signal during a period when the analog gradation voltage held by the sampling circuit exceeds a threshold value. The electro-optical device according to claim 1, further comprising a level determination circuit. 4. The pixel comprises: a pixel electrode; a counter electrode;
4. The device according to claim 1, further comprising an electro-optical material sealed between the pixel electrode and the counter electrode, wherein the drive signal generation circuit supplies the drive signal to the pixel electrode. Electro-optical device. 5. The pixel includes: a reflection mirror; and a reflection mirror driving unit that drives the reflection mirror by receiving a driving signal and performs pixel display by the reflection mirror. 4. The electro-optical device according to claim 1, wherein the driving signal is supplied to a reflection mirror driving unit. 6. A driving method for an electro-optical device including a plurality of pixels, wherein each of the plurality of pixels generates an analog gray scale voltage corresponding to a gray scale represented by the plurality of pixels, and corresponds to each of the plurality of pixels. And generating a drive signal having a time length corresponding to the analog gray scale voltage, and applying the drive signal to each of the pixels. 7. The electro-optical device according to claim 6, wherein the analog gray scale voltage is captured and held, and a drive signal is output while the held analog gray scale voltage exceeds a threshold. Drive method. 8. An electronic apparatus using the electro-optical device according to claim 1 for a display device.