JP2000349156A - Layout designing method and device of semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable the width of a wiring region between blocks to be accurately estimated in a short time in a layout design method where a block build-up system is used. SOLUTION: In this layout designing method, functional blocks 21A to 21E and input/output blocks 26A and 26D are arranged separate from each other by a certain space in an arrangement region 10, and a wiring grid region 31 composed of regions sandwiched in between a pair of adjacent tracks or columns is formed in wiring regions which are each located between the blocks. By the use of a labyrinth method where the wiring grid region 31 is considered as a wiring region, a wiring route in a wiring region between the blocks is searched. At this point, resting on circuit connection data, tracks occupied by wirings or vias passing through the unit wiring regions 31a of the wiring grid regions 31 are counted and held for each of the unit wiring counting regions 32a of wiring counting regions 32 corresponding to the wiring grid regions 31. By the use of the above discrete values, the width of a wiring region required for a wiring region between blocks can be estimated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a layout design method and a layout design apparatus for a semiconductor integrated circuit using a block building (building block) system.

[0002]

2. Description of the Related Art As the degree of integration of a semiconductor integrated circuit device is further increased, a large-scale and high-speed semiconductor integrated circuit device has been developed. Therefore, in order to design a highly integrated semiconductor integrated circuit device, a plurality of functional blocks as partial circuits are created in a hierarchical structure,
A block-level layout design method in which these functional blocks are arranged in a predetermined block arrangement area and the blocks are connected to each other by wiring has become essential. Conventionally, in order to determine the arrangement position of a block or a power supply wiring path, various methods described below are employed.

A first conventional method is a block-level layout design method based on a channel wiring system, in which channel wiring is performed between blocks, and the position of each block is determined based on the result of the channel wiring. By repeating these processes, a block arrangement position and a wiring result are obtained.

A second conventional method is a method in which an element formation region on a chip is divided into a plurality of partial regions, and wiring is performed for each of the divided partial regions by using a maze method.

According to the first conventional method, the channel region is necessarily secured by the wiring result even if each block is moved. However, as the size of the chip increases, the number of blocks, the number of terminals, and the number of wirings also increase, respectively, so that the hardware resources required by the layout design device, especially the memory capacity, and the processing time become enormous, and It is causing the prolongation of the period. As a method for solving this, there is a second conventional method. This is because the memory region and the processing time can be reduced by partitioning the element formation region. In fact, most of the current layout tools adopt the configuration of the second conventional method. Here, the second conventional method is a method of finding a wiring route in a restricted partial area. Therefore, if a sufficient wiring area is not secured, connection of all wirings is completely performed. Is not guaranteed. Conversely, if an extra wiring area is taken, the wiring is not guaranteed, but the chip area increases, which leads to an increase in manufacturing cost. In order to avoid this, a technique for estimating the wiring area that can estimate the wiring area to a necessary and minimum size is indispensable.

As a third conventional method, there is an estimation method of estimating a wiring region width by displaying blocks and wiring regions by points on a graph, and counting the number of passing connection wires passing through the points on the graph. . However, the third conventional method estimates a signal line characteristic such as a change in wiring width for each via or signal connecting wiring between different wiring layers, or a highly accurate wiring region width reflecting a terminal position of a block or the like. It is not possible.

[0007]

Further, in each of the above conventional layout design methods, when changing the arrangement position of a block based on a wiring result or a wiring area width, a designer must change the arrangement position of each block. Need to be considered,
Since the data provided to the designer is about the degree of congestion of the wiring area, examination by a skilled engineer in layout design is essential. Therefore, in the layout design of the power supply wiring, there is no other method than the determination by trial and error including the signal lines, and there is a problem that the number of steps in the layout design period increases.

The present invention has been made in view of the above-mentioned conventional problems, and provides a layout design method using a block assembling method.
It is an object of the present invention to be able to estimate a wiring region width between blocks in a short period of time and with high accuracy.

[0009]

In order to achieve the above object, the present invention provides a layout design method for a semiconductor integrated circuit, comprising: (1) a first reference (grid) line and a second reference A (lattice) line is divided into a lattice shape, and a plurality of functional blocks are temporarily arranged on the divided arrangement area. (2) A wiring area between the tentatively arranged functional blocks, in a direction in which the first reference line extends, is sandwiched between a pair of adjacent first reference lines and a pair of second reference lines. Extracting a first wiring grid area defined for each reference line,
From the region in the direction in which the second reference line extends, a second wiring grid region sandwiched between a pair of second reference lines adjacent to each other and partitioned for each pair of first reference lines is extracted. (3) Wiring is searched for each of the first and second wiring grid areas, and the number of occupied wirings in which the searched wiring occupies the first reference line or the second reference line in the wiring grid area is obtained. The configuration is as follows.

More specifically, a layout design method for a semiconductor integrated circuit according to the present invention comprises a plurality of first reference lines and a plurality of second reference lines which extend in parallel at predetermined intervals and intersect with each other in a grid pattern. On the placement area partitioned into
A layout design method for arranging a plurality of functional blocks constituting a semiconductor integrated circuit and estimating an inter-block wiring area width required for wiring laid in a wiring area formed between the arranged functional blocks. In the arrangement area, a plurality of functional blocks are spaced from each other and
A step of temporarily arranging the functional blocks along the reference line or the second reference line, and a step of temporarily interposing a pair of the first reference lines adjacent to each other from a region in the wiring region in the direction in which the first reference line extends. A plurality of the first divided by the second reference line
A first wiring grid region extracting step of extracting a first wiring grid region composed of unit wiring regions, and a step of extending a second reference line in the wiring region to a pair of second reference lines adjacent to each other. A second wiring grid area extracting step of extracting a second wiring grid area composed of a plurality of second unit wiring areas sandwiched and partitioned for each pair of first reference lines; and a first wiring grid area. For the first wiring, which is the number of occupied lines occupying the first reference line between the function blocks corresponding to the first unit wiring area and the searched wiring, based on the circuit connection information. A first wiring occupancy number obtaining step of obtaining an occupation number; and searching for wiring in the second wiring grid area based on the circuit connection information, and the searched wiring corresponds to the second unit wiring area. No. between functional blocks The second is a occupation numbers occupying the reference line
A second wiring occupation number acquiring step of acquiring the wiring occupying number of
An inter-block wiring area width estimating step of estimating an inter-block wiring area width between each functional block based on the first occupied number of wirings and the second occupied number of wirings.

According to the semiconductor integrated circuit layout designing method of the present invention, a wiring grid region sandwiched between a pair of first reference lines or second reference lines adjacent to each other in a wiring region where functional blocks are temporarily arranged is provided. A wiring is searched for each wiring grid area based on the circuit connection information, and the number of occupied wirings, which is the number of occupied first or second reference lines in the wiring grid area, is extracted. get. As a result, the wiring search area is only the wiring grid area sandwiched between the first and second reference lines adjacent to each other among the wiring areas between the blocks. For example, the maze method is used. It is possible to search for wiring in a short time. Further, since the number of occupied wirings in which the searched wiring occupies the first reference line or the second reference line in the wiring grid area is obtained and used, the necessary wiring area width between the blocks is reliably determined. Can be estimated (estimated).

In the layout design method for a semiconductor integrated circuit according to the present invention, the semiconductor integrated circuit has a plurality of wiring layers overlapping each other, and is provided between the first wiring occupation number obtaining step and the inter-block wiring area width estimating step. In the first wiring grid area, a via that connects one wiring layer to another wiring layer in a plurality of wiring layers is searched for based on the circuit connection information, and the searched via is a first unit. A first via occupation number acquiring step of acquiring a first via occupancy number which is an occupation number occupying the first reference line between the wiring area and the corresponding functional block; Searching for a via connecting one wiring layer and another wiring layer in a plurality of wiring layers based on the circuit connection information, and searching for the via between the functional blocks corresponding to the second unit wiring area. 2nd reference line A second via occupancy number acquiring step of acquiring a second via occupancy number that is an occupied occupancy number, wherein the inter-block wiring area width estimating step includes a first wiring occupancy number and a second wiring occupancy number. It is preferable to include a step of estimating an inter-block wiring area width based on the first via occupation number and the second via occupation number.

In the semiconductor integrated circuit layout designing method according to the present invention, a moving direction for estimating a moving direction that satisfies the estimated inter-block wiring region width is provided for each functional block after the inter-block wiring region width estimating step. Preferably, the method further includes an estimation step. This makes it easy to rearrange the plurality of functional blocks temporarily arranged in the arrangement area so as to have a necessary interval in the wiring area between the functional blocks. Note that this rearrangement process may be performed manually or may be mechanized.

[0014] In this case, the moving direction estimating step may include any one of the plurality of functional blocks as a first reference line or a second reference line.
By moving the reference line in the direction in which the reference line extends, by estimating the movement direction in which the area of the wiring region becomes smaller among the movement directions satisfying the estimated inter-block wiring region width for a plurality of functional blocks. It is preferable to include the step of performing. In this way, it becomes easy to relocate the plurality of functional blocks temporarily arranged in the arrangement area so as to have a necessary and minimum interval in the wiring area between the functional blocks. Again, it does not matter whether the relocation processing is performed manually or by a machine.

In the layout design apparatus for a semiconductor integrated circuit according to the present invention, each of the plurality of first reference lines and the plurality of second reference lines extending in parallel at predetermined intervals and intersecting with each other is partitioned in a grid pattern. A layout of a semiconductor integrated circuit in which a plurality of functional blocks in a semiconductor integrated circuit including a plurality of functional blocks are respectively arranged on an arrangement region, and a region area of a wiring region formed between the arranged functional blocks is optimized. A plurality of functional blocks on an arrangement area are temporarily arranged at intervals from one another in a wiring area, which is directed to a design apparatus, from a region extending in a direction in which a first reference line extends, to a pair of adjacent first reference lines. Extracting a first wiring grid area composed of a plurality of first unit wiring areas sandwiched between lines and partitioned for each pair of second reference lines; A plurality of second unit wiring regions sandwiched between a pair of second reference lines adjacent to each other and partitioned for each pair of the first reference lines from a region in the direction in which the second reference line extends in the wiring region. A wiring grid area extracting means for extracting a second wiring grid area; and a wiring search for the first wiring grid area based on the circuit connection information, wherein the searched wiring corresponds to the first unit wiring area. A first wiring occupancy number, which is an occupation number occupying the first reference line between the functional blocks to be executed, and searching for a wiring in the second wiring grid area based on the circuit connection information; The second number of occupied wirings, which is the number of occupied lines occupying the second reference line between the function blocks corresponding to the second unit wiring area and the searched wiring, is acquired, and the acquired first occupied number of wirings and An arrangement for retaining the second wiring occupancy number The occupation number holding unit and the first wiring grid area are searched for vias connecting one wiring layer and another wiring layer in a plurality of wiring layers based on the circuit connection information. First
Between the functional blocks corresponding to the unit wiring area of
The first via occupation number, which is the occupation number occupying the reference line, is obtained, and one wiring layer and another wiring layer in a plurality of wiring layers are provided for the second wiring grid area based on the circuit connection information. And a second via occupancy number that is the number of occupied occupied second reference lines between the function blocks corresponding to the second unit wiring area and the searched via is obtained. Acquired first via occupancy and second
Via occupying number holding means for holding the via occupying number, and a block between each functional block based on the first wiring occupying number, the second wiring occupying number, the first via occupying number, and the second via occupying number. An inter-block wiring area width estimating means for estimating an inter-wiring area width; and re-evaluating a plurality of functional blocks tentatively arranged in the arrangement area so as to satisfy the estimated inter-block wiring area width and reduce the area of the wiring area. A wiring area optimizing means for optimizing the area of the wiring area by arranging the wiring area;

According to the layout design apparatus for a semiconductor integrated circuit of the present invention, the width of the wiring area between blocks in the wiring area between the functional blocks can be optimized, and consequently, the compaction of the functional blocks can be performed.

A layout design apparatus for a semiconductor integrated circuit according to the present invention displays an arrangement position of a plurality of functional blocks temporarily arranged in an arrangement area and a moving direction of a block in which a wiring area is optimized for each functional block. It is preferable that a display unit is further provided. In this way, when relocating the temporarily arranged functional blocks by hand,
The necessary movement direction of the function block can be confirmed from outside.

In the semiconductor integrated circuit layout designing apparatus according to the present invention, when a power supply line for supplying a power supply voltage to a power supply terminal included in a functional block is set in a wiring area, an inter-block wiring among a plurality of wiring paths of the power supply wiring is provided. It is preferable that the power supply apparatus further includes a power supply wiring path determination unit that determines by selecting a wiring path with a small increase in the area width.

[0019]

(First Embodiment) A first embodiment of the present invention will be described with reference to the drawings.

FIG. 1 shows a partial plan configuration for describing an arrangement region used in a layout design method of a semiconductor integrated circuit according to a first embodiment of the present invention and a reference line (grid line) in the arrangement region. ing. In FIG. 1, the LSI
A plurality of tracks serving as a first reference line and a plurality of tracks serving as a second reference line extend in parallel with each other at a pitch interval serving as reference wiring and intersect with each other. Are partitioned in a grid pattern by the columns. On the arrangement area 10, for example, a first functional block 21 which is a partial circuit of a semiconductor integrated circuit is provided.
A and the second functional block 21B are arranged at a predetermined interval set as the initial arrangement
Are arranged along.

A wiring area 20 is formed between the functional blocks 21A and 21B. For example, the first functional block 2 is provided on the wiring region 20 via the first via 23A.
1A and a second via 2
A second wiring 24B connected to the second functional block 21B via 3B is laid.

Here, the occupied numbers of the tracks occupied by the wirings 24A, 24B and the vias 23A, 23B are called a first wiring occupied number and a first via occupied number, respectively. Called occupancy number. For example, as shown in FIG. 1, the first wiring 24A has two tracks 1
Therefore, the first wiring occupation number is 2,
Since the second via 23B occupies one track, the first via occupation number is one.

The value obtained by adding the minimum spacing rule of each of the wirings 24A and 24B to the wiring is defined as the wiring pitch.

Here, the wiring region 20 shown in FIG.
Shows a wiring region formed in the direction in which the track 11 as the reference line extends, and the column 12 as the second reference line.
In the case of the wiring area in the direction in which the wiring extends, although not shown, the occupied numbers of the wiring and the via occupying the column are referred to as a second wiring occupied number and a second via occupied number, respectively. The number of occupied tracks is 2.

In the present specification, the track 11
When it is not necessary to distinguish between the wiring region 20 in the direction in which the column extends and the wiring region 20 in the direction in which the column extends, the distinction such as the first wiring occupation number and the second wiring occupation number is omitted.

Hereinafter, a layout design method for a semiconductor integrated circuit according to the first embodiment will be described with reference to the drawings.

FIGS. 2A to 2C are block layouts for explaining the layout design method according to the first embodiment. FIG. 2A shows a layout area in which a plurality of blocks are initially placed. FIG. 2B shows a wiring grid area corresponding to the direction in which the columns extend in the arrangement area, and FIG. 2C shows a wiring counting area corresponding to the wiring grid area. ing. As shown in FIG. 2A, a plurality of square-shaped function blocks 21A to 21E are provisionally arranged on the arrangement area 10 so that the outer shape becomes one square, and a plurality of square-shaped function blocks 21A to 21E are provided in a peripheral area of each function block. Are input / output blocks 26A to 26D serving as input / output interfaces with the outside.
Is arranged. Between each of the functional blocks 21A to 21E and the input / output blocks 26A to 26D and each of the functional blocks 2
In a region between 1A to 21E, a wiring grid region 31 composed of a region sandwiched between a pair of adjacent columns is formed. Therefore, the interval between the wiring grid areas 31 matches the interval between the columns 12, and the wiring grid area 31 is limited to the wiring area to search for the wiring path of each inter-block wiring. Hereinafter, when it is not necessary to distinguish between a functional block and an input / output block, it is simply referred to as a block.

FIG. 2B is an enlarged view of the wiring grid area 31 shown in FIG. The wiring grid area 31 shown in FIG. 2B is an aggregate of a plurality of unit wiring areas 31 a sandwiched between a pair of columns 12 adjacent to each other and partitioned for each track 11. In addition, each unit wiring area 31
a contains back trace information 31 used to hold the wiring route when searching for the wiring route by the maze method.
b is retained. Note that the unit wiring area 31a in the wiring grid area 31 parallel to the track 11 corresponds to the column 1
2 are defined.

When the layout design method according to the present embodiment is realized by a computer-controlled layout design apparatus, the wiring count area 32 composed of a plurality of unit wiring count areas 32a shown in FIG. What is necessary is just to create and hold in the data storage (memory) part of the design device. That is, the unit wiring count area 3 of the wiring count area 32
2a, the unit wiring area 31 of the wiring grid area 31
The number of tracks occupied by the wiring or via for each a is stored.

The layout design method according to the present embodiment
In a wiring area in which a plurality of blocks are temporarily arranged in a wiring area 20 of the arrangement area 10 shown in FIG. 1, a wiring width (interval) required for design is quickly and accurately estimated (estimated). is there. The outline is shown in Figure 2
As shown in (a), a plurality of functional blocks 21A to 21E and input / output blocks 26A to 26D are arranged on the arrangement area 10 at an interval from each other as an initial arrangement. Next, an area sandwiched between a pair of adjacent tracks or columns is extracted as a wiring grid area 31 from the wiring area, and the number of wirings passing between each wiring grid area 31 and the corresponding block and the wiring pitch thereof And the wiring area width between the functional blocks is estimated based on the number of tracks occupied by vias provided for connecting wiring to the block terminals adjacent to each wiring grid area 31.

FIG. 3 is a flowchart showing a layout design method according to the first embodiment of the present invention. First, in a functional block provisional arrangement step ST01 shown in FIG. 3, as shown in FIG. 1A, functional blocks 21A to 21E constituting a desired semiconductor integrated circuit are spaced from each other and along a track or a column. Temporarily arrange. Here, since the track and the column are logical reference lines, the arrangement area 10 may be defined in advance by a grid-like reference line over the entire surface thereof. Only the region 20 may be defined by these reference lines. In the case of realizing as a layout design apparatus, each block is prepared in advance as data, an arrangement position (floor plan) of the initial arrangement is obtained from these data, and the obtained result is output to the arrangement area 10. .

Next, in the wiring grid region extracting step ST02 shown in FIG. 3, as shown in FIG. 2A, the wiring region 20 formed between the blocks adjacent to each other is adjacent to each other in the track direction. In the column direction, a region sandwiched by a pair of tracks is extracted as a wiring grid region 31 for each pair of columns adjacent to each other in the column direction. A wiring count area 32 is provided as data holding means corresponding to the extracted wiring grid area 31. The number of wirings passing through each unit wiring area 31a, the wiring pitch thereof, and the wiring connected to a block terminal adjacent to each unit wiring area 31a are provided in each unit wiring counting area 32a of the wiring counting area 32. The width of the wiring area between the functional blocks is estimated based on the number of occupied vias. Here, the initial value of the unit wiring count area 32a is set to 0.

Next, a wiring route search step ST0 shown in FIG.
In 3, the wiring grid area 31 is regarded as a wiring area, and a wiring path is searched for the wiring laid between the blocks by using a maze method. Here, the search for the wiring route
This is performed based on circuit connection information (design rules) such as a netlist that connects the blocks at the same potential. As described above, in this embodiment, since the search path is limited to the wiring grid area 31 having a width of one pair of tracks or columns between blocks, the wiring path can be searched in a short time.

Next, in the step ST04 of obtaining the number of occupied tracks by the wiring shown in FIG. 3, the reference wiring pitch is set to 1, and it is determined how many times the wiring pitch of the searched wiring is larger than the reference wiring pitch. The obtained wiring pitch is set as the number of pitches occupied by the wiring, and is updated with the number of pitches occupied by the wiring for each unit wiring count area 32a corresponding to the searched wiring path. For all the unit wiring areas 31a, a wiring path search step S for the wiring grid area 31 is performed.
T03 and Step ST04 of Obtaining Number of Tracks Occupied by Wiring
Are sequentially executed, the number of occupied wirings is calculated based on the number of wirings between the blocks and the wiring pitch.

Next, in the step ST05 of acquiring the number of tracks occupied by vias shown in FIG. 3, when the semiconductor integrated circuit has a multilayer wiring layer structure, the wiring belonging to one wiring layer of the multilayer wiring is replaced by another wiring. Vias are provided at portions connected to the layers. The number of tracks or columns occupied by the vias is calculated.

Hereinafter, the number of occupied vias will be described for each via configuration with reference to the drawings.

As a first configuration, a case where a plurality of input / output terminals (block terminals) provided in a block are provided in different layers from each other will be described. In this case, the number of vias required until the block terminal is connected to the wiring extending in the track direction from the block terminal is calculated as the “number of transfer vias” according to the wiring layer in which the block terminal is provided.

In general, in the case of a multilayer wiring structure, it is determined in advance in each of the wiring layers which of the track direction and the column direction the wiring is preferentially laid. When laying wiring from a block terminal in contact with the wiring area, it is necessary to change via a via from a wiring layer to which the block terminal belongs to a priority wiring layer in which the direction in which the wiring is drawn out is prioritized, and a wiring in the track direction. When connecting to another via, it is necessary to connect to another via again.

FIG. 4 shows an example of a first configuration in which the number of vias until the block terminal is connected to a predetermined wiring layer differs depending on the wiring layer to which the block terminal belongs. As shown in FIG. 4, the functional block 21 has a first block terminal 41A belonging to the first wiring layer and a second block terminal 41B belonging to the second wiring layer. First block terminal 41A
Is connected to the first via 42A, the second block terminal 41B is connected to the second via 42B and the third via 42C, and each of the vias 42A to 42C occupies one track 11 respectively. Here, for example, the priority direction of the first wiring layer is the column direction, and the priority direction of the second wiring layer is the track direction.

As described above, since the first block terminal 41A belongs to the first wiring layer, only the first via 42A is required until the first block terminal 41A is connected to the first wiring 24A in the track direction. Therefore, the number of transfer vias is 1. On the other hand, since the second block terminal 41B belongs to the second wiring layer, a via required until the second block terminal 41B is connected to the second wiring 24B in the track direction needs to be transferred from the second wiring layer to the first wiring layer. There are two vias 42A and a third via 42C that switches from the first wiring layer to the second wiring layer. Therefore, the number of switching vias in this case is two.

Next, as a second configuration, a case will be described in which a plurality of block terminals provided in a block are provided in different layers, and wiring layers connected to the block terminals have different wiring layers. In this case, when connecting each block terminal and a wiring belonging to one wiring layer extending in the track direction, the maximum number of vias occupying another wiring layer extending in the track direction is calculated as “maximum occupancy number”. I do.

FIG. 5 shows an example of a second configuration in which the track direction is the priority direction and the number of vias before connecting to different wiring layers differs depending on the wiring layer to which the block terminal belongs. As shown in FIG. 5, the function block 21 includes a first block terminal 41C belonging to the first wiring layer.
And a second block terminal 41D belonging to the third wiring layer. The first block terminal 41C is connected to the first wiring 24C via a first via 42D connecting the first wiring layer and the fourth wiring layer. Second block terminal 41D
Is a second via 42 connecting the third wiring layer and the first wiring layer.
E and a third wiring 42F connecting the first wiring layer and the second wiring layer to the second wiring 24D.

Here, the priority directions of the wiring layers having the four-layer structure are as follows: the first wiring layer and the third wiring layer are in the column direction, and the second wiring layer and the fourth wiring layer are in the track direction.
Therefore, the first block terminal 41C belonging to the first wiring layer
When the first wiring layer is connected to the second wiring layer, the first wiring layer does not occupy another wiring layer other than the adjacent second wiring layer. Belongs to the first
Is connected to the fourth wiring layer, the first via 42D penetrating through the second and third wiring layers.
It is necessary to provide. As a result, the second wiring layer extending in the track direction is also occupied. In FIG. 5, the first block is connected via a plurality of vias respectively connecting the first wiring layer and the second wiring layer, the second wiring layer and the third wiring layer, and the third wiring layer and the fourth wiring layer. The terminal 41C and the first wiring 24C belonging to the fourth wiring layer are connected.

On the other hand, in the case of the second block terminal 41D belonging to the third wiring layer, both the second wiring layer and the fourth wiring layer are wiring layers adjacent to the third wiring layer. The connection to any of the fourth wiring layers does not occupy another track.

As described above, in FIG. 5, the maximum number of vias required for the first block terminal 41C is two, and the maximum number of vias required for the second block terminal 41D is one. It is.

Next, as a third configuration, a case where the sizes of a plurality of block terminals provided in a block are different from each other will be described. In this case, for each block terminal,
The number of tracks occupied by the wide via that occupies two or more reference lines is calculated as the “number of wide tracks”.

Normally, since a larger current flows through the power supply wiring and the like than the signal line, a wiring wider than the signal line is used. Therefore, it is necessary to adjust the size of the block terminal provided in the block according to the amount of current. When such wide wirings are connected via vias, vias having a larger sectional area than vias used for connection of signal wirings are used, so that the number of occupied vias inevitably increases.

FIG. 6 shows a specific example of a wide wiring and a wide via. As shown in FIG. 6, the function block 21 includes:
It has a first block terminal 41E which is a wide terminal and a second block terminal 41F for signals. The first block terminal 41E has a wide first via 42G and a wide second via 42H occupying two tracks, respectively.
Is connected to the first wiring 24E via the. On the other hand, the second block terminal 41F is connected to the second wiring 24F via the third via 42I and the fourth via 42J occupying one track, respectively. Thus, the wide first via 42G and the second via 42H
Has two wide tracks and the third via 42I
And the fourth via 42J has one wide track.

As described above, with respect to vias, the via occupation number is calculated for each block terminal of each block including the first to third configurations.

Therefore, the occupation number per via is:
It can be calculated by the following equation (1).

Number of occupied vias = (number of transfer vias−1) × maximum occupied number × number of wide tracks (1) The number of occupied vias calculated by equation (1) is calculated for the wiring count area 32 adjacent to each block terminal. The sum is added for each unit wiring count area 32a. The process ST for acquiring the number of occupied tracks by the via
05 ends.

Next, an inter-block wiring area width calculation step ST06 as an inter-block wiring area width estimation step shown in FIG.
In the above, the value held in the wiring count area 32 is divided by the number of wiring layers in which the track direction or column direction in the corresponding wiring grid area 31 is the priority direction, and the obtained quotient is rounded up to the nearest whole number to obtain an integer. To Here, in the case of the first wiring count area 32 extending in the track direction, the track direction is divided by the number of wiring layers in which the track direction has priority. In the case of the second wiring count area 32 extending in the column direction, the column direction has priority. Divided by the number of wiring layers.

In this way, the distance between the blocks,
That is, the number of tracks required for the wiring area can be estimated. Therefore, by arranging the intervals between the blocks more than the number of tracks obtained by the estimation, not only the number of wires and the wiring pitch laid in the wiring area between the blocks but also the occupied area of the via and the wiring layer It is possible to obtain a high-precision block arrangement in which even the vias generated by the transfer are estimated.

In estimating the number of occupied wires and the number of occupied vias in the wiring area, a wiring path search process by a maze method using a wiring grid area of a pair of adjacent track widths or column widths as a wiring area, and a linear time. Since the process of estimating the via area that can be calculated is used, the block interval can be estimated in a very short time.

FIG. 7 is a block layout for explaining the layout design method according to the present embodiment, and shows an example of estimating the width of the inter-block wiring region. As shown in FIG. 7, the first functional block 21A has a wide first block terminal 41A belonging to the second wiring layer and a normal-width second block terminal 41B belonging to the first wiring layer. I have. The wiring area 20 between the first functional block 21A and the second functional block 21B is partitioned by a plurality of tracks 11.

On the wiring region 20, the first block terminal 41A extends in the track direction through the first and second vias 42A and 42B which connect the first and second wiring layers and are wide. It is connected to the first wiring 24A. Further, the second block terminal 41B is connected to a second wiring 24B extending in the track direction via a third via 42C connecting the first wiring layer and the second wiring layer.
A second line is provided between the first line 24A and the second line 24B.
A third wiring 24G belonging to the wiring layer is laid.

In the wiring count area 32A for wiring, a value calculated based on the wiring occupation number and the wiring pitch of the wiring passing through the wiring area 20 is held for each unit wiring count area. As shown in FIG. 7, the occupation number of the first wiring 24A is 2
Since each of the occupied numbers of the second and third wirings 24B and 24C is 1, the wiring count area 32A shown in FIG.
Can be obtained.

The via wiring count area 32B holds the number of occupied vias for each unit wiring count area. As shown in FIG. 7, the first and second vias 42A, 42B
Is 2, the maximum occupied number is 1, and the number of wide tracks is 2. Therefore, both the occupied via numbers are calculated from the formula (1). Further, since the number of transfer vias is 1 in the third via 42C, the number of occupied vias is 0 from the calculation formula (1).
Becomes

Accordingly, the wiring count area 32C shows the result obtained by adding the wiring count areas 32A and 32B for each unit wiring count area, and dividing the result by the number of wiring layers having the track direction as the wiring direction. In the case shown in FIG. 7, although the wiring is a two-layer wiring, since the wiring layer in the track direction uses only one of the second wiring layers, the result does not change even if the division is performed.

As described above, since the maximum value of the values held in the wiring count area 32C from the wiring count area 32C is 5, the wiring area 20 needs an interval of 5 tracks. Is estimated.

Hereinafter, a layout design apparatus for realizing the layout design method according to the first embodiment will be described with reference to the drawings.

FIG. 8 shows a functional configuration of a semiconductor integrated circuit layout design apparatus according to the first embodiment of the present invention. As shown in FIG. 8, an arithmetic unit 101 including a CPU, a storage unit 102 including an internal storage device and an external storage device connected to the arithmetic unit 101, an input unit 103 for receiving external data, and desired data are displayed. The display unit 104 includes a display unit 104.

In the wiring grid area extracting unit 105, the processing procedure in the wiring grid area extracting step ST02 shown in FIG. 3 is programmed so that the arithmetic unit 101 can execute it. Similarly, the inter-block wiring area width estimating unit 106 The processing procedure in the inter-block wiring area calculation step ST06 shown in FIG.

The storage unit 102 stores, for example, the wiring count area 32 as the wiring occupation number holding means as shown in FIG.
A, wiring count area 32 as via occupation number holding means
B and a wiring count area 32C.

Hereinafter, the operation of the layout design apparatus configured as described above will be described.

First, from the input unit 103, a layout result in which a plurality of functional blocks obtained by dividing a semiconductor integrated circuit to be designed are temporarily (initial) arranged in a predetermined layout area, circuit connection information (wiring information), and input / output Each data of block arrangement information is input, and each input data is held in each predetermined area of the storage unit 102.

Next, the wiring grid area extraction unit 105
Based on the input data, a wiring grid area is extracted from the wiring area, and then the inter-block wiring area width estimating unit 106 estimates a wiring area width (track width) required between the blocks in design. .

The display unit 104 of the layout design apparatus according to the present embodiment, based on the estimated wiring area width, if the wiring area width is insufficient at the initial arrangement position of each functional block, The moving direction in which each functional block is moved so that the estimated wiring area width is secured is displayed.

FIG. 9 shows a display example displayed on the display unit 104. Here, in FIG. 9, the same components as those shown in FIG. 2A are denoted by the same reference numerals. As shown in FIG. 9, for example, the second functional block 2
In the vicinity of the center of 1B, a first instruction mark 51A composed of two arrows, leftward and downward, is displayed, whereby the second functional block 21B and the first input / output block 26A are connected to each other. This indicates that it is necessary to increase the interval (wiring area width) between the second functional block 21B and the fourth input / output block 26D. A second instruction mark 51B made of a circle is displayed near the center of the first functional block 21A, which indicates that the first functional block 21A does not need to be moved. .

The display of these instruction marks is determined as follows.

First, the function blocks 21A to 21E and the input / output block 26A initially arranged on the predetermined arrangement area
~ 26D for each wiring region formed between the blocks,
Calculate the difference between the inter-block wiring area width at the time of initial placement and the estimated inter-block wiring area width at which the required wiring area width is estimated, and if the estimated inter-block wiring area width is larger than at the time of the initial placement, The difference is stored as an increase.

Next, the direction in which the increase in the width of the inter-block wiring area is minimized is defined as the moving direction of the block. The moving direction of each block is determined for each of the vertical (track) direction and the horizontal (column) direction of each block. Therefore, a direction that satisfies the increase in the width of the inter-block wiring area with respect to the vertical and horizontal directions of each block is defined as the moving direction of each block. When the increments are equal, the instruction mark is displayed as a circle.

As described above, according to the layout design apparatus of this embodiment, the wiring grid area 31 including the plurality of unit wiring areas 31a and the unit wiring count corresponding to the unit wiring area 31a are provided in the wiring area 20 between the blocks. Area 3
By providing 2a, the number of occupied wirings by the number of wirings passing through the inter-block wiring area and the number of vias occupied by vias estimated by the wiring layer and the wiring width of the input / output terminals of each block can be quickly estimated.

Further, since the maze method is executed by regarding only the limited area called the wiring grid area as the wiring area, it is possible to reduce the use of the memory resources of the layout design apparatus required when searching for the wiring area. As a result, even if the size of the semiconductor integrated circuit to be designed becomes large, the width of the wiring area between blocks can be estimated in a short time and the estimation accuracy is improved without increasing the scale of the layout design apparatus. In addition, the layout design man-hour can be reduced.

Note that the shape of each of the instruction marks 51A and 51B is merely an example, and it is sufficient that the direction marks 51A and 51B have a shape and a color that can be distinguished from a moving direction indicating the left-right or up-down direction and a movement unnecessary. Also, instead of a plurality of arrows, a vector sum of these vectors may be used.

Further, not only the moving direction but also the moving amount of the block is set to a value obtained by subtracting the smaller increasing amount from the larger increasing amount for each wiring area, and the increasing amount is displayed simultaneously with the moving direction. You may.

Further, the change information of each block position is input from the input unit 103 shown in FIG. 8, and the process of estimating the width of the wiring area between the blocks is executed again on the changed input result, and the result is displayed. The information may be output to the unit 104.

(Second Embodiment) Hereinafter, a second embodiment of the present invention will be described with reference to the drawings.

In the first embodiment, a method for estimating a required wiring region width from connection information in a wiring region formed between blocks on an arrangement region and moving a block satisfying the required wiring region width The layout design apparatus for designating a direction has been described. In the present embodiment, a method for performing compaction on each functional block based on the wiring area width between blocks obtained by the first embodiment will be described.

FIGS. 10A and 10B are block layouts for explaining a layout design method of a semiconductor integrated circuit according to the second embodiment of the present invention.
10A shows a state where a plurality of blocks are initially arranged on the arrangement area, and FIG. 10B shows an arrangement result in which one-dimensional compaction processing has been performed on each block. As shown in FIG. 10A, on the arrangement area 10,
A plurality of square-shaped function blocks 21A to 21D are initially arranged so that the outer shape becomes one square, and input / output blocks 26A to 26D serving as input / output interfaces with the outside are arranged in the peripheral area of each function block. Have been.

As shown in FIG. 10B, for example, the second functional block 21 B and the fourth
In the wiring area between the third functional block 21D and the wiring area between the third functional block 21C and the fourth input / output block 26D, three wirings 24 are laid.

After estimating the wiring region width for each of the initially arranged blocks in the same manner as in the first embodiment, as shown in FIG. One-dimensional compaction is performed in the horizontal (column) direction and the vertical (track) direction to obtain a layout whose arrangement position is optimized.

As described above, by performing the one-dimensional compaction with the wiring area width between the blocks as the minimum spacing between the blocks, it is possible to easily obtain the block arrangement result satisfying the wiring area width estimation result. it can.

According to the second embodiment, instead of calculating the wiring area width between blocks by executing channel wiring as shown in the first conventional method, one track width or one column width is used. Since it has a wiring search step using a maze method that regards the wiring grid area as a wiring area, and a via area estimation step that can be calculated in linear time,
The interval between blocks can be quickly estimated, and one-dimensional compaction using a constraint graph can be executed in a short time.

(Modification of Second Embodiment) A modification of the second embodiment according to the present invention will be described below with reference to the drawings.

FIG. 11 shows a layout design method according to a modification of the present embodiment, and shows a plan configuration of an arrangement region for explaining a method of reducing a chip area. here,
In FIG. 11, the same components as those shown in FIG. 9 are denoted by the same reference numerals, and description thereof will be omitted.

In this modification, each functional block 21
After estimating the inter-block wiring area width in A to 21E, each functional block 21A to 21E is moved by one track or one column, and one-dimensional compaction is performed on a new arrangement result after the movement. .

In the block assembling method, the arrangement position of each block and the wiring area width between each functional block are determined by
An area required for the arrangement region 10, that is, a chip area can be calculated. Therefore, when each functional block is moved in the vertical direction or the horizontal direction, the moving direction in which the calculated chip area becomes the minimum is defined as the moving direction of each functional block. By sequentially performing such processing for each functional block, it is possible to indicate the direction in which the chip area decreases when each functional block is moved in the designated direction by one track or one column.

For example, FIG. 11 shows that the chip area can be reduced by moving the fourth functional block 21D one track to the right in the drawing.
The first functional block 21A indicates that the chip area does not decrease even when the first functional block 21A is moved in any direction of up, down, left, and right.

Here, it is needless to say that the shapes or colors of the instruction marks 51A and 51B for instructing the moving direction which can reduce the chip area are not limited.

FIG. 12 shows a functional configuration of an automatic layout design apparatus for a semiconductor integrated circuit according to a modification of the present embodiment. Here, in FIG. 12, the same components as those shown in FIG. 8 are denoted by the same reference numerals, and description thereof will be omitted.

As shown in FIG. 12, the automatic layout designing apparatus according to the present embodiment
5, a block selecting unit 107, a moving direction estimating unit 108, a block moving unit 109, a chip area estimating unit 110, and a block position determining unit 111, in addition to the block 5 and the inter-block wiring area width estimating unit 106. Again, the block selecting unit 107, the moving direction estimating unit 108, the block moving unit 10
9. Chip area estimating unit 11 as wiring area optimizing means
The arithmetic unit 101 of the 0 and block position determination unit 111 is programmed to be executable.

Hereinafter, the operation of the automatic layout design apparatus configured as described above will be described.

First, from the input unit 103, each data of an arrangement result, circuit connection information, and input / output block arrangement information in which a plurality of functional blocks obtained by dividing a semiconductor integrated circuit to be designed are initially arranged in a predetermined arrangement area. Is input and each input data is stored in each predetermined area of the storage unit 102.

Next, the wiring grid area extraction unit 105
A wiring grid area is extracted from the wiring area based on the input data, and then an inter-block wiring area width estimating unit 106 estimates a wiring area width necessary for design between the blocks.

Next, based on the estimated wiring region width,
The moving direction of the block selected by the block selecting unit 107 is estimated by the moving direction estimating unit 108, and the block is moved to a position satisfying the inter-block wiring area width by the block moving unit. Here, the result of the movement may be displayed on the display unit 104.

Next, the process proceeds to a process for reducing the chip area.

When an arbitrary block is interactively designated by the input unit 103 with respect to the arrangement result in which the necessary inter-block wiring area width is secured, the designated block is moved by one track in the designated direction. Alternatively, it is moved by one column, and one-dimensional compaction is executed again. If there are a plurality of specified directions, compaction is performed in all the specified directions, and the block is moved in the movement direction in which the chip area becomes the smallest. The new placement result is
Each time, it is displayed on the display unit 104.

Therefore, even if the block is moved in either the vertical direction or the horizontal direction, if such processing is repeatedly executed until the chip area cannot be further reduced, it becomes necessary to execute the processing between the blocks. It is possible to obtain a block arrangement that can reduce the chip area while securing a sufficient wiring area.

Here, a processing method in which the final solution (result) differs depending on the moving order and moving direction of the blocks when there are a plurality of moving directions, and a moving method in which the chip area increases when moving the blocks. Since the processing method is not allowed, it is not possible to obtain an optimum arrangement result with respect to the initial arrangement. However, when processing is performed interactively as in the present embodiment, an improved arrangement result can be quickly obtained for an arbitrary initial arrangement.

Since the method of selecting a block to be moved is arbitrary, a block to be moved may be selected using a random number.

(Third Embodiment) Hereinafter, a third embodiment according to the present invention will be described with reference to the drawings.

FIGS. 13A and 13B are schematic block diagrams for explaining a wiring method of a power supply path between blocks in a layout design method of a semiconductor integrated circuit according to a third embodiment of the present invention. FIG. 13 (a)
Indicates a power supply wiring on the arrangement area, and FIG. 13B shows a wiring count area corresponding to the wiring area. FIG. 13 (a)
As shown in (1), the first functional block 21A to the third functional block 21C are arranged on the arrangement area 10 at an interval from each other. An arrangement area 20 is formed in an area between the functional blocks 21A to 21C and a peripheral area thereof.

A first power supply block 26E is arranged in a region opposite to the third functional block 21C with respect to the first functional block 21A, and a third functional block 21C is provided for the second functional block 21B. In the area opposite to
Power supply block 26F is arranged.

A block (power) terminal 41A is provided at an end of the first functional block 21A in contact with the wiring region 20 on the side of the second power supply block 26F. In addition,
Here, in order to simplify the description, the power supply block 26
Input / output blocks other than E and 26F are omitted.

In FIG. 13A, the block terminal 41
A is connected to the first power supply block 26E by a first power supply wiring path 61A shown by a solid line, and is connected to the second power supply block 26F by a second power supply wiring path 61B shown by a broken line.

Hereinafter, the wiring region 2 formed as described above
0, whether the first power wiring path 61A or the second power wiring path is selected when the power path wiring method according to the present embodiment is used will be described.

Here, as shown in FIG. 13B, the wiring count area 32 corresponding to the wiring grid area (not shown) extracted from the wiring area 20 is formed by the method shown in the first embodiment. It is assumed that the track occupation number is calculated and held for each unit wiring count area.

The area on the side of the first power supply block 26E in the wiring count area 32 includes a first unit wiring count area 32b in which 8 where the number of tracks occupied is the largest among the areas is held. The area on the second power supply block 26F side in the counting area 32 includes a second unit wiring counting area 32c in which 6 having the largest track occupation number is held in the area.

First, in FIG. 13A, it is assumed that there is no wiring route in the direction of the second power supply block 26F with respect to the block terminal 41A of the first functional block 21A, and the maze method is used. By searching for a wiring path, a first power supply wiring path 61A is obtained. Subsequently, assuming that there is no wiring path in the direction of the first power supply block 26E, a second power supply wiring path 61B is obtained by searching for a wiring path using the maze method. Here, it is assumed that the number of tracks occupied by the power supply wiring does not depend on the wiring direction of the power supply.

Therefore, when the first power supply wiring path 61A is selected, the sum of the track occupation number of the power supply wiring itself and the wiring count area corresponding to the wiring area 20 through which the power supply wiring itself passes is the maximum value of 8 Is not exceeded, the required wiring area width between blocks does not change even if the first power supply wiring path 61A is provided.

On the other hand, when the second power supply wiring path 61B is selected, the second power supply wiring path 61B passes through the unit wiring count area 32c having the maximum value of 6 among the corresponding wiring count areas, Since the width of the wiring area 20 between the blocks is increased by the number of tracks occupied by the wiring itself, it is certain that the number of tracks occupied by the second unit wiring count area 32c becomes 7 or more. Therefore, the first power supply wiring path 61A or the second power supply wiring path 61B may be selected on the condition that the increase in the chip area described in the modification of the second embodiment is small.

FIG. 14 shows a functional configuration of an automatic layout design apparatus for a semiconductor integrated circuit according to the present embodiment. Here, in FIG. 14, the same components as those shown in FIG. 12 are denoted by the same reference numerals, and description thereof will be omitted. As shown in FIG. 14, the layout automatic designing apparatus according to the present embodiment has a configuration shown in FIG.
And a power supply path determination unit 114.

Accordingly, as described above, when a plurality of power supply wiring paths can be selected, not only the size of the track occupied width of the corresponding power supply wiring path but also the size of the chip area after wiring is selected. Therefore, the width of the wiring area between blocks including the power supply wiring can be estimated in a short time and with high accuracy.

In this embodiment, the first power supply block 26E and the second power supply block 26F are set as the connection targets of the block terminals 41A, which are the power supply terminals. Good.

For example, for example, a power supply block terminal 41
If A is provided at the end adjacent to the wiring area of the first functional block 21A parallel to the track direction, the power search may be performed twice in the track (vertical) direction.

[0117]

According to the layout design method of the semiconductor integrated circuit of the present invention, the search area for searching for wiring is limited to the wiring grid area sandwiched between a pair of first and second reference lines adjacent to each other. Therefore, for example, even if the maze method is used for searching for the wiring, the search can be performed in a short time. Further, since the number of occupied wirings in which the searched wiring occupies the first reference line or the second reference line in the wiring grid area is obtained and used, the necessary wiring area width between the blocks is reliably determined. Can be estimated. Therefore, even when the size of the semiconductor integrated circuit to be designed becomes large, the time for estimating the width of the inter-block wiring area between the functional blocks can be shortened and the estimation accuracy is improved, so that the layout design man-hour can be shortened.

In the layout design method of a semiconductor integrated circuit according to the present invention, the semiconductor integrated circuit has a plurality of wiring layers overlapping each other, and is provided between the first wiring occupation number obtaining step and the inter-block wiring area width estimating step. In the first wiring grid area, a via that connects one wiring layer to another wiring layer in a plurality of wiring layers is searched for based on the circuit connection information, and the searched via is a first unit. A first via occupation number acquiring step of acquiring a first via occupancy number which is an occupation number occupying the first reference line between the wiring area and the corresponding functional block; Searching for a via connecting one wiring layer and another wiring layer in a plurality of wiring layers based on the circuit connection information, and searching for the via between the functional blocks corresponding to the second unit wiring area. 2nd reference line A second via occupancy number acquiring step of acquiring a second via occupancy number that is an occupied occupancy number, wherein the inter-block wiring area width estimating step includes a first wiring occupancy number and a second wiring occupancy number. Including the step of estimating the inter-block wiring area width based on the first via occupation number and the second via occupation number can surely cope with the design of a semiconductor integrated circuit having a multilayer wiring structure.

In the layout design method for a semiconductor integrated circuit according to the present invention, a moving direction for estimating a moving direction that satisfies the estimated inter-block wiring region width for each functional block after the inter-block wiring region width estimating step. If the estimation step is further provided, a plurality of functional blocks temporarily arranged in the arrangement area can be easily rearranged so as to have a necessary interval in a wiring area between the functional blocks.
Compaction processing becomes easy.

In this case, the moving direction estimating step includes the step of determining one of the plurality of functional blocks by using the first reference line or the second reference line.
By moving the reference line in the direction in which the reference line extends, by estimating the movement direction in which the area of the wiring region becomes smaller among the movement directions satisfying the estimated inter-block wiring region width for a plurality of functional blocks. Since the plurality of functional blocks temporarily arranged in the arrangement area can be rearranged so as to have a necessary and minimum interval in the wiring area between the functional blocks, the chip area can be reduced. It will be easier.

According to the semiconductor integrated circuit layout designing apparatus of the present invention, since the layout designing method of the present invention can be realized, the width of the wiring area between the functional blocks can be optimized, and as a result, the compaction of the functional blocks can be reduced. Can also do.

A layout design apparatus for a semiconductor integrated circuit according to the present invention displays the arrangement positions of a plurality of functional blocks temporarily arranged in an arrangement area and the moving direction of a block whose wiring area is optimized for each functional block. With additional display means, a person can check the required movement direction of the function block from outside, so if optimization of compaction results cannot be uniquely determined, it can be left to humans Becomes

When the semiconductor integrated circuit layout design apparatus of the present invention sets a power supply line for supplying a power supply voltage to a power supply terminal included in a functional block to a wiring area, an inter-block wiring among a plurality of wiring paths of the power supply line is used. By further providing a power supply wiring path determining unit that determines by selecting a wiring path with a small increase in the area width, it is possible to determine a power supply wiring path that has conventionally depended on manual labor.

[Brief description of the drawings]

FIG. 1 is a partial plan view showing an arrangement region used for a layout design method of a semiconductor integrated circuit according to a first embodiment of the present invention and a reference line in the arrangement region.

FIGS. 2A and 2B are block diagrams for explaining a layout design method of the semiconductor integrated circuit according to the first embodiment of the present invention, and FIG. 2A is a plan view in which a plurality of blocks are temporarily arranged in an arrangement area; (B) is a plan view showing a wiring grid area in an arrangement area, and (c) is a configuration diagram showing a wiring counting area corresponding to the wiring grid area.

FIG. 3 is a flowchart illustrating a layout design method of the semiconductor integrated circuit according to the first embodiment of the present invention.

FIG. 4 is a partial plan view for explaining the number of tracks occupied by vias in a wiring region in the semiconductor integrated circuit layout designing method according to the first embodiment of the present invention.

FIG. 5 is a partial plan view for explaining the number of tracks occupied by vias in a wiring region in the semiconductor integrated circuit layout designing method according to the first embodiment of the present invention.

FIG. 6 is a partial plan view for describing the number of tracks occupied by vias in a wiring region in the semiconductor integrated circuit layout design method according to the first embodiment of the present invention.

FIG. 7 is a partial plan view showing an example of estimating a wiring region width between blocks for describing a layout design method of the semiconductor integrated circuit according to the first embodiment of the present invention.

FIG. 8 is a functional configuration diagram showing a semiconductor integrated circuit layout design apparatus according to the first embodiment of the present invention.

FIG. 9 is a plan view showing a display example of an arrangement region in a display unit of the semiconductor integrated circuit layout design apparatus according to the first embodiment of the present invention.

FIG. 10 shows a block arrangement for explaining a layout design method of a semiconductor integrated circuit according to a second embodiment of the present invention, and FIG. 10 (a) shows a state where a plurality of blocks are initially arranged on an arrangement area. It is a top view, and (b) is a top view showing the arrangement result which performed one-dimensional compaction processing to each block.

FIG. 11 is a plan view showing an arrangement region for explaining reduction of a chip area in a layout design method according to a modification of the second embodiment of the present invention.

FIG. 12 is a functional configuration diagram showing a layout design apparatus for a semiconductor integrated circuit according to a modification of the second embodiment of the present invention.

FIG. 13 shows a schematic block layout for explaining wiring of a power supply path between blocks in a semiconductor integrated circuit layout designing method according to a third embodiment of the present invention;
(A) is a top view which shows the power supply wiring on an arrangement area,
(B) is a configuration diagram showing a wiring count area corresponding to a wiring area.

FIG. 14 is a functional configuration diagram showing a layout design apparatus for a semiconductor integrated circuit according to a third embodiment of the present invention.

[Explanation of symbols]

 Reference Signs List 10 Arrangement area 11 Track (first reference line) 12 Column (second reference line) 20 Wiring area 21 Function block 21A First function block 21B Second function block 21C Third function block 21D Fourth function Block 21E Fifth functional block 23A First via 23B Second via 24 Wiring 24A First wiring 24B Second wiring 24C First wiring 24D Second wiring 24E First wiring 24F Second wiring 24G Third wiring 26A First input / output block 26B Second input / output block 26C Third input / output block 26D Fourth input / output block 26E First power supply block 26F Second power supply block 31 Wiring grid area 31a Wiring Grid area 31b Back trace information 32 Wiring count area 32a Unit wiring count area 32b 1st unit wiring count area 32c 2nd unit wiring count area 32A wiring count area (wiring occupancy number holding means) 32B wiring count area (via occupancy number holding means) 32C wiring count area 41A first block terminal 41B 2 block terminals 41C 1st block terminal 41D 2nd block terminal 41E 1st block terminal 41F 2nd block terminal 42A 1st via 42B 2nd via 42C 3rd via 42D 1st via 42E 2 via 42F 3rd via 42G 1st via 42H 2nd via 42I 3rd via 42J 4th via 51A First indication mark 51B Second indication mark 61A First power supply wiring path 61B Second Power supply wiring path 101 calculation unit 102 storage unit 103 input unit 104 display unit (display Stage 105 wiring grid region extracting unit 106 inter-block wiring region width estimating unit 107 block selecting unit 108 moving direction estimating unit 109 block moving unit 110 chip area estimating unit (wiring region optimizing means) 111 block position determining unit (wiring region optimization) 113) Power path search section 114 Power path determination section

 ────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Masahiko Toyonaga 1006 Kazuma Kadoma, Kadoma City, Osaka Prefecture F-term in Matsushita Electric Industrial Co., Ltd. (Reference) 5B046 AA08 BA05 BA06 5F064 AA06 DD02 DD08 DD12 DD18 DD20 DD24 DD32 DD50 EE03 EE08 EE10 EE12 EE14 EE15 EE16 EE26 EE27 EE52 EE58 EE60 HH06

Claims (7)

[Claims] 1. A plurality of functional blocks are provided on an arrangement area, which extends in parallel at a predetermined interval and is divided into a grid by a plurality of first reference lines and a plurality of second reference lines that intersect with each other. Layout of a semiconductor integrated circuit for arranging the plurality of functional blocks in a semiconductor integrated circuit and estimating an inter-block wiring area width required for wiring laid in a wiring area formed between the arranged functional blocks A design method, wherein a plurality of functional blocks are temporarily arranged in the arrangement region at intervals from each other and along the first reference line or the second reference line; From the region in the direction in which the first reference line extends, the plurality of first reference lines sandwiched by the pair of first reference lines adjacent to each other and partitioned for each pair of the second reference lines
A first wiring grid area extracting step of extracting a first wiring grid area composed of unit wiring areas; and a pair of second wiring grid areas adjacent to each other from a region in the wiring area in a direction in which the second reference line extends. A plurality of second sections sandwiched between reference lines and partitioned for each pair of the first reference lines
A second wiring grid area extracting step of extracting a second wiring grid area composed of unit wiring areas, and searching for wiring in the first wiring grid area based on circuit connection information. Wiring is performed between the functional blocks corresponding to the first unit wiring area and the first unit wiring area.
A first wiring occupation number obtaining step of obtaining a first wiring occupying number that is an occupying number occupying the reference line; and searching for wiring in the second wiring grid area based on the circuit connection information. , The searched wiring is the second
A second wiring occupation number acquiring step of acquiring a second wiring occupying number, which is an occupying number occupying the second reference line, between the functional blocks corresponding to the unit wiring area and the first wiring occupancy. A step of estimating an inter-block wiring area width between the respective functional blocks based on the number and the second number of occupied wirings. . 2. The method according to claim 1, wherein the semiconductor integrated circuit has a plurality of wiring layers overlapping each other, wherein the first wiring occupation number obtaining step and the inter-block wiring area width estimating step are performed during the first step. A via that connects one wiring layer and another wiring layer in the plurality of wiring layers is searched for the wiring grid area based on the circuit connection information, and the searched via is connected to the first unit wiring area. A first via occupancy number acquiring step of acquiring a first via occupancy number which is an occupancy number occupying the first reference line between functional blocks corresponding to the first and second wiring grid areas; Searching for vias connecting one wiring layer and another wiring layer in the plurality of wiring layers based on the circuit connection information, and finding the vias between functional blocks corresponding to the second unit wiring area; The second group between A second via occupancy number acquiring step of acquiring a second via occupancy number which is an occupancy number occupying the reference line, wherein the inter-block wiring area width estimating step comprises: 2. The semiconductor according to claim 1, further comprising a step of estimating the inter-block wiring area width based on a second wiring occupation number, the first via occupation number, and the second via occupation number. Layout design method for integrated circuits. 3. A moving direction estimating step of estimating a moving direction that satisfies the estimated inter-block wiring area width for the plurality of functional blocks after the inter-block wiring area width estimating step. 3. The layout design method for a semiconductor integrated circuit according to claim 1, wherein: 4. The moving direction estimating step includes moving one of the plurality of functional blocks in a direction in which the first reference line or the second reference line extends by an interval between the reference lines. 4. The method according to claim 3, further comprising estimating, for a plurality of functional blocks, a moving direction in which the area of the wiring region becomes smaller among the moving directions satisfying the estimated inter-block wiring region width. 5. A layout design method for a semiconductor integrated circuit. 5. A plurality of functional blocks are provided on an arrangement area which is extended in parallel at a predetermined interval and which is divided into a grid by a plurality of first reference lines and a plurality of second reference lines which cross each other. A layout design apparatus for a semiconductor integrated circuit for arranging the plurality of functional blocks in a semiconductor integrated circuit and optimizing a region area of a wiring region formed between the arranged functional blocks, A plurality of functional blocks above are interposed between a pair of first reference lines adjacent to each other from a region in a direction in which the first reference lines extend in a wiring region formed by being temporarily arranged at intervals from each other; A first wiring grid region including a plurality of first unit wiring regions partitioned for each pair of the second reference lines is extracted, and a first wiring grid region is extracted from the first wiring grid region. A plurality of second unit wiring regions sandwiched between a pair of the second reference lines adjacent to each other and partitioned for each pair of the first reference lines from a region in the direction in which the second reference line extends; Wiring grid area extraction means for extracting a second wiring grid area; and searching for wiring in the first wiring grid area based on circuit connection information, and searching for the wiring in the first unit wiring area. Between the corresponding functional blocks and the first
A first wiring occupancy number, which is an occupation number occupying the reference line, is obtained, and a wiring is searched for the second wiring grid area based on the circuit connection information. A second wiring occupancy number, which is an occupation number that occupies the second reference line, between the functional blocks corresponding to the second unit wiring area and the second wiring area, and the acquired first and second wiring occupancy numbers are obtained. Wiring occupancy number holding means for holding the number, and vias for connecting one wiring layer and another wiring layer in the plurality of wiring layers to the first wiring grid area based on the circuit connection information. Searching and acquiring the first via occupation number, which is the occupation number of the searched via occupying the first reference line between the functional blocks corresponding to the first unit wiring area and the second via, and For the wiring grid area, A via that connects one wiring layer and another wiring layer in the plurality of wiring layers is searched based on the circuit connection information, and the searched via is located between the functional blocks corresponding to the second unit wiring region. A second via occupancy number that occupies the second reference line, and a via occupancy number holding unit that holds the acquired first via occupancy number and second via occupancy number; 1, the second line occupancy, the first
An inter-block wiring area width estimating means for estimating an inter-block wiring area width between the functional blocks based on the via occupation number and the second via occupancy number; Wiring region optimization means for optimizing the region area of the wiring region by rearranging the functional blocks so as to satisfy the estimated inter-block wiring region width and to reduce the area of the wiring region. A layout design apparatus for a semiconductor integrated circuit. 6. A display unit for displaying an arrangement position of the plurality of functional blocks tentatively arranged in the arrangement area and a moving direction of a block in which a wiring area is optimized for each of the functional blocks. 6. The layout design apparatus for a semiconductor integrated circuit according to claim 5, wherein: 7. When a power supply line for supplying a power supply voltage to a power supply terminal of the functional block is set in the wiring area, an increase in the width of the inter-block wiring area among a plurality of wiring paths of the power supply wiring is small. 6. The layout design apparatus for a semiconductor integrated circuit according to claim 5, further comprising a power supply wiring path determining means for determining by selecting a wiring path.