JP2000340413A5 - - Google Patents

Description

【００３６】
（実施の形態２）
以下、本発明の実施の形態２における多連チップ抵抗器およびその製造方法について、図面を参照しながら説明する。
【００３７】
図５は本発明の実施の形態２における多連チップ抵抗器の断面図である。
【００３８】
図５において、４１は９６％のアルミナを含有してなる絶縁性の基板である。４２は基板４１の上面の側部から側面の一部にかけて金系のスパッタリング法により設けられた金属材料からなる複数対の第１の上面電極層であり、この第１の上面電極層４２の稜線には丸みをもたせている。また基板４１の側面上に設けられた第１の上面電極層４２の面積は、基板４１の側面の面積の半分以下である。４３は前記複数対の第１の上面電極層４２に電気的に接続するように基板４１の上面に設けられた銀系の導電粉体にガラスを含有してなる複数対の第２の上面電極層である。４４は前記複数対の第２の上面電極層４３に電気的に接続するように基板４１の上面に設けられた酸化ルテニウムを主成分とする複数の抵抗層である。４５は少なくとも複数の抵抗層４４の上面を覆うように設けられたガラスまたは樹脂等からなる保護層である。４６、４７は必要に応じて第１、第２の上面電極層４２、４３を覆うように設けられ、かつはんだ付け時の信頼性等を確保できるようにしたニッケルめっき層およびはんだめっき層である。
【００３９】
以上のように構成された本発明の実施の形態２における多連チップ抵抗器の製造方法について、以下に図面を参照しながら説明する。
【００４０】
図６（ａ）〜（ｃ）および図７（ａ）〜（ｄ）は本発明の実施の形態２における多連チップ抵抗器の製造方法を示す工程図である。
【００４１】
まず、図６（ａ）に示すように、表面に後工程で短冊状および個片状に分割するために設けた複数の縦方向および横方向の分割溝４８、４９を有する耐熱性および絶縁性に優れた９６％のアルミナを含有してなるシート状基板４１の上面全体および縦方向、横方向の分割溝４８、４９内にスパッタリング工法により金を着膜する。この後、フォトリソ法により、着膜された金を所望の電極パターンとして約３００〜４００℃の温度で熱処理を行い、複数対の第１の上面電極層４２を形成する。このとき横方向の分割溝４９内まで金を着膜するため、横方向の分割溝４９の奥まで第１の上面電極層４２を形成することができる。また、この縦方向および横方向の分割溝４８、４９のシート状基板４１の厚みに対する深さは、製造工程での取り扱い時に割れないように、基板４１の厚みの半分以下になるように形成されている。
【００４２】
次に、図６（ｂ）に示すように、複数対の第１の上面電極層４２の一部に重なるようにシート状基板４１の上面に銀系の導電粉体とガラスとを含有してなる電極ペーストを印刷後、約８５０℃で焼成して複数対の第２の上面電極層４３を形成する。
【００４３】
次に、図６（ｃ）に示すように、複数対の第２の上面電極層４３間を電気的に接続するようにシート状基板４１の上面に酸化ルテニウムを主成分とする抵抗ペーストを印刷後、約８５０℃で焼成して複数の抵抗層４４を形成する。
【００４４】
次に、図７（ａ）に示すように、抵抗層４４の抵抗値を所定の値に修正するために、ＹＡＧレーザーでトリミング溝５０を施してトリミングを行う。このとき、抵抗値測定用のトリミングプローブは、第２の上面電極層４３上にセットしてトリミングを行う。
【００４５】
次に、図７（ｂ）に示すように、抵抗値修正済みの抵抗層４４を保護するため、少なくとも抵抗層４４を覆うようにガラスを主成分とするペーストを印刷し、約６００℃で焼成して保護層４５を形成する。この場合、横方向に並ぶ複数の抵抗層４４を縦方向の分割溝４８を跨いで連続して覆うように保護層４５の印刷パターンを形成してもよい。
【００４６】
次に、図７（ｃ）に示すように、第１の上面電極層４２、抵抗層４４、トリミング溝５０、保護層４５を形成したシート状基板４１を横方向の分割溝４９に沿って分割し、短冊状基板５１を形成する。このとき、短冊状基板５１の長手方向の側面には、先に形成した第１の上面電極層４２が横方向の分割溝４９の深さまで形成された状態になっている。
【００４７】
最後に、図７（ｄ）に示すように、露出している第１、第２の上面電極層４２、４３にめっきを施すための準備工程として、短冊状基板５１を縦方向の分割溝４８に沿って分割し、個片状の基板５２を形成する。そして露出している第１、第２の上面電極層４２、４３を覆うように電気めっきによって、ニッケルめっき層（図示せず）と、はんだめっき層（図示せず）とを形成して、多連チップ抵抗器を製造するものである。
【００４８】
以上のように構成、かつ製造された本発明の実施の形態２における多連チップ抵抗器をプリント基板等の実装基板にはんだ付けで実装した状態について説明する。
【００４９】
図８（ａ）は本発明の実施の形態２における多連チップ抵抗器の実装状態を示す断面図、図８（ｂ）は同上面図である。本発明の実施の形態２における多連チップ抵抗器を保護層４５を下にしてプリント基板等の実装基板のはんだランドパターン５３にはんだ付けで実装した場合、図８（ａ）に示すように、基板４１の側面に設けられた側面電極層（図示せず）の面積が小さいため、基板４１の側面にはほとんどはんだが付かず、このはんだによるフィレット５４がわずかに形成されるのみとなる。すなわち、基板４１の側部に設けられた第１、第２の上面電極層（図示せず）で実装基板のはんだランドパターン５３にはんだ付けされるため、このはんだによるフィレット５４がわずかに形成された状態となる。このとき、図８（ｂ）の実装状態の上面図に示すように、多連チップ抵抗器の部品面積５５に対して側面をはんだ付けする面積５６は小さくなり、その結果、これらを合わせた実装面積５７を低減させることができるものである。
【００５０】
また、図８（ｂ）のように、部品面積５５と側面をはんだ付けするために必要な面積５６とを合わせた面積が実装面積５７となる場合、例えば１．０×１．０ｍｍサイズの多連チップ抵抗器を実装して従来構造の製品と実装面積を比較すると、約２０％の縮小化を図ることができるものである。よって、本発明の構成によれば、基板４１の側面に設けられた電極の面積が小さいため、この多連チップ抵抗器をプリント基板等の実装基板に実装した際、実装面積に占めるはんだ付け面積を低減させることができるとともに、フィレット５４を小さく形成できるため、使用するはんだの量を低減させることができるものである。
【００５１】
なお、本発明の実施の形態２において、はんだめっき層４７と保護層４５とを面一またははんだめっき層４７の高さを保護層４５より高くすることにより、はんだめっき層４７と実装時のランドパターン５３との隙間が生じにくくなって、実装品質をさらに向上させることができるものである。
【００５２】
また、本発明の実施の形態２において、複数対の上面電極層４２、複数の第２の上面電極層４３、複数の抵抗層４４および保護層４５を（表２）に示す組み合わせとしたときには、（表２）に示すように、他の特性を向上させることができるものである。
【００５３】
【表２】

【００５４】
【発明の効果】
以上のように本発明の多連チップ抵抗器の製造方法によれば、複数対の上面電極層が、基板の上面の側部から側面の一部にかけて設けられており、そして基板の側面に設けられている上面電極層は基板の厚みの半分以外であり、さらにこの上面電極層は、基板の側面全体ではなく、側面の一部のみに設けられているため、この多連チップ抵抗器を実装基板にはんだ付けで実装した際、はんだフィレットが形成される部分を小さくすることができ、これにより、実装面積に占めるはんだ付け面積を低減させることができるものである。また、多連チップ抵抗器であるため、チップ抵抗器単品のものに比べて、はんだフィレットを複数対形成する必要がなく、これにより、はんだ付けによる実装時に必要なはんだランドパターンの面積をより小さくすることができるため、さらに実装面積を低減させることができるという効果を奏するものである。
【図面の簡単な説明】
【図１】
本発明の実施の形態１における多連チップ抵抗器の断面図
【図２】
（ａ）〜（ｃ）同多連チップ抵抗器の製造方法を示す工程図
【図３】
（ａ）〜（ｃ）同多連チップ抵抗器の製造方法を示す工程図
【図４】
（ａ）同多連チップ抵抗器の実装状態を示す断面図
（ｂ）同多連チップ抵抗器の実装状態を示す上面図
【図５】
本発明の実施の形態２における多連チップ抵抗器の断面図
【図６】
（ａ）〜（ｃ）同多連チップ抵抗器の製造方法を示す工程図
【図７】
（ａ）〜（ｄ）同多連チップ抵抗器の製造方法を示す工程図
【図８】
（ａ）同多連チップ抵抗器の実装状態を示す断面図
（ｂ）同多連チップ抵抗器の実装状態を示す上面図
【図９】
（ａ）従来の多連チップ抵抗器の斜視図
（ｂ）従来の多連チップ抵抗器の断面図
【図１０】
（ａ）（ｂ）同多連チップ抵抗器の製造方法を示す工程図
【図１１】
（ａ）（ｂ）同多連チップ抵抗器の製造方法を示す工程図
【図１２】
（ａ）同多連チップ抵抗器の実装状態を示す断面図
（ｂ）同多連チップ抵抗器の実装状態を示す上面図
【符号の説明】
２１，４１ 基板
２２ 上面電極層
２３，４４ 抵抗層
２４，４５ 保護層
２７，４８ 縦方向の分割溝
２８，４９ 横方向の分割溝
３０，５１ 短冊状基板
３１，５２ 個片状の基板
４２ 第１の上面電極層
４３ 第２の上面電極層 [Document name] Specification [Title of invention] Manufacturing method of multiple chip resistor [Claims]
1. A step of forming a plurality of pairs of upper surface electrode layers on the upper surface of the sheet-shaped substrate and in the divided grooves by a sputtering method across the divided grooves of a sheet-shaped substrate having a dividing groove, and the plurality of pairs. A step of forming a plurality of resistance layers so as to electrically connect the upper surface electrode layers, a step of forming a protective layer so as to cover at least the plurality of resistance layers, and a step of forming the sheet-like substrate obtained in the previous step. A method for manufacturing a multiple chip resistor, comprising a step of dividing the sheet-shaped substrate into strip-shaped substrates by a dividing groove and a step of dividing the strip-shaped substrate into individual pieces.
2. A step of forming a plurality of pairs of first upper surface electrode layers on the upper surface of the sheet-shaped substrate and in the divided grooves by a sputtering method across the divided grooves of the sheet-shaped substrate having the divided grooves, and the above-mentioned step. The step of forming the plurality of pairs of the second upper surface electrode layers so as to electrically connect the plurality of pairs of the first upper surface electrode layers and the plurality of pairs of the second upper surface electrode layers so as to electrically connect the layers. The sheet-like substrate is formed into a strip-shaped substrate by a step of forming a plurality of resistance layers, a step of forming a protective layer so as to cover at least the plurality of resistance layers, and a dividing groove of the sheet-like substrate obtained in the previous step. A method for manufacturing a multiple chip resistor, comprising a step of dividing the strip-shaped substrate into individual pieces and a step of dividing the strip-shaped substrate into individual pieces.
Description: TECHNICAL FIELD [Detailed description of the invention]
[0001]
[Technical field to which the invention belongs]
The present invention relates to a method for manufacturing a multiple chip resistor used in various electronic devices.
0002.
[Conventional technology]
In recent years, with the miniaturization of electronic devices, there is an increasing demand for miniaturization in order to increase the mounting density of electronic components used for circuit boards. As for resistors, in order to reduce the mounting area on the mounting board, there is an increasing demand for not only small resistors but also multiple chip resistors in which independent resistance elements are one unit. There is.
0003
As a conventional resistor of this type, the one disclosed in the microfilm of Jitsugyo No. 2-79430 (Jitsukaihei No. 4-3801) is known.
0004
Hereinafter, a conventional multiple chip resistor and a method for manufacturing the same will be described with reference to the drawings.
0005
9 (a) is a perspective view of a conventional multiple chip resistor, and FIG. 9 (b) is a cross-sectional view of the conventional multiple chip resistor.
0006
FIG. 9 (a), in (b), 1 is a substrate made of ceramic with a cut-out 2 in the center of both sides. Reference numeral 3 denotes two pairs of upper surface electrode layers provided on the side surface of the upper surface of the substrate 1. Reference numeral 4 denotes two resistance layers provided so as to partially overlap the two pairs of upper surface electrode layers 3. Reference numeral 5 denotes a protective layer provided so as to cover the two resistance layers 4. Reference numeral 6a is two pairs of side electrode layers provided from the side surface of the substrate 1 to the side surface of the lower surface so as to partially overlap the two pairs of upper surface electrode layers 3, and the conductive paste is printed and fired. Reference numeral 6b is a solder plating or a plating layer composed of nickel and solder plating provided so as to cover the two pairs of the upper surface electrode layers 2 and the two pairs of the side electrode layers 6a.
0007
The manufacturing method of the conventional multiple chip resistor configured as described above will be described below.
0008
10 (a) and 10 (b) and 11 (a) and 11 (b) are process charts showing a method of manufacturing a conventional multiple chip resistor.
0009
First, as shown in FIG. 10 (a), a through hole 9 in a sheet-like substrate 8a made of ceramic, vertical dividing grooves 10a and lateral dividing groove 10b for dividing in a subsequent step the substrate 8a To form.
0010
Next, as shown in FIG. 10 (b), the upper surface of the sheet-like substrate 8a, a plurality to the top electrode layer 3 of the plurality of pairs formed by printing, overlaps a part of the upper surface electrode layers 3 becomes more pairs The resistance layer 4 of the above is printed and formed.
0011
Next, as shown in FIG. 11 (a), after printing and forming the plurality of protective layers 5 so as to cover the entire plurality of resistance layers 3, the lateral dividing grooves 10b (FIGS. 10 (a) and 10 (b)). ) Is divided to obtain a strip-shaped substrate 8b.
0012
Next, as shown in FIG. 11 (b), coating the side surface electrode layers 6a so as to partially overlap the upper surface electrode layers 3 of the strip-shaped substrate 8b from the side surface of the strip-shaped substrate 8b toward the lower surface side After forming, the strip-shaped substrate 8b is divided along the vertical dividing groove 10a to obtain an individual piece-shaped substrate (not shown).
0013
Finally, by applying solder plating or nickel and solder plating on the surface of the portion of the upper surface electrode layers 3 and the side electrode layers 6a, FIG. 9 (a), forming a plating layer 6b as (b), the A conventional multi-chip resistor was manufactured.
0014.
[Problems to be Solved by the Invention]
However, in the above-mentioned conventional configuration, when this multiple chip resistor is soldered to a mounting board such as a printed circuit board, the multiple chip resistor is shown in the cross-sectional view showing the mounting state of FIG. 12 (a). The vessel is soldered to the solder land pattern 12 of the mounting board on both the side surface provided with the side electrode layer (not shown) and the side portion of the lower surface, and the fillet 13 is formed by this solder. In this case, as shown in the top view of the mounting state of FIG. 12 (b), the requires area 15 for soldering the side surfaces in addition to the component area 14 of the array type chip resistor 11, mounting the total area of these 16 is required. Moreover, in order to improve the mounting density, the smaller the external dimensions of the parts, the larger the ratio of the soldered area to the mounting area, and as a result, the mounting density for miniaturizing electronic devices is improved. Had the problem of limitations.
0015.
The present invention solves the above-mentioned conventional problems, and an object of the present invention is to provide a method for manufacturing a multiple chip resistor capable of reducing the soldering area occupying the mounting area when mounted on a mounting board.
0016.
[Means for solving problems]
In order to achieve the above object, a plurality of methods for manufacturing a multiple chip resistor of the present invention are performed by a sputtering method on the upper surface of the sheet-shaped substrate and in the divided grooves across the divided grooves of the sheet-shaped substrate having the divided grooves. A step of forming a pair of top electrode layers, a step of forming a plurality of resistance layers so as to electrically connect the plurality of pairs of top electrode layers, and a step of forming a protective layer so as to cover at least the plurality of resistance layers. A step of dividing the sheet-shaped substrate into strip-shaped substrates by a dividing groove of the sheet-shaped substrate obtained in the previous step, and a step of dividing the strip-shaped substrate into individual pieces. According to this manufacturing method, it is possible to reduce the soldering area occupying the mounting area when the multiple chip resistor obtained by this manufacturing method is mounted on a mounting board such as a printed circuit board. Further, since it is a multiple chip resistor, the area of the solder land pattern required for mounting by soldering can be made smaller than that of a single chip resistor.
[0017]
BEST MODE FOR CARRYING OUT THE INVENTION
According to the first aspect of the present invention, a plurality of pairs of upper surface electrode layers are formed on the upper surface of the sheet-shaped substrate and in the divided grooves by a sputtering method so as to straddle the divided grooves of the sheet-shaped substrate having the divided grooves. A step, a step of forming a plurality of resistance layers so as to electrically connect the plurality of pairs of upper surface electrode layers, a step of forming a protective layer so as to cover at least the plurality of resistance layers, and a step obtained in the previous step. The sheet-shaped substrate is divided into strip-shaped substrates by the divided grooves of the sheet-shaped substrate, and the strip-shaped substrate is divided into individual pieces. According to this manufacturing method, the substrate is divided. Since the electrodes are formed only on a part of the side surface, not on the entire side surface, when this multiple chip resistor is soldered to the mounting board, the part where the solder fillet is formed can be reduced. Therefore, it has an effect that the soldering area occupying the mounting area can be reduced.
0018
The invention according to claim 2 of the present invention is a plurality of pairs of first upper surface electrode layers by a sputtering method in the upper surface of the sheet-shaped substrate and in the divided grooves straddling the divided grooves of the sheet-shaped substrate having the divided grooves. A step of forming a plurality of pairs of the second upper surface electrode layers so as to be electrically connected to the plurality of pairs of the first upper surface electrode layers, and a step of forming the plurality of pairs of the second upper surface electrode layers. In the step of forming a plurality of resistance layers so as to electrically connect the two, a step of forming a protective layer so as to cover at least the plurality of resistance layers, and a dividing groove of the sheet-like substrate obtained in the previous step. It includes a step of dividing the sheet-shaped substrate into strip-shaped substrates and a step of dividing the strip-shaped substrate into individual pieces. According to this manufacturing method, not the entire side surface of the substrate but a part of the side surface thereof. Since the electrodes are formed only on the mounting board, when this multiple chip resistor is mounted on the mounting board by soldering, the portion where the solder fillet is formed can be reduced, thereby reducing the soldering area occupying the mounting area. It has the effect of being able to reduce it.
0019
(Embodiment 1 )
Hereinafter, the multiple chip resistor according to the first embodiment of the present invention and a method for manufacturing the same will be described with reference to the drawings.
0020
FIG. 1 is a cross-sectional view of the multiple chip resistor according to the first embodiment of the present invention.
0021.
In FIG. 1 , reference numeral 21 denotes an insulating substrate containing 96% alumina. Reference numeral 22 denotes a plurality of pairs of upper surface electrode layers made of a metal material provided by a gold-based sputtering method from a side portion to a part of the upper surface surface of the substrate 21 , and the ridgeline of the upper surface electrode layer 22 is rounded. There is. The area of the upper surface electrode layers 22 provided on the side surface of the substrate 21 is less than half the area of the side surface of the substrate 21. Reference numeral 23 denotes a plurality of resistance layers containing ruthenium oxide as a main component, which are provided on the upper surface of the substrate 21 so as to be electrically connected to the plurality of pairs of upper surface electrode layers 22. Reference numeral 24 denotes a protective layer made of glass, resin or the like provided so as to cover at least the upper surfaces of the plurality of resistance layers 23. Reference numerals 25 and 26 are a nickel plating layer and a solder plating layer, which are provided so as to cover the upper surface electrode layer 22 as needed and can ensure reliability at the time of soldering.
0022.
The method for manufacturing the multiple chip resistor according to the first embodiment of the present invention configured as described above will be described below with reference to the drawings.
[0023]
2 (a) to 2 (c) and 3 (a) to 3 (c) are process diagrams showing a method for manufacturing a multiple chip resistor according to the first embodiment of the present invention.
0024
First, as shown in FIG. 2 (a), heat resistance and insulation have a plurality of vertical and horizontal dividing grooves 27 , 28 provided on the surface for dividing into strips and individual pieces in a later process. Gold is deposited on the entire upper surface of the sheet-shaped substrate 21 containing 96% alumina, and in the dividing grooves 27 and 28 in the vertical and horizontal directions by a sputtering method. Then, by the photolithography method, the film-formed gold is heat-treated at a temperature of about 300 to 400 ° C. as a desired electrode pattern to form a plurality of pairs of upper surface electrode layers 22. At this time, since the gold is applied to the inside of the dividing groove 28 in the lateral direction, the upper surface electrode layer 22 can be formed to the depth of the dividing groove 28 in the lateral direction. The depth to the thickness of the sheet-like substrate 21 of the vertical and horizontal dividing grooves 27, 28 so as not crack during handling in the manufacturing process, half to be less than the thickness of the sheet-like substrate 21 It is formed.
0025
Next, as shown in FIG. 2 (b), after printing a resistance paste containing ruthenium oxide as a main component on the upper surface of the sheet-shaped substrate 21 so as to electrically connect a plurality of pairs of the upper surface electrode layers 22, about A plurality of resistance layers 23 are formed by firing at 850 ° C.
0026
Next, as shown in FIG. 2 (c), to modify the resistance value of the resistive layer 23 to a predetermined value, trimming by performing trimming groove 29 in YAG laser. At this time, the trimming probe for measuring the resistance value is set on the upper surface electrode layer 22 for trimming.
[0027]
Next, as shown in FIG. 3 (a), in order to protect the resistance value corrected for the resistive layer 23, and printing a paste composed mainly of glass so as to cover at least the resistance layer 23, fired at about 600 ° C. To form the protective layer 24. In this case, the print pattern of the protective layer 24 may be formed so as to continuously cover the plurality of resistance layers 23 arranged in the horizontal direction across the division grooves 27 in the vertical direction.
[0028]
Next, as shown in FIG. 3 (b), the upper surface electrode layers 22, the resistance layer 23, the trimming groove 29 is divided along a sheet-like substrate 21 to form a protective layer 24 in the lateral direction of the dividing groove 28, the strip The shape substrate 30 is formed. At this time, the upper surface electrode layer 22 formed earlier is formed on the side surface of the strip-shaped substrate 30 in the longitudinal direction to the depth of the dividing groove 28 in the lateral direction.
[0029]
Finally, as shown in FIG. 3 (c), as a preparation step for plating the upper surface electrode layers 22 exposed, and divided along the strip-shaped substrate 30 in the longitudinal direction of the dividing grooves 27, pieces A shaped substrate 31 is formed. Then, a nickel plating layer (not shown) and a solder plating layer (not shown) are formed by electroplating so as to cover the exposed upper surface electrode layer 22, and a multiple chip resistor is manufactured. Is.
[0030]
A state in which the multiple chip resistor according to the first embodiment of the present invention, which is configured and manufactured as described above, is soldered to a mounting substrate such as a printed circuit board will be described.
0031
FIG. 4A is a cross-sectional view showing a mounted state of the multiple chip resistor according to the first embodiment of the present invention, and FIG. 4B is a top view of the same. When the multiple chip resistor according to the first embodiment of the present invention is soldered to the solder land pattern 32 of a mounting board such as a printed circuit board with the protective layer 24 facing down, as shown in FIG. 4A. Since the area of the side electrode layer (not shown) provided on the side surface of the substrate 21 is small, almost no solder is attached to the side surface of the substrate 21, and the fillet 33 formed by this solder is only slightly formed. That is, the upper surface electrode layer (not shown) provided on the side portion of the substrate 21 is soldered to the solder land pattern 32 of the mounting substrate, and the fillet 33 formed by this solder is slightly formed. At this time, as shown in the top view of the mounted state of FIG. 4 (b), the area 35 for soldering the side surface is smaller than the component area 34 of the multiple chip resistor, and as a result, these are combined and mounted. The area 36 can be reduced.
[0032]
Further, as shown in FIG. 4B, when the total area of the component area 34 and the area 35 required for soldering the side surface is the mounting area 36, for example, a large number of 1.0 × 1.0 mm size. Comparing the mounting area with a product having a conventional structure by mounting a continuous chip resistor, it is possible to reduce the size by about 20%. Therefore, according to the configuration of the present invention, since the area of the electrodes provided on the side surface of the substrate 21 is small, when this multiple chip resistor is mounted on a mounting board such as a printed circuit board, the soldering area occupying the mounting area. In addition to being able to reduce the amount of solder used, the amount of solder used can be reduced because the fillet 33 is formed to be small.
0033
In the first embodiment of the present invention, the solder plating layer 26 and the protective layer 24 are flush with each other, or the height of the solder plating layer 26 is made higher than that of the protective layer 24, so that the solder plating layer 26 and the land at the time of mounting are landed. It is possible to further improve the mounting quality because a gap with the pattern 32 is unlikely to occur.
0034
Further, in the first embodiment of the present invention, when the combination shown top electrode layer 22 of the plurality of pairs, a plurality of resistance layers 23 and a protective layer 24 in (Table 1), as shown in (Table 1), the other It is possible to improve the characteristics of.
0035.
[Table 1 ]

0036
(Embodiment 2 )
Hereinafter, the multiple chip resistor according to the second embodiment of the present invention and a method for manufacturing the same will be described with reference to the drawings.
0037
FIG. 5 is a cross-sectional view of the multiple chip resistor according to the second embodiment of the present invention.
[0038]
In FIG. 5 , reference numeral 41 denotes an insulating substrate containing 96% alumina. Reference numeral 42 denotes a plurality of pairs of first upper surface electrode layers made of a metal material provided by a gold-based sputtering method from a side portion to a part of the upper surface surface of the substrate 41 , and a ridge line of the first upper surface electrode layer 42. Is rounded. The area of the first upper surface electrode layer 42 provided on the side surface of the substrate 41 is less than half the area of the side surface of the substrate 41. Reference numeral 43 denotes a plurality of pairs of second upper surface electrodes formed by containing glass in a silver-based conductive powder provided on the upper surface of the substrate 41 so as to be electrically connected to the plurality of pairs of the first upper surface electrode layers 42. It is a layer. Reference numeral 44 denotes a plurality of resistance layers containing ruthenium oxide as a main component, which are provided on the upper surface of the substrate 41 so as to be electrically connected to the plurality of pairs of the second upper surface electrode layers 43. Reference numeral 45 denotes a protective layer made of glass, resin or the like provided so as to cover the upper surfaces of at least a plurality of resistance layers 44. Reference numerals 46 and 47 are nickel-plated layers and solder-plated layers that are provided so as to cover the first and second upper surface electrode layers 42 and 43 as needed and that can ensure reliability during soldering. ..
[0039]
The method for manufacturing the multiple chip resistor according to the second embodiment of the present invention configured as described above will be described below with reference to the drawings.
0040
6 (a) to 6 (c) and 7 (a) to 7 (d) are process diagrams showing a method for manufacturing a multiple chip resistor according to the second embodiment of the present invention.
[0041]
First, as shown in FIG. 6 (a), heat resistance and insulation have a plurality of vertical and horizontal dividing grooves 48 and 49 provided on the surface for dividing into strips and individual pieces in a later process. Gold is deposited on the entire upper surface of the sheet-shaped substrate 41 containing 96% alumina, and in the dividing grooves 48 and 49 in the vertical and horizontal directions by a sputtering method. Then, by the photolithography method, the film-formed gold is heat-treated at a temperature of about 300 to 400 ° C. as a desired electrode pattern to form a plurality of pairs of the first upper surface electrode layers 42. At this time, since the gold is applied to the inside of the dividing groove 49 in the lateral direction, the first upper surface electrode layer 42 can be formed to the depth of the dividing groove 49 in the lateral direction. Further, the depth of the vertical and horizontal dividing grooves 48 and 49 with respect to the thickness of the sheet-shaped substrate 41 is formed so as to be less than half the thickness of the substrate 41 so as not to be cracked during handling in the manufacturing process. ing.
[0042]
Next, as shown in FIG. 6 (b), contains a conductive powder and glass silver based on the upper surface of the sheet substrate 41 so as to overlap a portion of the first top electrode layer 42 of the plurality of pairs After printing, the electrode paste is fired at about 850 ° C. to form a plurality of pairs of second top electrode layers 43 .
[0043]
Next, as shown in FIG. 6 (c), a resistance paste containing ruthenium oxide as a main component is printed on the upper surface of the sheet-like substrate 41 so as to electrically connect a plurality of pairs of the second upper surface electrode layers 43. After that, it is fired at about 850 ° C. to form a plurality of resistance layers 44.
[0044]
Next, as shown in FIG. 7 (a), in order to modify the resistance value of the resistive layer 44 to a predetermined value, trimming by performing trimming groove 50 in YAG laser. At this time, the trimming probe for measuring the resistance value is set on the second upper surface electrode layer 43 to perform trimming.
0045
Next, as shown in FIG. 7 (b), for protecting the resistance value corrected for the resistive layer 44, and printing a paste composed mainly of glass so as to cover at least the resistance layer 44, fired at about 600 ° C. To form the protective layer 45. In this case, the print pattern of the protective layer 45 may be formed so as to continuously cover the plurality of resistance layers 44 arranged in the horizontal direction across the division grooves 48 in the vertical direction.
[0046]
Next, as shown in FIG. 7 (c), divided along the first upper surface electrode layers 42, the resistance layer 44, the trimming groove 50, the sheet-like substrate 41 to form a protective layer 45 in the lateral direction of the dividing grooves 49 Then, the strip-shaped substrate 51 is formed. At this time, the first upper surface electrode layer 42 formed earlier is formed on the side surface of the strip-shaped substrate 51 in the longitudinal direction to the depth of the division groove 49 in the lateral direction.
[0047]
Finally, as shown in FIG. 7 (d), first exposed, as a preparation step for plating the second upper surface electrode layers 42, 43, a strip-shaped substrate 51 in the longitudinal dividing grooves 48 It is divided along the above to form an individual piece-shaped substrate 52 . Then, a nickel plating layer (not shown) and a solder plating layer (not shown) are formed by electroplating so as to cover the exposed first and second upper surface electrode layers 42 and 43. It manufactures continuous chip resistors.
0048
A state in which the multiple chip resistor according to the second embodiment of the present invention, which is configured and manufactured as described above, is soldered to a mounting substrate such as a printed circuit board will be described.
[0049]
FIG. 8A is a cross-sectional view showing a mounted state of the multiple chip resistor according to the second embodiment of the present invention, and FIG. 8B is a top view of the same. When the multiple chip resistor according to the second embodiment of the present invention is soldered to the solder land pattern 53 of a mounting board such as a printed circuit board with the protective layer 45 facing down, as shown in FIG. 8 (a). Since the area of the side electrode layer (not shown) provided on the side surface of the substrate 41 is small, almost no solder is attached to the side surface of the substrate 41, and the fillet 54 formed by this solder is only slightly formed. That is, since the first and second upper surface electrode layers (not shown) provided on the side portion of the substrate 41 are soldered to the solder land pattern 53 of the mounting substrate, a fillet 54 formed by this solder is slightly formed. It will be in a state of being soldered. At this time, as shown in the top view of the mounted state of FIG. 8B, the area 56 for soldering the side surface is smaller than the component area 55 of the multiple chip resistor, and as a result, these are combined and mounted. The area 57 can be reduced.
0050
Further, as shown in FIG. 8B, when the total area of the component area 55 and the area 56 required for soldering the side surface is the mounting area 57, for example, a large number of 1.0 × 1.0 mm size. Comparing the mounting area with a product having a conventional structure by mounting a continuous chip resistor, it is possible to reduce the size by about 20%. Therefore, according to the configuration of the present invention, since the area of the electrodes provided on the side surface of the substrate 41 is small, when this multiple chip resistor is mounted on a mounting board such as a printed circuit board, the soldering area occupying the mounting area. The amount of solder used can be reduced because the fillet 54 can be formed to be small.
0051
In the second embodiment of the present invention, the solder plating layer 47 and the protective layer 45 are flush with each other, or the height of the solder plating layer 47 is made higher than that of the protective layer 45, so that the solder plating layer 47 and the land at the time of mounting are landed. The gap with the pattern 53 is less likely to occur, and the mounting quality can be further improved.
[0052]
In the second embodiment of the present invention, when the combination shown top electrode layer 42 of the plurality of pairs, the plurality of second upper surface electrode layers 43, a plurality of resistive layers 44 and the protective layer 45 (Table 2) As shown in (Table 2 ), other characteristics can be improved.
[0053]
[Table 2 ]

0054
【Effect of the invention】
According to the manufacturing method of multiple-chip resistor of the present invention as described above, the upper surface electrode layer pairs are provided over the portion of the side surface from the side of the upper surface of the substrate, and provided on the side surface of the substrate is in the upper surface electrode layers are is other than half the thickness of the substrate, further the upper electrode layer, not the entire side surface of the substrate, because it is provided only on a part of the side surface, mounting the multiple-chip resistor When the solder fillet is formed on the substrate by soldering, the portion where the solder fillet is formed can be reduced, whereby the soldering area occupying the mounting area can be reduced. Moreover, since a multiple-chip resistor, as compared with the chip resistor separately, it is not necessary to a plurality of pairs form a solder fillet, thereby more reducing the area of the soldering land pattern required when mounting by soldering Therefore, the mounting area can be further reduced.
[Simple explanation of drawings]
FIG. 1
FIG. 2 is a cross-sectional view of the multiple chip resistor according to the first embodiment of the present invention.
(A) to (c) FIG. 3 is a process diagram showing a method for manufacturing the same multiple chip resistor.
(A) to (c) FIG. 4 is a process diagram showing a method for manufacturing the same multiple chip resistor.
(A) Cross-sectional view showing the mounted state of the multiple chip resistor (b) Top view showing the mounted state of the multiple chip resistor [FIG. 5]
FIG. 6 is a cross-sectional view of a multiple chip resistor according to a second embodiment of the present invention.
(A) to (c) FIG. 7 is a process diagram showing a method for manufacturing the same multiple chip resistor.
(A) to (d) Process diagrams showing a method for manufacturing the same multiple chip resistor (FIG. 8 ).
(A) Cross-sectional view showing the mounted state of the multiple chip resistor (b) Top view showing the mounted state of the multiple chip resistor [FIG. 9 ]
(A) a perspective view of a conventional multiple-chip resistor (b) cross-sectional view of a conventional multiple-chip resistor [10]
(A) (b) Process diagram showing a method of manufacturing the same multiple chip resistor (FIG. 11 ).
(A) (b) Process diagram showing a method of manufacturing the same multiple chip resistor (FIG. 12 ).
(A) Cross-sectional view showing the mounted state of the multiple chip resistor (b) Top view showing the mounted state of the multiple chip resistor [Explanation of reference numerals]
21, 41 board
22 Top electrode layer 23, 44 Resistance layer 24, 45 Protective layer 27, 48 Vertical division groove 28, 49 Horizontal division groove 30, 51 Strip-shaped substrate
31 and 52 piece-shaped substrates
42 First top electrode layer
43 Second top electrode layer

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