JP2000315121A - Rtc circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a real time clock(RTC) circuit capable of highly accurately correcting time by simple constitution without increasing current consumption and the size of equipment. SOLUTION: When power supply for the equipment is turned on, an operation control part 60 controls the operation of a reference oscillator 30 and a frequency error detector 40 and the detector 40 measures the frequency error of a reference clock generated by a clock oscillator 10 by using a highly accurate reference clock generated by the oscillator 30. The frequency error is always inputted to an oscillator 50 with a correcting function. The oscillator 50 cumulatively adds a fixed value previously set by a digital oscillator to be driven by a reference clock whose frequency is divided by a frequency divider 20 and the frequency error by data consisting of the number of bits corresponding to requested accuracy, generates a clock based on the most significant bit(MSB) of the cumulatively added result, and when the accumulation of the frequency error reaches the MSB, corrects the generated clock.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to R
It relates to a TC (Real Time Clock) circuit.

[0002]

2. Description of the Related Art As is well known, the time correction of an RTC circuit provided in a conventional portable device such as a portable telephone is disclosed in Japanese Patent Application Laid-Open No. H07-197007.
As described in -31289, etc., correction is mainly performed by calculation of the CPU of the device, or correction based on a time signal or reference time information from an artificial satellite or the like.

The correction by the calculation of the CPU of the device is performed by the RTC
The frequency shift of the basic clock of the circuit is measured by TCXO, and the CPU corrects the time based on the measurement result. Thus, when the time is corrected using the CPU,
There is a problem that current consumption is large.

On the other hand, if the interval (correction cycle) of correction by the CPU is increased to reduce current consumption, many time errors will be corrected collectively.
Poor response to correction. In this case, if the frequency shift of the basic clock of the RTC circuit occurs earlier than the correction cycle due to temperature drift or the like, erroneous correction will be performed, and in the worst case, the time may oscillate. is there.

On the other hand, when time correction is performed based on time information or time information serving as a reference from an artificial satellite (GPS satellite) or the like, a configuration for acquiring such information is required, which leads to an increase in the size of the device and a portable device. Has the problem of being unsuitable.

[0006]

When the time is corrected in the conventional RTC circuit, there is a problem that the current consumption increases and the size of the device increases. SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and provides an RTC circuit capable of performing time correction with high accuracy with a simple configuration without increasing current consumption or increasing the size of equipment. With the goal.

[0007]

In order to achieve the above-mentioned object, the present invention provides an RTC (Real Tim Clock) for performing pulse generation.
e Clock) circuit, a first oscillating means which operates constantly to generate a basic clock, and a reference which operates in response to an instruction through a control signal and which is faster and more accurate than the basic clock of the first oscillating means. Using a clock, a frequency error detecting means for detecting a frequency error by counting a basic clock for a predetermined gate time, and a clock operating according to the basic clock and corresponding to the frequency error obtained by the frequency error detecting means. And a second oscillating means for generating.

In the RTC circuit having the above configuration, a frequency error of the basic clock is detected using a reference clock that is faster and more accurate than the basic clock, and a clock corresponding to the frequency error is generated.

Therefore, according to the RTC circuit having the above configuration, there is no need to perform calculations by the CPU or obtain other time information to perform correction, so that the RTC circuit can be simplified without increasing current consumption or increasing the size of the device. With the configuration, time correction can be performed with high accuracy.

Further, according to the present invention, the second oscillating means includes:
The frequency error represented by a predetermined bit width and a predetermined value are cumulatively added for each basic clock, and a clock corresponding to a specific bit of the addition result is generated.

Therefore, according to the RTC circuit having the above configuration, a corrected clock is generated when the accumulation of the frequency error is carried over to the specific bit. For this reason, since the clock corrected by the accumulator can be generated, the time can be corrected with high accuracy with a simple configuration.

Further, the present invention is characterized in that there is provided first operation control means for operating the frequency error detection means through a control signal every time a predetermined time elapses. Therefore, according to the RTC circuit having the above configuration, the first
If it is not necessary to detect the frequency error with high frequency, such as the clock frequency fluctuating due to the aging of the oscillating means or the temperature fluctuation, the generation of the high-speed and high-precision reference clock can be stopped. Current consumption can be reduced.

Still further, the present invention is characterized in that there is provided second operation control means for varying the gate time of the frequency error detection means. Therefore, the RTC having the above configuration
According to the circuit, the detection accuracy of the frequency error can be changed by changing the gate time as required, so that
The accuracy of the clock generated by the RTC circuit can be adjusted.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a configuration of an RTC circuit according to an embodiment of the present invention.
The RTC circuit includes a clock oscillator 10, a frequency divider 20,
Reference oscillator 30, frequency error detector 40, oscillator 50 with correction function, operation control unit 60, clock counter 7
0.

The clock oscillator 10 has a frequency of 100 ppm for a clock.
An oscillator for generating a basic clock having relatively low accuracy is output to the frequency divider 20 and the frequency error detector 40. Here, the frequency F _t of the basic clock, and 32.768kHz.

The frequency divider 20 divides the basic clock by 2 ^N. The frequency divider 20 includes n (1 ≦ N ≦ n) flip-flops 21 as shown in FIG.
It is composed of an asynchronous counter using 1 to 21n to reduce current consumption.

The selection circuit 22 selectively outputs the basic clock divided by 2 ^N among the basic clocks divided by the flip-flops 211 to 21n to the oscillator with correction function 50. Note that N is a value specified by an operation control unit 60 described later.

The reference oscillator 30 uses a TCXO or the like to generate a reference clock having a precision of several ppm higher than that of the clock oscillator 10.
The operation is controlled by The generated reference clock is output to the frequency error detector 40. Here, the frequency F _r of the reference clock, 14.4 MHz
And

The frequency error detector 40 detects a frequency error occurring in the basic clock based on the reference clock. The frequency error detector 40 is, for example, as shown in FIG.
As shown in (1), it comprises a gate generation counter 41 and an error measurement counter 42, and these operations are controlled by an operation control unit 60.

The gate generation counter 41 has a clock oscillator 1
The basic clock generated at 0 is counted, and a gate signal having a gate width T set in advance through the operation control unit 60 is generated. Here, the gate width T is
If “32768” is set and there is no error in the basic clock, the frequency of the basic clock is 32.768 kHz.
Because of z, the gate generation counter 41 generates a gate signal for 1 second when there is no error in the basic clock.

The error measuring counter 42 is provided with the reference oscillator 3
The reference clock generated at 0 is counted, and the gate signal generated at the gate generation counter 41 is enabled.

The error measuring counter 42 obtains the difference between the count value counted within the time set by the gate signal and the expected value E set in advance through the operation control unit 60, and calculates this difference as the frequency error. Is output to the oscillator 50 with the correction function.

It should be noted that the frequency error once obtained is determined by the oscillator 50 with the correction function until a new frequency error is obtained even if the error measuring counter 42 is in an operation stopped state.
Continues to be output to

Here, the reference clock is 14.4M.
In Hz, when there is no error in the basic clock, the expected value E is “14400” because the gate signal is 1 sec.
000 "is set. That is, the gate width T is set to a value determined from the ratio between the frequency Ft of the basic clock and the frequency Fr of the reference clock according to the following equation. B is a bit width described later.

[0025]

(Equation 1)

The oscillator 50 with a correction function corrects the frequency error of the basic clock divided by the frequency divider 20 in accordance with the error obtained by the frequency error detector 40, and generates a corrected basic clock. This is a digital oscillator, for example, a cumulative adder as shown in FIG.

The adder 51 adds the frequency error obtained by the frequency error detector 40, the output of the flip-flop 52 described later, and an addition value A preset through the operation control unit 60, and this addition is performed. Flip-flop 52
To enter.

The flip-flop 52 operates with the basic clock divided by the frequency divider 20 and inputs its output to the adder 51. And again, flip-flop 52
Inputs a clock based on the MSB (Most Significant Bit) of the output to the clock counter 70 as a clock for clock.

The operation control section 60 controls the respective sections of the RTC circuit in an integrated manner. The operation control section 60 controls the operation of the reference oscillator 30 and the frequency error detector 40, and operates the frequency divider 20 in accordance with a user's instruction. A value N for determining the frequency, a value of the gate width T of the frequency error detector 40, an expected value E, and a value of the added value A of the adder 51 are set.

The clock counter 70 has a 60-second counter 71.
, A 60-minute counter 72, and a 24-hour counter 73, each of which measures seconds, minutes, and hours based on the basic clock corrected by the oscillator 50 with a correction function.

Next, the operation of the RTC circuit having the above configuration will be described below. In the following description, a case where N is “1”, that is, a case where the frequency divider 20 divides the frequency by 2 will be described. Since the oscillator 50 with the correction function always consumes current, the frequency of the clock selected by the selection circuit 22 is preferably low in order to reduce the current.

Reference oscillator 30 and frequency error detector 4
0 is controlled by the operation control unit 60 when the power of a device such as a mobile phone in which the RTC circuit is mounted is turned on, detects a frequency error, and controls the operation to stop.

After a predetermined time has elapsed,
The operation of the reference oscillator 30 and the frequency error detector 40 is controlled by the operation control unit 60, a frequency error is newly obtained, and the operations thereof are stopped and controlled.

By the operation control of the operation control unit 60 as described above, the frequency error detector 40 operates the gate generation counter 4
1, the basic clock is counted by the gate width T as shown in FIG. 5, and a gate signal is generated. And
The error measurement counter 42 counts the reference clock by enabling the gate signal, and calculates a difference from the expected value E,
That is, a frequency error is obtained. This frequency error is input to the oscillator 50 with a correction function.

In order to improve the accuracy of correcting the frequency error of the oscillator 50 having a correction function, the number of bits of data to be handled by the cumulative addition may be increased. This is the value (including one digit of the integer part).

Here, for example, if an accuracy of 1 ppm or less is required, the bit width B is set to 18 bits, that is, 2 bits.
^-17 (<1 ppm). Even if it is 18 bits, the operating frequency is sufficiently low and the increase in current consumption is negligible.

Because the frequency of the basic clock of the clock oscillator 10 is 32.768 kHz, the speed of the accumulative addition operation of the oscillator 50 with the correction function is 1/164384 seconds.
ec and operates at 32.768 kHz because the current consumption of the flip-flop of the frequency divider 20 in the preceding stage is much larger.

Here, for simplicity of explanation of the operation, it is assumed that the frequency error obtained by the frequency error detector 40 is "1" and the added value A is "1". In addition, in order to make the correction accuracy 1 ppm or less, the bit width B of the data handled by the oscillator 50 with a correction function is set to 18 bits.

In this case, as shown in FIG. 6, the output of the flip-flop 52 is added to the output (a) of the frequency divider 20 by the cumulative addition in the adder 51 as shown in FIG. Varies with value.

For this reason, M of the output of the flip-flop 52
The clock based on SB changes as shown in FIG. In other words, the frequency error cumulatively added up to time Ti is shifted up to the MSB here, so that the clock is corrected by about 0.5 cycle.

As described above, in the RTC circuit having the above configuration, when the power of the device is turned on or every time a predetermined time elapses,
The operation control unit 60 includes the reference oscillator 30 and the frequency error detector 4
0 to control the frequency error detector 40 using the highly accurate reference clock generated by the reference oscillator 30.
Measures the frequency error of the basic clock generated by the clock oscillator 10 and constantly inputs it to the oscillator 50 with the correction function.

The oscillator 50 with a correction function is a digital oscillator that operates on the basic clock divided by the frequency divider 20 and converts the fixed value A and the frequency error with the number of bits according to the required precision. The expression is used to perform cumulative addition, and a clock is generated using the MSB of the cumulative addition result. For this reason, in the oscillator with a correction function, when the accumulation of the frequency error is advanced to the MSB, the generated clock is corrected.

Therefore, according to the RTC circuit having the above configuration, the reference oscillator 30 and the frequency error detector 40 are operated only when the frequency error is obtained, and the digital oscillator which operates on the basic clock without depending on the operation of the CPU. Since the correction of the basic clock is performed, the time can be accurately corrected with a simple configuration without increasing the current consumption or increasing the size of the device.

The present invention is not limited to the above embodiment. In addition, it goes without saying that various modifications can be made without departing from the spirit of the present invention.

[0045]

As described above, according to the present invention, a frequency error of a basic clock is detected using a reference clock that is faster and more accurate than the basic clock, and a clock corresponding to the frequency error is generated. ing.

Therefore, according to the present invention, since there is no need to perform calculations by the CPU or obtain other time information to perform correction, it is possible to achieve a simple configuration without increasing the current consumption and the size of the device. An RTC circuit capable of accurately performing time correction can be provided.

Further, according to the present invention, the second oscillating means includes:
The frequency error represented by the predetermined bit width and the predetermined value are cumulatively added for each basic clock, and a clock corresponding to a specific bit of the addition result is generated. Therefore, when the accumulation of the frequency error is carried over to the specific bit, a corrected clock is generated, and the clock corrected by the accumulator can be generated. Thus, it is possible to provide an RTC circuit capable of performing time correction with high accuracy.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram showing a configuration of an embodiment of an RTC circuit according to the present invention.

FIG. 2 is a circuit block diagram showing a configuration of a frequency divider of the RTC circuit shown in FIG.

FIG. 3 is a circuit block diagram showing a configuration of a frequency error detector of the RTC circuit shown in FIG.

FIG. 4 is a circuit block diagram showing a configuration of an oscillator with a correction function of the RTC circuit shown in FIG. 1;

FIG. 5 is a diagram for explaining an operation of generating a gate signal in the frequency error detector shown in FIG. 3;

FIG. 6 is a view for explaining a frequency correction operation of a basic clock in the oscillator with a correction function shown in FIG. 4;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 ... Clock oscillator 20 ... Divider 211-21n ... Flip-flop 22 ... Selection circuit 30 ... Reference oscillator 40 ... Frequency error detector 41 ... Gate generation counter 42 ... Error measurement counter 50 ... Oscillator with a correction function 51 ... Adder 52: flip-flop 60: operation control unit 70: clock counter 71: 60-second counter 72: 60-minute counter 73: 24-hour counter

Claims (4)

[Claims] 1. An RTC (Real Time Clock) for generating a clock
A first oscillating means which operates constantly to generate a basic clock, and operates in response to an instruction through a control signal, and which operates at a higher speed and a higher precision than the basic clock of said first oscillating means. A frequency error detecting means for detecting a frequency error by counting the basic clock for a predetermined gate time using a clock, and operating with the basic clock and according to the frequency error obtained by the frequency error detecting means. And a second oscillating means for generating a clock. 2. The second oscillating means accumulatively adds the frequency error represented by a predetermined bit width and a predetermined value for each basic clock, and generates a clock corresponding to a specific bit of the addition result. The RTC circuit according to claim 1, wherein 3. The RTC according to claim 1, further comprising first operation control means for operating frequency error detection means through the control signal every time a predetermined time elapses. circuit. 4. The RTC circuit according to claim 1, further comprising second operation control means for varying a gate time of said frequency error detection means.