JP2000298654A - Processor element circuit, parallel calculation system and bus bridging method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce design man-hours of a processor element and a bus ridge circuit when a dedicated system is constructed as a parallel computer system by selecting an operation processing mode and a bridge mode and sharing the same LSI by a processor element and the bus bridge circuit. SOLUTION: This system is constituted of a host computer 11 and plural sheets of boards 12 on which many processor elements 14 are mounted. The host computer 11 and the respective boards 12 are connected to each other with a system bus 13. In the system, a mode selection means can select an operation processing mode and a bridge mode. A processor element circuit is used as the processor element 14 of a parallel calculation system by making it to be the operation processing mode or it can be used as a bus bridge circuit 17 for protocol conversion with the different bus of the parallel calculation system or as a part of it by making it to be the bridge mode.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus bridge device for conversion between bus protocols used in a dedicated parallel computing system for performing enormous calculations such as ab initio molecular orbital calculations and gravity many-body problems. , And a system using the bus bridge device.

[0002]

2. Description of the Related Art In the past, in the fields of drug development and material design, it has been extremely difficult to carry out experiments using actual objects. Techniques have become popular. In general, simulating such chemical phenomena requires an enormous amount of computation, and chemists have been devoting their energies to developing calculation algorithms for performing high-speed simulations. At the same time, a dedicated massively parallel computer has been devised to speed up the calculation.

As a result of such efforts, in recent years, in the field of computational chemistry, a simulation technique called ab initio molecular orbital calculation has been greatly developed. This ab initio molecular orbital calculation method will be described.

First, an outline of the ab initio molecular orbital calculation method will be described. The principle of the ab initio molecular orbital calculation method is
For example, "Shigeru Fujinaga, Molecular Orbital Method, Iwanami Shoten (1980)"
And "Osamu Kikuchi, Basic Quantum Chemistry, Asakura Shoten (1997)"
And so on. In this method, the energy of a certain molecule is calculated by calculation according to the quantum chemical principle. By finding the minimum value of the energy among the distances and arrangements between the atoms, it is possible to determine the characteristics of the material and to design the medicine.

The most frequently used method for ab initio molecular orbital calculation is a calculation method called the Hartree-Fock method (HF method). Hereinafter, the outline of the HF method will be described.

In the HF method, the Fock equation is expressed by S
It is formulated as a method to solve by the CF method. Here, assuming that the total number of atomic orbitals contained in a molecule is N and the total number of molecular orbitals expressed by a linear approximation of the atomic orbital (LCAO) is m, the Fock equation is 1 with respect to the Schrodinger equation for the whole molecule. It is expressed by a matrix expression FC = SCε (1) obtained as a result of performing the electronic approximation and the LCAO approximation. The HF method converts this Fock equation into an SCF (Self Consis
(tent field) method. By solving this equation, the energy of the molecule is obtained, and it is possible to determine whether the molecule is in a stable state based on the value.

In the equation (1), F is an N × N matrix called a Fock matrix. S is an N × N matrix called an overlap matrix, C is an N × m matrix representing coefficients, ε
Is an m × m diagonal matrix representing the energy of each electron occupying the molecular orbital.

Here, the element Frs (r, r,
s = 1 to N) is represented by the following equation.

Frs = hrs + grs = hrs + Σ [t, u = 1 to N] Ptu ((rs, tu) − (1/2) (rt, su)) (2)

The hrs in the equation (2) is an integral amount representing the energy for one electron, and is calculated by a number in proportion to N ^{2 in} one calculation of the equation (1).

In this specification, Σ [i, j =
1-N] f (i, j) is 1 to N for i and j
It is assumed that the calculation for obtaining the sum up to the above for the function f (i, j) is shown. Also, Σ [i = 1 to N] f (i)
Denotes an operation for calculating the sum of 1 to N for i for the function f (i).

Further, Ptu in the equation (2) is called a density matrix, and is expressed by using the above matrix C as follows.

Ptu = Σ (j = 1 to m) Ctj · Cju (3) Also, (rs, tu) (r, s, t, u = 1) in equation (2)
To N) are physical quantities called two-electron integrals, and are represented by the following formula using the atomic orbital χ _i (r) (i = 1 to N, where r is a coordinate).

(Rs, tu) = ∫∫χ _r (r1) χ _s (r1) (1 / r12) × χ _t (r2) χ _u (r2) dr1 · dr2 (4)

Here, r1 and r2 are independent 2
Two coordinate systems, each of which performs double integration over the entire space. R12 represents the distance between the coordinate systems r1 and r2. In this two-electron integration, r, s, t, and u are required by the number of atomic orbitals, respectively, so that a single calculation of the equation (1) requires a number proportional to N ^{4 in} one calculation.

Next, the element Srs of the overlap matrix S is represented by the following equation.

Srs = ∫χ _r (r1) χ _s (r1) dr1 (5) Since it is expressed as described above, the HF method uses m eigenvalues εi and eigenvectors Ci (i = 1 to m). However, as can be seen from the equations (2) and (3), the Fock matrix included in the equation (1) is obtained using the vector Ci representing the coefficient.
If Ci obtained by solving equation (1) is not used, Frs
Will not be determined.

Therefore, first, an appropriate value is set as an initial value of Ci, and Frs is obtained using the Ci.
Solving the eigenvalue problem of equation (1), finds a new Ci.
Next, a new F is calculated using the obtained Ci to solve the equation (1). The calculation is repeated in this manner, and the calculation is terminated when there is almost no difference between the Ci used for the calculation of F and the obtained Ci. Physically, there is no contradiction between the Coulomb field created by each electron constituting the molecule and the Coulomb field created by the nucleus at each repetition, so this method uses the SCF (self-cons
This method is called an isent field method and is widely used in molecular orbital calculations.

The number of two-electron integrals represented by the equation (1) is
Since the total number of atomic orbitals is proportional to the fourth power of N, for example, in the case of a molecule consisting of about 100 atoms that often appears in the field of biology, for example, the value of N is about 1000.
It is on the order of 100 trillion squares. Here, before calculating the two-electron integral, a method of judging a small value and cutting off the value is often used.
The number of electron integration is about 100 million, which is still a huge number.

For this reason, although the same two-electron integral is used in each iteration of the SCF method, there is no memory capacity for temporarily calculating and storing the two-electron integral. The direct method of fixing is usually used.
In the molecular orbital calculation by the direct method, since the calculation of the two-electron integral occupies most of the calculation time, it is important to speed up this part.

Here, the atomic orbit χ _i represented by the equation (4)
In general, a Gaussian function that can analytically calculate a two-electron integral is used for the calculation. As a method of calculating a high-speed two-electron integral using the atomic orbital of the Gaussian function, a conventional method is described in S. Obara and A. Saika, J.C.
hem. Phys. 84, 3963 (1986) "(hereinafter referred to as Reference 1) (hereinafter referred to as Ohara's method).

Ohara's method introduces a physical quantity called an auxiliary integral which is an extension of the two-electron integral, and is expressed in the form of a recurrence formula including the auxiliary integral. According to the recurrence formula, one two-electron integral is represented by a form of a product-sum operation including a lower-order auxiliary integral. When calculating a certain two-electron integral, first,
According to the recurrence formula, the calculation is performed by expanding to a form including only the lowest-order auxiliary integral, and then sequentially obtaining higher-order auxiliary integrals by a product-sum operation.
In other words, the calculation of the two-electron integral results in a series of product-sum operations with a particular format.

As described above, since the amount of calculation in the molecular orbital calculation becomes enormous, the calculation of two-electron integral and the like have been parallelized to reduce the calculation time. Known techniques for performing high-speed molecular orbital calculation include Japanese Patent Application Laid-Open No. 9-50 / 1990.
No. 428, Japanese Unexamined Patent Publication No. 9-50458, a method of calculating different two-electron integrals by a plurality of processors, or “Architecture of MOE for exclusive use in ultra-high-speed molecular orbital calculation” (Tech. ,
As shown in CPSY96-46, 1996-05), there is a method of performing calculation using a dedicated parallel computer.

In particular, in the molecular orbital calculation, the calculation amount of the two-electron integral is large, and this calculation is independent of each other and relatively easy to parallelize. It is faster to calculate with a high-speed dedicated computer. As described above, in recent years, calculations using a special-purpose computer for a specific application have been actively performed.

FIG. 7 shows an example of a parallel computing system as a dedicated system for performing molecular orbital calculations and the like. This system includes a host computer 1 configured using a general-purpose workstation or a PC (personal computer), and a plurality of boards 2 on which a large number of processor elements 4 are mounted. 2 is connected by a system bus 3.

Further, in each board 2, a local memory 5 is connected to each of a number of processor elements 4. Many processor elements 4 are connected through a board bus 6. The board bus 6 and the system bus 3 are connected via a bus bridge 7.

The system bus 3 is required to have high versatility in addition to high speed because it is a bus directly connected to the host computer 1. In addition, the processor element 4 must perform high-speed calculations using parameters and control variables necessary for the calculation, and therefore the board bus 6 is mainly required to have high speed.

In order to increase the speed of the board bus 6, it is necessary to reduce the load capacity of the bus.
The number of processor elements 4 connected to one board bus 6 must be reduced, and the board bus 6 itself must be shortened. For this reason, the board bus 6 on one board 2 must be separated from the board bus 6 on another board 2. In addition, a high-speed bus developed exclusively for the board bus or a new high-speed bus utilizing the latest technology is often used for the board bus 6, and such a bus is used for general-purpose PCs and workstations. Often not implemented yet.

For this reason, a bus bridge 7 for relaying protocol conversion and the like between the system bus 3 and the board bus 6 is required on each board. An example of this type of bus bridge circuit is disclosed in JP-A-6-37768.
No., etc.

[0030]

By the way, in the case of a dedicated system, it is often necessary to design a custom processor element. In particular, when a huge amount of calculations such as the molecular orbital method described above must be performed, the scale of the processor element inevitably increases, and thus the man-hour for designing the processor element is increased.

As described above, since a dedicated bus or the like is used for the board bus 6, there is no general-purpose product in the bus bridge circuit 7, and it must be newly designed. For this reason, along with the design man-hour of the processor element 4,
There is a problem that the design man-hour of the bus bridge 7 is required.

The purpose of the invention described in the above-mentioned Japanese Patent Application Laid-Open No. Hei 6-37768 is to reduce the capacity of a transfer buffer between buses. Not be. Rather, especially in the case of a dedicated system, it is important to suppress the increase in the number of design steps described above.

In view of the above, it is an object of the present invention to reduce the number of design steps for a processor element and a bus bridge circuit when a dedicated system is constructed as a parallel computing system.

[0034]

In order to achieve the above object, a processor element circuit according to the present invention has a function of performing arithmetic operations in parallel and a plurality of buses. A processor element circuit used in a parallel computing system including a bridge circuit for performing a bridge between the internal memory and the first memory, the internal memory for storing data, and a first register therein. An arithmetic unit for performing an operation on the data read from the register and storing the operation result in the internal memory or the first register; and a processor element circuit,
A mode selection unit for selecting which of a bridge mode and an operation is to be performed, and when the arithmetic processing mode is selected by the mode selection unit, the mode selection unit sets the processor operation between the processor element circuit and the external memory. When the bridge mode is selected, the interface means for inputting / outputting data between the processor element circuit and the peripheral circuit, and when the arithmetic processing mode is selected by the mode selecting means, the apparatus stands by at startup. State, becomes an operating state by a subsequent starting operation, and when the bridge mode is selected by the mode selecting means, becomes a booting state at the time of starting, and becomes an operating state by a subsequent transition operation,
Furthermore, a second register for storing data therein is provided, and is operated in accordance with an instruction sequence, so that at least the function of controlling the arithmetic unit and the external memory or the external memory or Processor means having a function of inputting and outputting data between the peripheral circuit and the second register or the first register; and supplying a specific instruction sequence to the processor means in the boot state. When the instruction sequence read from the ROM by the specific instruction sequence is stored in the internal memory, the transition operation is performed on the processor unit after the supply of the specific instruction sequence is completed, and the processor unit is in the operating state. Instruction selection means for reading an instruction sequence from the internal memory and supplying it to the processor means; The data stored in the internal memory or the external memory is read, and the data stored in the internal memory or the external memory is read and output to the external bus. External bus interface means for performing operations.

According to a second aspect of the present invention, in the processor element circuit according to the first aspect, the processor means includes means for processing an interrupt, and the interface means selects a bridge mode by the selection input. Means for inputting an interrupt from the peripheral circuit and supplying it to the processor means, wherein the external bus interface means interrupts the processor means when specific data is input from the external bus. Is provided.

According to a third aspect of the present invention, there is provided a parallel computing system having a function of performing operations in parallel, a plurality of buses, and a bridge circuit for bridging the plurality of buses. And a processor element circuit according to claim 1 or 2, wherein the processor element is set to the arithmetic processing mode by the mode selecting means, and a plurality of the processor elements are controlled by the processor element. Multiple boards to be mounted on each, and on each of the boards,
2. A first bus for connecting the external bus interface means of the plurality of processor elements to each other, a second bus for connecting the host computer and the plurality of boards, and Item 3. The processor element circuit according to Item 2, wherein a bridge mode is set by the mode selection means, the external bus interface means is connected to the first bus on each of the boards, and a conversion is made to the second bus. A bus bridge connected to the interface means through a circuit and performing protocol conversion between the first bus and the second bus with each other by the means.

According to a fourth aspect of the present invention, there is provided a bus bridge method for performing a protocol conversion between the first bus and the second bus having different protocols in the parallel computing system according to the third aspect. Receiving, from the processor element, write information including a write request, a write address, and write data for a node located outside the first bus based on a write procedure of the first bus; Writing the write data to the write address based on the write information based on the write procedure of the second bus.

Furthermore, the invention of claim 5 is a bus bridge method for performing a protocol conversion between the first bus and the second bus having different protocols in the parallel computing system according to claim 3. A read request including a read request from a node located outside the first bus, a read address, and an address of a processor element for storing read data from the processor element is written into the first bus by the processor element. A step of receiving data based on the read information, a step of reading data from the read address based on the read procedure of the second bus, and the read data being included in the read information. Write to the address of the processor element based on the write procedure of the second bus And having a forward, a.

[0039]

According to the first aspect of the present invention, the operation mode and the bridge mode can be selected by the mode selection means, and the processor element circuit is used as the processor element of the parallel computing system by setting the operation mode to the operation mode. By setting the bridge mode, the parallel computing system can be used as a bus bridge circuit for performing protocol conversion between different buses or a part thereof.

According to the second aspect of the present invention, since the processor means is made to perform interrupt processing, when the processor element circuit is used as a bus bridge circuit or a part thereof, it is input / output at an arbitrary time. Data to and from the bus can be easily processed.

According to the third aspect of the present invention, in the parallel computing system, the processor element and the bus bridge circuit can be configured by using the same processor element circuit. In addition to the reduction, the development period of the system can be shortened.

According to the fourth aspect of the present invention, when the bus bridge circuit is configured using the processor element circuit, the resources of the second bus that cannot be directly accessed for writing from the first bus are used. , Can be accessed using the writing of the first bus. Therefore, it is possible to access from the first bus without adding a special circuit.

According to the fifth aspect of the present invention, when a bus bridge circuit is configured using a processor element circuit, resources of the second bus which cannot be directly read and accessed from the first bus are used. , Can be accessed using the writing of the first bus. Therefore, it is possible to access from the first bus without adding a special circuit.

[0044]

Embodiments of the present invention will be described below with reference to the drawings.

[System Configuration] FIG. 2 is a block diagram showing a configuration of an embodiment of a parallel computing system according to the present invention. In the embodiment shown in FIG. 2, the parallel computing system is configured as a dedicated system. This system comprises a host computer 11 configured using a general-purpose workstation or a PC (personal computer); It comprises a plurality of boards 12 on which a number of processor elements 14 are mounted, and the host computer 11 and each board 12 are connected by a system bus 13.

In each board 12, each of a number of processor elements 14 has a local memory 1
5 are connected and provided. Many processor elements 14 are connected through a board bus 16. The board bus 16 and the system bus 13
They are connected via a bus bridge circuit 17.

The host computer 11 controls the entire system shown in FIG. Each board 12 performs individual calculations performed in this system in parallel. The processor element 14 of each board 12 includes therein a floating-point arithmetic unit operated by a program, and executes individual calculations (floating-point multiply-add operation) given to each board 2.
The local memory 15 stores parameters and control variables used for calculation. Each processor element 1
4 executes a calculation using the parameters and control variables stored in the local memory.

In this embodiment, the bus bridge circuit 17 and the processor element 14 are configured using a common LSI in order to reduce the number of steps for developing the bus bridge circuit 17. Details will be described later.

Next, the system bus 13 and the board bus 16 in the parallel computing system of FIG. 2 will be described.

Since the system bus 13 is connected to the host computer 11 composed of a general-purpose PC or the like, the general-purpose bus is used as described above. There are various examples of a general-purpose bus used for the system bus 13. In this embodiment, an IEEE 1394 serial bus is used. At present, the IEEE 1394 serial bus has a maximum transfer rate of 400 Mbps, and has a sufficient high-speed even though it is generally used.

The board bus 16 is a high-speed parallel bus or the like. Although there are various examples of a bus used for the board bus 16, in this embodiment, at present, a PPRAM-Li having a communication performance of up to 800 Mbps is used.
nk.

In FIG. 2, two ports are prepared in the bus bridge circuit 17 of each board 12, and each board 12 is connected in series by using these ports.
The system bus 13 is configured in a daisy chain format of the EEE1394 serial bus.

In the PPRAM-Link, as described later, in order to reduce the load capacity on the bus,
Because they are connected in a unidirectional ring by bit signals,
The connection form of the board bus 16 shown in FIG. 2 also has this shape.

Hereinafter, the PPR used for the board bus 16 will be described.
The specification of AM-Link will be described in more detail. For PPRAM-Link, refer to “PPRAM-
Overview of Link Logic Hierarchy Specification (Kyudai Univ., 0.1 Edition) "(Yamazaki et al., Tech. Rep. IEICE., ICD97-
24, 1997-05), and "Development of PPRAM-Link Interface Core" (Hashimoto et al., Information Processing Society of Japan, ARC-125-11, 1997-08). First, a connection example of the PPRAM-Link is shown in FIG.

In FIG. 4, N1 to N5 are basic structural units called PPRAM nodes. Each of the PPRAM nodes N1 to N5 has a 17-bit input terminal I
nOutputLink and output terminal OutputLink
And, as shown in the example of FIG.
The input terminal InputLink and the output terminal OutputLink of the RAM node are connected, and are connected in a unidirectional ring as a whole.

The upper 16 bits of the 17-bit signal of the input terminal InputLink or the output terminal OutputLink are the symbol signal, and the lower 1 bit is the flag signal. These signals are used as common clock signals (not shown). Synchronously, data is transferred one by one clock. Although one LSI may include a plurality of PPRAM nodes, in this embodiment, one PPRAM node is used.
The RAM node corresponds to one processor element 14.

Each of the PPRAM nodes N1 to N5 has
A unique node identifier is assigned to the entire system, and an offset address is assigned to a memory or the like in each PPRAM node. Access between the PPRAM nodes is performed using the node identifier and the offset address.

Next, with respect to communication between two PPRAM nodes, an example in which access such as read (read) and write (write) is performed from the PPRAM node N1 to the memory provided in the PPRAM node N3 in FIG. To explain. One access is called a transaction.

Such a transaction is referred to as PPRA
This is performed by exchanging packets between the M nodes.
Here, the packet is one unit of communication in the PPRAM-Link, and is the input terminal Input described above.
The signal is continuously transferred over a plurality of clocks through a 16-bit symbol signal included in the signal of the Link or the output terminal OutputLink. At this time, the above-mentioned flag signal is used for control such as packet discrimination. Furthermore, 1 clock transmitted through the symbol signal in 1 clock
6-bit data is called one symbol.

In the PPRAM-Link, as described above, since packets are connected in a unidirectional ring, packets are transferred from the PPRAM node N1 to the PPRAM node N.
3 is sent to the PPRAM node N1 → P in FIG.
The path from the PRAM node N2 to the PPRAM node N3 is used, and the packet is transferred from the PPRAM node N3 to the PPRAM.
When sent to the node N1, the PPRAM node N3 in FIG. 4 → the PPRAM node N4 → the PPRAM node N5 →
The path of the PPRAM node N1 is used.

FIG. 5 shows a communication procedure in the case of this embodiment. As described above, the PPRAM node N1 (request side) switches from the memory provided in the PPRAM node N3 (response side) to the like. FIG. 7 is a conceptual diagram showing a procedure of one transaction for performing access. Communication is performed according to the following procedure.

A request transmission packet is sent from the PPRAM node N1 to the PPRAM node N3.

A request reception packet is sent from PPRAM node N3 to PPRAM node N1.

A response transmission packet is sent from PPRAM node N3 to PPRAM node N1.

A response reception packet is sent from PPRAM node N1 to PPRAM node N3.

Here, each packet contains header information. This header information includes the node identifier of the node that issued the packet, the node identifier of the packet destination,
It contains information such as the offset address of the packet destination memory and the type of transaction (read, write, etc.). Therefore, the requesting node and the responding node can exchange packets based on the header information.

When a read request is made from the PPRAM node N1, the PPRAM node N3 adds the header and the data read from the memory to the above-mentioned response transmission packet and sends it.

Further, when a write request is issued from the PPRAM node N1, the PPRAM node N1 adds the data to be written to the PPRAM node N3 to the request transmission packet and sends the packet.

The request acknowledgment packet and the response acknowledgment packet are packets for confirming that the PPRAM node that sent the transmission packet has arrived at the destination without losing the packet in the middle of the transmission path. In addition, and
The transfer of the transmission packet and the transfer of the reception packet as described above are collectively referred to as a subaction.

As described above, one transaction in the PPRAM-Link is performed according to the procedure described above.

Next, taking the above-mentioned molecular orbital calculation as an example,
The operation of the system shown in FIG. 2 will be described. First, an outline of the calculation will be described.

As described above, in the molecular orbital calculation, the calculation amount of each two-electron integral is proportional to the fourth power of the basis number N, and each calculation can be performed independently. Also,
The computational complexity of the diagonalization of the Fock matrix represented by equation (1) is
Although proportional to the third power of N, the individual calculations are dependent on each other. In this calculation, if the absolute value of the two-electron integral is sufficiently small, the cutoff is performed as described above. However, when considering a base of a practical size, the calculation amount of the two-electron integral is smaller than that of the two-electron integral. It is far more than the calculation of the diagonalization of the matrix.

Therefore, when the molecular orbital calculation is performed by the dedicated system shown in FIG. 2, the calculation of the two-electron integral with a small amount of communication due to a large amount of calculation is performed in parallel by a plurality of processor elements 14. The calculation of the diagonalization of the Fock matrices, which have a relatively small amount of calculation and depend on each other, is performed by the host computer 11.

The two-electron integral calculated by the processor element 14 is sent to the host computer 11 and
When the host computer 11 calculates the Fock matrix elements according to the equation (2), an enormous amount of two-electron integral data must be communicated through the board bus 16 and the system bus 13. As a result, even if the two-electron integration or the Fock matrix is diagonalized at high speed, the communication speed limits the performance of the system, and the speed of the molecular orbital calculation of the system cannot be improved.

For this reason, in order to reduce the communication amount, each processor element 14 uses grs in the equation (2).
Is calculated, and the value is sent to the host computer 11. The host computer 11 calculates a Fock matrix element according to the equation (2) based on this value.

Further, since the calculation based on the above-described SCF method is performed, the density matrix element is calculated by the equation (3) every time the calculation is repeated. This calculation is also performed by the host computer 11.

Next, an outline of a specific calculation procedure by the system of FIG. 2 will be described. First, the molecular information and basis information necessary for the calculation of the two-electron integral, a program for operating the floating-point arithmetic unit inside the processor element 14 and calculating the two-electron integral and the grs, and further, other calculations It is assumed that parameters such as Taylor expansion coefficients required for the above are stored in the memory of the host computer 11 in advance.

The value of the density matrix element required for the calculation of grs used in the first iteration of the SCF method is also calculated in advance by the host computer 11 based on the expression (3) and stored in its memory. It is assumed that Further, the calculation of the two-electron integral assigned to each processor element 14 is performed in such a manner that the calculation time of each processor element 14 becomes uniform, and the calculation time of the system is minimized from the viewpoint of calculation time and communication time. 11 is determined.

After the system is started for the first time, each processor element 14
Among the data stored in 1, molecular information, base information and other parameters, the above-mentioned programs, etc. are transferred and stored in a memory inside the processor element 14 or a local memory 15 attached to the processor element 14. .

At this time, these data are first sent from the host computer 11 to the bus bridge circuit 17 on each board 12 via the IEEE 1394 serial bus which is the system bus 13, and the bus bridge circuit 17 PPRAM-L which is a board bus 16
Relay to the Ink is performed. Thereafter, the data is sent to each processor element 14 through the board bus 16. Thereafter, the host computer 11 further activates each processor element 14 through the same path, and each processor element 14 starts calculation.

As described above, since the host computer 11 determines which two-electron integral is to be calculated by a certain processor element 14, after the processor element 14 is activated, the host computer 11
, Two-electron integral information assigned to each processor element 14 or density matrix information for calculating grs from the two-electron integral is transferred.

Each processor element 14
The two-electron integral corresponding to the transferred two-electron integral information is calculated according to the above-described program. When the calculation of the two-electron integral is completed, the processor element 14 calculates
The grs is calculated by multiplying by the density matrix transferred together with the two-electron integration information.

The grs calculated in this manner is stored in the associated local memory 15 by each processor element 14, and calculation end information is sent from each processor element 14 to the host computer 11. Upon receiving the calculation end information from the processor element 14, the host computer 11 reads grs from the local memory 15.

At this time, the above-mentioned calculation end information is first transmitted from each processor element 14 to the P
The data is transferred to the bus bridge circuit 17 on the board 12 through the PRAM-Link, and relayed to the IEEE 1394 serial bus, which is the system bus 3, by the bus bridge circuit 17. After that, the calculation end information is transmitted to the system bus 1
3 to the host computer 11. Also,
When the value of grs is read from the local memory 15, the data is sent to the host computer 11 through the same route.

After that, the host computer 11 sends another two-electron integral information and density matrix information to be assigned to the processor element 14 which has completed the calculation, and the processor element calculates again grs, and Is sent back to the host computer 11. This operation is repeated until the calculation of all two-electron integrals is completed.
Since the host computer 11 has Fock matrix elements, the host computer 11 performs diagonalization.

Further, since the Fock matrix elements are repeatedly calculated by the above-described SCF method, if it is determined that further repetition is necessary after the diagonalization of the Fock matrix is completed, the host computer 11 ,
Again, the calculation of the new grs is repeated in each processor element 14 according to the procedure described above until the density matrix elements are calculated and the final result is obtained.

[Embodiment of Processor Element Circuit] As described in the section of the related art, in the case of a dedicated system, the processor element 14 and the bus bridge circuit 17 usually use dedicated LSIs, respectively. . In this embodiment, as described above, the processor element circuit used as the processor element 14 is minimally expanded and used as the bus bridge circuit 17 or a part of the bus bridge circuit 17. Thus, labor and cost for developing two types of LSIs are eliminated.

In the following description, the LSI chip of the processor element circuit that can be shared by the processor element and the bus bridge circuit will be referred to as a shared chip.

The structure of the shared chip will be described below with reference to FIGS.
This will be described with reference to FIG. FIG. 1 is a configuration diagram when the processor element 14 is configured using a shared chip.
FIG. 3 shows a bus bridge circuit 1 using a shared chip.
7 is a configuration diagram in the case of configuring No. 7; FIG.

[Configuration of Shared Chip] First, the configuration of the shared chip (processor element circuit) in this embodiment will be described with reference to FIG. FIG. 1 shows an internal configuration of a shared chip 20 according to this embodiment in a local memory 1.
5 is a block diagram shown together with a board bus 16; FIG.

As shown in FIG. 1, the shared chip 20
PU 21, floating point arithmetic unit 22, internal memory 23, local memory controller 24, peripheral circuit controller 25, multiplexer 26, load generator 27, board bus interface 28
, A processor element internal bus (abbreviated as PE bus) 30, a local memory internal bus (abbreviated as LM bus) 31, an instruction bus 32, a floating-point data bus 33, and an input terminal 34 for a mode selection signal SEL. And an interrupt control signal line 35.

The CPU 21 controls the whole of the shared chip and the whole calculation when operating as a processor element. In this example, a 32-bit CPU is used. The CPU 21 has a plurality of 32-bit integer registers therein, and these registers are used for integer operations.

The floating-point arithmetic unit (hereinafter abbreviated as FPU) 22 has a double-precision floating-point arithmetic unit therein and executes a product-sum operation at a high speed. FPU
Reference numeral 22 includes a plurality of floating-point registers capable of storing 64-bit double-precision floating-point data, and is used for the operation of the double-precision floating-point calculator.

The internal memory 23 stores instructions executed by the CPU 21, calculation results executed by the CPU 21 and the FPU 22, and the like. The internal memory 23 has a three-port configuration. Port 1 is a 32-bit read-only port connected to an instruction bus 32 via a multiplexer 26. Port 2 is a 32-bit read / write port connected to a processor element internal bus 30. Port, port 3 is F
It is a 64-bit read / write port for exchanging double precision floating point data with PU22.

A local memory controller (hereinafter referred to as LM)
C) 24 generates a chip select signal and a write signal of an external local memory connected to the shared chip 20. A peripheral circuit controller (hereinafter abbreviated as PEC) 25 generates a control signal for the peripheral circuit.

Multiplexer 26 is one of instructions from internal memory 23 or load generator 27,
This is for selecting an instruction to be input to the register 21. The load generator 27 is for generating a program for initialization when the shared chip 20 is used in the bus bridge circuit 17.

The board bus interface 28 interfaces the board bus 16 with a processor element circuit constituted by the shared chip 20.

The processor element internal bus (hereinafter referred to as P
The E bus 30 is a 32-bit bus for connecting the board bus interface 28, the CPU 21, the FPU 22, and the internal memory 23.

A local memory internal bus (hereinafter abbreviated as LM bus) 31 is provided with an external local memory and a CPU.
21 is a 64-bit bus for connecting to the FPU 22.

The instruction bus 32 stores the program in the CPU 21.
This is a 32-bit bus for reading the data. The floating-point data bus 33 is connected to the FPU 22 by the internal memory 23.
This is a bus for exchanging double-precision floating-point data stored in.

The input terminal 34 of the mode selection signal SEL is
A selection input terminal for selecting whether to use the shared chip 20 as a processor element or a bus bridge circuit.

The interrupt signal line 35 is a line for supplying an interrupt signal from the board bus interface 28 to the CPU 21.

Further, if the mode selection signal SEL is "0", the shared chip 20 is used as a processor element, and if "1", it is used as a bus bridge circuit. Here, in the circuit constituted by the shared chip 20, when the mode selection signal SEL is "0" and is used as a processor element, the operation processing mode is set. Time is called bridge mode.

[Configuration, Function, and Operation as Processor Element] [Configuration as Processor Element] Next, a configuration when the shared chip 20 is operated as the processor element 14 will be described.

As described above, FIG.
Is used as the processor element 14, and the value of the mode selection signal SEL supplied to the input terminal 34 is "0". For this reason, the common chip 20 enters the arithmetic processing mode and is used as a processor element.

When the shared chip 20 is in the arithmetic processing mode, the multiplexer 26 selects the output of the internal memory 23, and the instruction stored in the internal memory 23 is read out to the instruction bus 32.

At this time, as shown in FIG. 1, the board bus interface 28 is connected to the board bus 16 and the LM bus 31 and the LMC 24 are connected to the local memory 15.
Connect to For example, a general-purpose S
Using a RAM, the LM bus 31 is connected to the data terminal and the address terminal of the SRAM, and the LMC 24
It generates control signals such as an SRAM chip select signal and a write enable signal. Since the LM bus 31 is 64 bits as described above, the local memory 15
For example, four SRAMs having a data width of 16 bits are connected in parallel.

When the shared chip 20 is in the arithmetic processing mode, the peripheral circuit controller 25 and the load generator 27 do not function.

Next, functions of the CPU 21 and the board bus interface 28 in the arithmetic processing mode among the internal units of the shared chip 20 will be described. First,
The function of the CPU 21 will be described.

The CPU 21 is a normal RISC processor, and internally includes a 32-bit integer register as described above. In addition to the integer registers, it includes a control register for controlling an internal unit and an external unit of the CPU 21. The CPU 21 is in a startup waiting state (standby state) immediately after a reset or the like, and does not operate until the board bus interface 28 starts up, as described later. Hereinafter, the description will be continued assuming that the CPU 21 has been activated.

From the board bus interface 28 to the CPU
When the memory 21 is activated, the state is changed to an operation state, and the internal memory 2 is previously transferred from a specific address through the instruction bus 32.
The reading of the instruction stored in No. 3 is started. Thereafter, the instructions are sequentially read out one by one from the internal memory 23 while the address is incremented, and the instructions are interpreted and executed.

The instructions of the CPU 21 are constituted by an instruction set of a general RISC-type general-purpose CPU, and include at least a NOP instruction that performs no operation, an arithmetic and logic operation instruction between a 32-bit integer register and a control register, A shift operation instruction, a load / store instruction between the internal memory 23 and the 32-bit integer register inside the CPU 21 via the PE bus 30, a load / store instruction between the LM12 and the 32-bit integer register via the LMBUS,
Also, the local memory 15 and the FP through the LM bus 31
Load and store instructions between floating point registers inside U22, load and store instructions between internal memory 23 and floating point registers inside FPU 22, jump and branch instructions, floating point arithmetic unit inside FPU 22 , A floating-point operation instruction for performing a floating-point operation between floating-point registers inside the FPU 22, and an integer register inside the CPU 21 and a floating-point inside the FPU 22 using a bus (not shown) between the CPU 21 and the FPU 22. It has a data transfer instruction between registers.

Of these instructions, the local memory 15
When a load, store instruction, floating-point operation instruction, or data transfer instruction between the CPU 21 and the internal memory 23 and the floating-point register inside the FPU 22 is read by the CPU 21,
The CPU 21 controls the FPU through a control signal (not shown).
These instructions are executed while controlling a floating-point register and a floating-point arithmetic unit inside 22.

Further, the CPU 21 stores the local memory 15
And a floating point register or CPU inside the FPU 22
When executing a load / store instruction to / from an integer register in the internal memory 21, the CPU 21
Is output to the local memory 15 via the LM bus 31 and the LM controller 24
To generate a chip select signal, a write signal, and the like for the local memory 15 and output the signal to the local memory 15. In the case of loading between the local memory 15 and the integer register inside the CPU 21, the data is read through the 64-bit LM bus 31.

At this time, according to the setting of the control register, the 32-bit integer register in the CPU 21 stores
The upper 32 bits of the LM bus 31 are read or the lower 32 bits are read.
Whether to read the bit is selected. Further, since the store from the integer register to the local memory 15 is also performed through the 64-bit LM bus 31, the upper 32 bits of the local memory 15 are set according to the setting of the control register.
Whether to write to bits or to write to lower 32 bits is selected.

Further, the CPU 21 has a function of processing an interrupt, and when interrupted from outside of the board bus interface 28 or the processor element circuit or from the FPU 22 through the interrupt signal line 35 or the like, the CPU 21 executes the work which has been executed so far. Interrupt, save the address of the interrupted instruction in an integer register, and jump to the interrupt handler. When the execution of the interrupt handler is completed, the process returns to the address stored in the specific integer register and resumes the original work.

Next, an outline of the function and configuration of the board bus interface 28 will be described.

The board bus interface 28 interfaces between the board bus 16 operating according to the above-described PPRAM-Link protocol and the inside of the shared chip 20. Therefore, the board bus interface 2
8 indicates access to the internal memory 23 or the PPR described above.
A packet corresponding to the AM-Link subaction is generated. This board bus interface 28
Has six functions described in the following (A) to (F).

(A) Another PP via the board bus 16
In response to a write request from the RAM node to the internal memory 23, data sent from the outside is transferred to the PE bus 30.
Is written to the internal memory 23 in units of 32 bits.

(B) Another PP via the board bus 16
In response to a write request from the RAM node to the local memory 15, data sent from the outside is written to the local memory 15 via the LM bus 31 in 64-bit units.

(C) Another PP via the board bus 16
In response to a read request from the RAM node to the internal memory 23, the internal memory 23
Data is read in units of 2 bits and output to the board bus 16.

(D) Another PP via the board bus 16
In response to a read request of the local memory 15 from the RAM node, the local memory 1
Data is read in units of 5 to 64 bits and output to the board bus 16.

(E) In response to a write request from the CPU 21 to another PPRAM node, a request is output to the board bus 16, and data stored in the internal memory 23 is read out via the PE bus 30. 16 is output.

(F) In accordance with a data read request from the CPU 21 to another PPRAM node, a request is output to the board bus 16 and data input from the board bus 16 is transferred to the internal memory via the PE bus 30. Write to 23.

In order to realize these functions, the board bus interface 28 has a function of accessing the internal memory 23 and the local memory 15 as well as the functions (A) to (3) described above.
In correspondence with the operation of (F), a function for generating a sub-action of PPRAM-Link and a function for operating in cooperation with the CPU 21 constituting the transaction shown in FIG.

Next, the outline of the configuration of the board bus interface 28 will be described. The configuration of the unit of the board bus interface 28 has already been disclosed in the above-mentioned document by Hashimoto et al. Therefore, here, an example of the board bus interface 28 that has been slightly modified based on this configuration based on this embodiment will be described.

FIG. 6 shows a modified board bus interface 28 based on the configuration of Hashimoto et al.
FIG. 3 is a block diagram showing an example of the configuration. In FIG. 6, broken lines represent main control signals between blocks.

In the board bus interface 28, the packet inputted from the input terminal InputLink is judged by the address decoder 40 whether the packet is addressed to this node. As a result of this determination, if the packet is addressed to the own node, the packet is put into the input queue 43. If the packet is not addressed to the own node, the packet is sent to the adjacent node through the output terminal OutputLink. Can be put in.

When the input packet is a request transmission packet or a response transmission packet among the packets described with reference to FIG. 5, the request reception packet and the response reception packet are always returned by the above-described sub-action operation. Therefore, the reception packet generator 44 is controlled from the address decoder 40 to generate these reception packets. Furthermore, when a request transmission packet or a response transmission packet is generated inside the processor element, the transmission queue is accumulated in the output queue 45.

The outputs of the bypass FIFO 41, the reception packet generator 44, and the output queue 45 are connected to the flow controller 42, respectively. The flow controller 42 selects one packet from these, and outputs it from the output terminal OutputLink. The detailed operation of the flow controller 42 is described in the above-mentioned document and will not be described.

Further, the interruption control block 46
When packet generation is performed by U21, the CPU
21 is a block for generating an interrupt signal Intr to be output to the CPU 21.

The memory access block 47 is a block for writing / reading data to / from the local memory 15 and the internal memory 23 according to a request from the outside.

Further, the control status register 48 comprises two registers, a control register 48a and a status register 48b. The control register 48a controls the internal blocks of the board bus interface 28 according to the stored data content. This control register 48a
Since data can be written from the CPU 21 through the PE bus 30, the board bus interface 28 is controlled by the CPU through the control register 48a. The state register 48 b is a register for transmitting the internal state of the board bus interface 28 to the CPU 21, and can be read out to the CPU 21 through the PE bus 30.

When the transactions (A) to (F) are executed using this configuration, the following is performed.

First, the operation of a transaction in accordance with an external write request as described in (A) and (B) will be described. In this case, first, data to be written together with the header of the request transmission packet is input to the input queue 43. Therefore, as described above, the reception packet is generated by the reception packet generator 44, and the memory access block 47 is transmitted from the input queue 43 to the input queue 43. Start up,
Write data to the target memory. After writing the data, the interrupt block 46 is activated and the CPU
An interrupt is generated at 21.

When the CPU 21 receives the interrupt, it jumps to the interrupt handler and generates the header information of the response transmission packet in the internal memory 23. As described above, since there are several types of packets generated by the CPU when an interrupt is received, the board bus interface 28 holds information indicating that an external write request has been received in the status register 48b. The CPU 21 determines the type of the header of the packet to be generated by reading the status register 48b through the PE bus 30.

Thereafter, the CPU 21 writes the data in the control register 48a through the PE bus 30, and instructs the board bus interface 28 to output a response packet.
Then, the board bus interface 28 reads the header of the response transmission packet through the memory access block 47 and stores it in the output queue 45, thereby outputting the response transmission packet to the board bus 16.

In consideration of the fact that the response acknowledgment packet output by the target node cannot be received for various reasons, the response queue is sent to the output queue 45 until the response acknowledgment packet is returned to the input queue 43. The outgoing packet shall be retained. If the response acknowledgment packet does not return even after a certain period of time, the output queue 45
Outputs the response transmission packet again.

Next, the operation of a transaction according to a read request from the outside as described in (C) and (D) will be described. In this case, since only the header of the request transmission packet is stored in the input queue 43, the reception packet is generated by the reception packet generator 44 as described above. Interrupts the CPU 21.

Then, the CPU 21 generates a header of a response packet to the read request in the internal memory 23 based on the information of the status register 48b, as in the previous case. Thereafter, the CPU 21 instructs the output of a response packet to the read request by writing to the control register 48a.

Then, the board bus interface 28
Reads the header of the response transmission packet through the memory access block 47, and furthermore, the memory access block 47 reads the local memory 15 or the internal memory 23
Read the data from the requested address at
It is stored in the output queue 45. Then, (A),
As in the case of (B), a response packet is output from the output queue 45.

Next, the state of a transaction when the CPU 21 issues a write request to another node as described in (E) will be described. In this case,
The CPU 21 stores the header of the write request packet and the data to be written at a specific address in the internal memory 23, and writes the data to the control register 48a to the board bus interface 28 so as to output the write request. To instruct.

Then, the board bus interface 28
Reads out the header and data of the request transmission packet from the specific address in the internal memory 23 through the memory access block 47 and stores them in the output queue 45. Thereafter, a request transmission packet is output from the output queue 45 as in the case of a response transmission packet.

At this time, if a reception packet for the request transmission packet does not return even after a certain period of time has elapsed after the transmission of the request transmission packet, the above-mentioned (A) and (B) are used to retransmit the request transmission packet. As in the case of waiting for a reception packet for a response transmission packet described in the case of (1), the packet is held in the output queue 45 and the reception packet is waited until the reception packet is returned.

Further, taking into consideration a case where a response subaction to the request subaction issued by the CPU 21 is not returned, the interrupt block 46 sets the input queue 43 even if a certain time has elapsed after outputting the request subaction.
If no response transmission packet is returned to the
Give an interrupt to

When the CPU 21 receives this interrupt, it jumps to the interrupt handler and retransmits the previously transmitted request transmission packet. At this time, the CPU 21 determines, based on the information from the status register 48b, that the retransmission operation is to be performed.

When a response sub-action to the output request sub-action is returned and a response transmission packet is stored in the input queue 43, a reception packet is generated by the reception packet generator 44 and interrupted as described above. The timer of the block 46 is cleared so that an interrupt for retransmission is not issued to the CPU 21.

The status register 48b contains the CPU 2
Since a flag indicating that the transaction generated by 1 has been completed is held, this flag is set after receiving the response transmission packet. CP
U21 can wait for this flag to be set and move on to the next operation.

Finally, as shown in (F), the CPU 21
The state of a transaction when a read request is issued to another node from is described. In this case, first, the CPU 21 writes only the header of the read out transmission packet into the internal memory 23, and instructs the board bus interface 28 to output the packet through the control register 48 as described above. Thereafter, the header of the packet read from the internal memory is stored in the output queue 45 by the memory access block 47, and the request transmission packet is output.

After that, when the request reception packet and the response transmission packet are returned, the memory access block 47
The data included in the response transmission packet is stored in the internal memory 23.
Write to a specific location in. Thereafter, as in the case of (E), a flag indicating that the transaction has been completed is set. The CPU 21 can access the data written in the internal memory 23 after confirming that this flag is set.

Further, the operation in the case where the request reception packet and the response transmission packet for the request transmission packet are not returned is the same as the case of the above (E).

Here, in the case of the above (E) or (F), a certain processor element 1 on the board 12
4, the other processor element 14 or the bus bridge circuit 17 is connected to the board bus 1 of the PPRAM-Link.
6 so that it can be recognized as a PPRAM node,
It is possible to send such a write / read request.

However, since the memory on the host computer 11 is outside the PPRAM-Link, it cannot be recognized from the processor element 14 on the board 12. For example, even if a certain processor element 14 attempts to write to a specific address in a memory on the host computer 11, the host computer 11
Since no node identifier or offset address of the PRAM-Link is assigned, writing cannot be performed.

Therefore, in this embodiment, the PPRAM
-This problem is solved by using a link write request.

When a certain processor element 14 wants to access the memory on the host computer 11, the bus bridge circuit 17 supplies a PPRAM-Lin
Send a write request for k. At this time, in the write data included in the request transmission packet, the memory address of the host computer 11, the type of transaction, the data to be written, and the like are put in advance.

When the bus bridge circuit 17 receives this packet, it accesses the host computer 11 in accordance with the sent contents. Details of this access will be described later.

Next, a method of starting from the board bus interface 28 to the CPU 21 will be described. This activation is performed by writing to an internal register of the CPU 21 through the PE bus 30.

The CPU 21 may be activated by automatically writing data from the board bus interface 28 after waiting for a specific time after resetting, or from the host computer 11 to the system bus 13 or the board bus 1.
6 via the board bus interface 28. In the case of the latter activation method, as described above, since the CPU 21 must generate a response transmission packet, it is necessary to completely interrupt the CPU 21 after the activation of the CPU 21 before interrupting. Alternatively, since a transaction called an active message that does not return a response transmission packet is prepared in the PPRAM-Link, this active message may be used.

[Operation as Processor Element 14] The operation of the processor element 14 when the molecular orbital-only system operates according to the above-described calculation procedure will be described.

Here, first, when viewed from the system bus 13, the internal memory of the host computer 11, the internal memory 23 of each processor element 14, and the local memory 15 attached to the processor element 14 are the system bus. Since it is mapped in the address space of the IEEE 1394 serial bus, it can be accessed using the assigned address.

Further, when viewed from the board bus 16 on the board 12, as described above, a node identifier is assigned to each processor element 14, and
An offset address is allocated to the internal memory 23 of the processor element 14 and the attached local memory 12.
The internal memory 23 and the local memory 15 can be accessed using the node identifier and the offset address through the AM-Link.

First, after the system is started, each internal unit of the processor element 14 is reset through a reset terminal (not shown).

The board bus interface 28 automatically initializes immediately after resetting, and becomes ready to operate according to the interface function described later. Also, CP
As described above, the U21 is in a start-up waiting state (standby state) in which it is not operated by being reset as described above.

As described above, after starting the system,
A write request is transferred from the host computer 11 via the system bus 13 → the bus bridge circuit 17 → the board bus 16, and molecular information, base information, other parameters, and a program are transferred to the processor element 14.

At this time, using the functions (A) and (B) of the board bus interface 28 described above, molecular information and
The base information and other parameter information are written in the local memory 15, and the program is stored in the internal memory 2.
3 is written. Thereafter, when the processor element 14 is activated, the host computer 11 activates the CPU 21 as described above. As a result, the CPU 21 transitions from the start waiting state to the operating state.

When the CPU 21 transitions to the operation state, the CP
U21 executes an instruction from a specific address of the internal memory 23. Here, it is assumed that the above-described program is loaded from an address at which the CPU 21 starts operating.
Therefore, the CPU 21 starts executing the program written in the internal memory 23 by the host computer 11 in advance. Further, as described above, by setting the CPU 21 in the standby state after the reset, the contents of the internal memory 23 before the program is written can be executed, and the runaway of the CPU 21 can be prevented.

Next, the CPU 21 causes the host computer 11 to execute, for example, a loop composed only of NOP instructions until the two-electron integral information and the density matrix element assigned to the processor element 14 are written. wait. Thereafter, the host computer 11 communicates with the system bus 13, the bus bridge circuit 17,
The information write request is transferred through the board bus 16 and written to the local memory 15 by the function (B) of the board bus interface 28 described above.

When the CPU 21 detects that the writing of the necessary information has been completed, it exits the waiting state by executing the loop, executes the two-electron integration and the calculation of grs, and stores the calculation result of grs in the local memory 15. Store. Write detection method (host computer 11 and C
Synchronization with the PU 21) and further details of this calculation will be described later.

Thereafter, as described above, the processor element 14 sends the calculation end information to the host computer 11 as follows.

First, the host computer 11 provides a specific variable area corresponding to each processor element 14 in its internal memory or the like for the calculation end information. This variable is called a calculation end bit. The calculation end bit corresponding to each processor element 14 is, as described above, because the internal memory of the host computer 11 is mapped in the address space of the system bus 13
It can be accessed from all processor elements 14.

When the system is started, this calculation end bit is set to, for example, “0”, and the host computer 11
Monitors this calculation end bit, and if it is "1", determines that the calculation by the corresponding processor element 14 has been completed and performs a necessary operation.

The CPU 21 uses the above-described writing method to the memory on the host computer 11 to execute the board bus 16, bus bridge circuit 17, system bus 1
Then, by writing "1" to the calculation end bit of the internal memory of the host computer 11 via "3", the calculation end information is transferred.

When the calculation end information is transmitted in this manner, the host computer 11 sends the information to the local memory 1 connected to the processor element for which the calculation has been completed.
By sending a read request to the device 5, the value of grs stored here is read using the function (D) of the board bus interface 28.

Thereafter, the calculation end bit of the processor element 14 is cleared to “0” again, and the two-electron integration information and the density matrix corresponding to the next calculation performed by the processor element 14 are described above. And send it in the same way. Hereinafter, the same procedure is repeated.

Next, the contents of the two-electron integration and the calculation of grs, and how to establish synchronization between the host computer 11 and the processor element 14 will be described.

[Outline of 2-electron integration and grs calculation]
First, an outline of two-electron integration and calculation of grs will be described.

As described above, the two-electron integral represented by the above equation (4) is reduced to a calculation procedure using a floating-point multiply-accumulate operation by a calculation using the Ohara method or the like. Therefore, in the program sent to the processor element 14 after the system is started, the calculation procedure of the two-electron integration using the floating-point operation instruction by the floating-point operation unit of the FPU 22 is included in, for example, a subroutine, and the calculation is performed When doing this, call this subroutine.

Further, as shown in the above-mentioned literature relating to Ohara's method, the parameters necessary for the calculation of the two-electron integral include the coordinates of the atoms involved in the calculation, the types of atoms, and the basis set used. An orbital index determined accordingly, and an orbital quantum vector related to the type of orbital, a coefficient used for superposition of two-electron integration, and the like. These parameters may be included in the two-electron integration information sent from the host computer, or if the molecule and the basis set to be used are determined, these parameters are also determined. Sent to the local memory 15 attached to the processor element 14,
As the electronic integration information, an index indicating these parameters may be sent.

The orbital quantum vector described here is
It is divided into a plurality of types, and corresponds to each of the four atomic orbitals as represented by equation (4). For this reason,
There are a plurality of two-electron integrals, and the calculation procedure of the two-electron integral using the floating-point operation instruction exists only for this type.
Therefore, the above method requires a plurality of subroutines. Therefore, these subroutines are not stored in the internal memory 23 having a limited capacity, for example.
The information may be stored in the local memory 15.

At this time, since the calculation of the two-electron integral includes a part represented by a sequence of floating-point operations without control instructions such as branching, this part is stored in the local memory 15.
Further, the floating point arithmetic unit of the FPU 22 includes
It is also possible to provide a mode in which the calculation procedure is read out from the local memory 15 without receiving the control described above, and the calculation is performed in this mode.

After the two-electron integral is calculated as described above, the processor element 14 calculates grs according to the above equation (2). For this calculation, the density matrix information sent together with the two-electron integration information from the host computer 1 is used. At this time, the calculation is performed according to a certain procedure regardless of the type of the two-electron integration,
This procedure may be included in the program stored in the internal memory 23, and after the two-electron integration is obtained, grs may be obtained by executing a floating-point operation according to this procedure.

Some of the density matrix information sent from the host computer 11 is commonly used between the processor elements 14 on the board 12.
Therefore, these density matrices are stored in the host computer 1
It is also possible to send the data between the processor elements 14 through only the high-speed board bus 13 instead of sending the data from 1.

[Synchronization of host and processor element]
Next, how to transfer the two-electron integral information and the density matrix information by the host computer 11 and how to synchronize the above calculations in the processor element 14 will be described.

If synchronization is not established between them, the CPU 21 starts the calculation before the two-electron integral information and the density matrix used for the calculation are written into the local memory 15. Alternatively, the host computer 11 overwrites the two-electron integral information and the density matrix even though the calculation by the CPU 21 is not completed. As a result of these,
The obtained value of grs is incorrect.

To avoid such a situation, for example,
A variable area called a tag bit is provided at a specific internal memory 23 or local memory 15 address. This tag bit can be written from both the host computer 11 and the CPU 21. While the tag bit is "0", the CPU 21 cannot start the two-electron integration and the calculation of grs, and cannot exit the above loop until the tag bit becomes "1". Also, the tag bit is “1”
In the meantime, the host computer 11 performs two-electron integration information,
And the density matrix element cannot be written, and waits until the tag bit becomes “0”.

Under such a premise, the tag bit is set to "0" when the system is started. Then, first,
As described above, the CPU 21 repeats the loop until the host computer 11 writes the two-electron integral information and the density matrix element. After writing the information, the host computer 11 sets the tag bit to “1”. Then, since the tag bit becomes “1”, the CPU 21 exits the loop and starts the two-electron integration and the calculation of grs. Further, the CPU 21
When the calculation of s ends, the CPU 21 sets the tag bit to “0”.

During this time, even if the host computer 11 tries to write the next two-electron integral information or density matrix information, as described above, the host computer 11 is in the waiting state, It does not overwrite information. Thereafter, when the tag bit becomes “0” by the CPU 21, the host computer 11
The next two-electron integral information and density matrix information are written.

By doing so, the host computer 11 and the processor element 14 can be synchronized using the tag bits. Therefore, the CPU 2
It is possible to avoid the calculation of two-electron integration and grs by using the two-electron integration information and density matrix before writing or the two-electron integration information and density matrix after being overwritten.

To increase the efficiency, grs is stored in the memory of the host computer 11 and is stored in the local memory 15 for writing two-electron integrals and density matrix elements. Of the local memory 15 and two tag bits, and the above-described writing, inspection, and reading may be performed alternately. In this way, the host computer 11 can write the two-electron integral information and the density matrix information while the processor element 14 is performing the calculation, for example, so that the calculation efficiency is improved.

[Configuration and Function as Bus Bridge Circuit,
Operation] [Configuration as Bridge Circuit] Next, the shared chip 20
Will be described as a part of the bus bridge circuit 17. FIG. 3 shows the bus bridge circuit 17.
FIG. 3 is a block diagram showing the configuration of the shared chip 20;
It is configured using some additional circuits. At this time, FIG.
As shown in (1), the mode selection signal SEL input to the input terminal 35 of the shared chip 20 is "1", and the shared chip 20 operates in the bridge mode.

Circuits added to the shared chip 20 include a ROM 36 for storing a program used by the CPU 21 of the shared chip 20 in the bridge mode, an IEEE 36
Link layer controller of 1394 serial bus
LLC) 37 and an IEEE 1394 serial bus physical layer controller (hereinafter abbreviated as PHY)
38 are provided. Then, an external interrupt line 39 is provided from the LLC 37 to the shared chip 20. Since an interrupt from the external interrupt line 39 is input to the CPU 21 via a signal line (not shown), the interrupt handler is activated by the external interrupt as described above.

Here, the LLC 37 and the PHY 38 will be briefly described. LLC37 and PHY38 are IE
This circuit has a function based on the specifications of the link layer and the physical layer according to the EE1394-1995 standard.

Among them, LLC3 having a link layer function
7 may be a general-purpose bus such as a PCI bus, for example. Here, a chip select signal and a write pulse signal or a request A general-purpose interface that controls access using signals and acknowledge signals.

At present, LLC 37 and PHY 38 having such a general-purpose interface function are available from several companies.
Examples of LLC include TSB12LV31 manufactured by Texas Instruments and NN8A213 manufactured by Nippon Steel Corporation. Examples of PHY include TSB21LV03 manufactured by Texas Instruments and NN8A202 manufactured by Nippon Steel Corporation. is there.

The interface between the shared chip 20 and the LLC 37 will be further described. The above-mentioned LLC has internal registers, and is interfaced from the shared chip 20 by write / read access to these registers. Therefore, from the shared chip 20, in addition to the control signal described above, an SRA using an address signal of several bits and a data signal of, for example, 16 bits is used.
It can be interfaced in the same way as M.

In this embodiment, the control signal of the LLC 37 is generated by the PEC 25. As the address signal of the LLC 37, several lower bits of the address signal output from the LM bus 31 used for the address of the local memory 15 in the arithmetic processing mode are input. Here, the data signal is 16 bits, and this data signal includes, for example, the upper 16 bits of the 64-bit data signal connected to the LM bus 31 used for data input / output of the local memory 15 in the arithmetic processing mode. Use bits.

Further, the LLC 37 is connected to the PHY 38 by a specific interface. In the PHY 38, processing of the physical layer such as control of a transmission line is performed, and communication is performed through the ports 1 and 2 shown in FIG. Port 1 and port 2 are, as shown in FIG.
It is connected to the system bus 13 and connected between the boards 12 or the host computer 11 in the form of a daisy chain.
Are connected to each other.

The shared chip 20 is connected to, for example, the ROM 36 having a data bus width of 16 bits, in addition to the LLC 37. In this embodiment, a control signal such as a chip select signal of the ROM 36 is generated by the LMC 24 in the same manner as in the arithmetic processing mode, and the address signal is L.
The address signal is output from the M bus 31. Further, assuming that the data signal is 16 bits, for this data signal, for example, the lower 16 bits of a 64-bit data signal input / output to / from the LM bus 31 are connected.

[Function and Operation of Bus Bridge Circuit 17] Next, the function and operation of the bus bridge circuit 17 will be described.

[Functions of Bridge Circuit] First, functions when the shared chip 20 is in the bridge mode will be described focusing on differences from the arithmetic processing mode. In this bridge mode, the operation after reset at system startup and C
The operation of the PU 21 is different from the operation processing mode.

First, after a reset at the time of system startup, the CPU 21 is in a startup waiting state in the arithmetic processing mode, whereas in the bridge mode, it is first in the boot state to automatically execute a program stored in the ROM 36. And then automatically shifts to the operating state.

Thus, before the IEEE 1394 serial bus as the system bus 13 and the PPRAM-Link as the board bus 16 start up, the program can be loaded and the operation can be started without using the communication function. .

[0203] In the boot state, the multiplexer 26 selects the output of the load generator 27 and supplies it to the CPU 21 through the instruction bus 32 instead of the instruction stored in the internal memory 23.

The load generator 27 has a ROM 36
Through the LM bus 31 to the instruction stored in
Loads an integer register inside the CPU 21 for each bit,
An operation of forming a 32-bit instruction by putting together two load results and storing the result in the internal memory 23 is repeated a predetermined number of times while increasing the addresses of the ROM 36 and the internal memory 23. " Is automatically generated.

Further, at this time, the CPU 21 executes the command substantially in the same manner as the above-described operation state. As a result,
When the CPU 21 is in the boot state, the load generator 27
The instructions stored in the ROM 36 are all stored in the internal memory 23 in order to execute the instruction generated in the step S1.

However, in general, the access time of the ROM 36 is often slower than the access time of the local memory constituted by the SRAM. Therefore, the execution of the load instruction from the ROM 36 in the boot state is performed in the operation state in the operation processing mode. Takes longer to execute than load instructions.

As described above, when loading an integer register inside the CPU 21 through the LM bus 31, which part of the 64-bit LM bus 31 is loaded is determined by the setting of the control register of the CPU 21. Therefore, the load instruction causes the LM bus 31
CPU 21 so that it is loaded from the lower 32 bits of
The value immediately after resetting of the control register is set.

When the instructions in the ROM 36 have been transferred to the internal memory 23 in the boot state, as described above, the CPU
21 automatically shifts to the operating state and starts executing the instruction. In this state, the multiplexer 26 is switched to select an instruction output from the internal memory 23 as in the arithmetic processing mode. At the same time, the CPU 21
In the boot state, instructions are read out and executed sequentially from the address of the internal memory 23 where the program is stored.

Here, the operation of the load / store instruction from the external circuit in the operation state is different between the arithmetic processing mode and the bridge mode. In the arithmetic processing mode, reading / writing is performed to / from the local memory 15 configured by a general-purpose SRAM, whereas in the bridge mode, reading / writing is performed through the interface of the LLC 37 described above.

Therefore, in bridge mode, PEC2
5, while generating a control signal for the LLC 37, based on the above-described general-purpose interface specifications, the LLC 37
The reading and writing of the internal register included in the. In addition, since there is a difference in the access time between the SRAM and the LLC 37, the CPU 21 executes load and store with the LLC 37 by using a different number of cycles from that in the arithmetic processing mode.

At this time, the lower 16 bits of the LM bus 31
Writing from a bit is prohibited by setting the control register of the CPU 21. Therefore, even when a store command is issued, writing to the ROM 36 is not performed, and the output of the ROM 36 does not collide with the data output. .

Other units, such as the board bus interface 28, other than the above-described units, operate in the bridge mode.
It has the same function as the arithmetic processing mode.

[Outline of Operation of LLC 37] Next, an outline of an operation when communication is performed from the shared chip 20 via the system bus 13 composed of an IEEE 1394 serial bus using the LLC 37 will be described.

In the specification of the IEEE 1394 serial bus, asynchronous asynchronous transfer and isochronous transfer for performing real-time transfer, which is faster than asynchronous transfer, are defined. It is assumed that asynchronous transfer of the bus standard is used. At this time, LLC3
In general, the following can be considered as the communication control procedure by 7.

First, it is assumed that the LLC 37 includes a transmit FIFO, a receive FIFO, a control register, and a status register. FI for transmission
The FO is used when transmitting an asynchronous transfer packet from the shared chip 20 to the system bus 13 which is an IEEE 1394 serial bus, and writing is performed from the shared chip 20 according to the above-described general-purpose interface. The control register is used to control this transmission, and similarly, writing is performed from the shared chip 20.

The receive FIFO is used when receiving asynchronous transfer packets from the IEEE 1394 serial bus, which is a system bus, and is read from the shared chip 20 in accordance with the above-described general-purpose interface. An interrupt signal line 39 from the LLC 37 to the CPU 21 is also used.

At this time, the status register is used for transmitting the interrupt status and the like to the shared chip 20, and is read from the shared chip 20 according to the general-purpose interface. The LLCs announced by the companies mentioned above use various communication control procedures, but the general procedures described here can be handled with only slight changes, so The description will be made based on this procedure.

In the IEEE 1394 asynchronous transfer, when a write transaction and a read transaction are performed from one node to another node, the request packet transmission and response are performed in the same manner as the PPRAM-Link request packet transmission described above. A transaction is configured by receiving a packet.

In other words, the requesting node sends out an asynchronous write request packet or read request packet. Thereafter, the node that has received the request returns an asynchronous write response packet or read response packet to the requesting node. Also, PP
As in the case of the RAM-Link, in the case of writing, data is added to a write request packet, and in the case of reading, data is added to a read response packet.

In the link layer of the IEEE 1394 serial bus standard, the processing at the packet level is performed as described above. Therefore, the processing at the transaction level such as the processing of the asynchronous request packet and the response packet needs to be performed by the program of the shared chip 20. There is.

Here, the shared chip 20 to the IEEE 13
When transmitting an asynchronous request packet or response packet through the 94 serial bus, first, these packets are written into the above-mentioned transmit FIFO through the CPU 21 in the shared chip 20, and then a specific value is stored in the control register. To instruct transmission of the packet. Then, the packet stored in the transmission FIFO is automatically transmitted to IEEE 1394 by the LLC 37.

When an asynchronous request packet or response packet is received from the IEEE 1394 serial bus, this packet is stored in the receive FIFO of the LLC 37, and is sent from the LLC 37 to the shared chip 20 through the external interrupt signal line 39 described above.
Is interrupted. Therefore, C in shared chip 20
The PU 21 activates an interrupt handler and reads a packet from the receive FIFO described above. Also, by reading the data of the status register, the CPU 2
1 can obtain information such as the type of packet when an interrupt occurs.

[Operation as Bus Bridge Circuit]
The manner in which the bus bridge circuit 17 operates with the functions described above will be described. As described above, the CPU 2 in the shared chip 20 after being initialized by the system.
1 operates according to a program read from the ROM 36 to the internal memory 23. In connection with the operation of the system described above or the operation of the processor element 14, the bus bridge circuit 17 needs to perform the following three operations based on this program.

(G) Processing of a request from the host computer 11 to each processor element 14 for writing a parameter or a program to the internal memory 23 or the local memory 15.

(H) From each processor element 14,
Processing of a write request to the calculation end bit of the host computer 11.

(I) Processing of a read request for grs data from the local memory 15 attached to each processor element 14 from the host computer 11.

The contents of these operations will be described below.

First, the CPU 21 of the bus bridge circuit 17
Is normally the LLC request transmission packet of the IEEE 1394 bus standard issued by itself.
A loop for monitoring the elapsed time is executed for those for which no response packet has been returned through 37. CP
The reason why U21 normally performs this operation will be described later. In addition, since the operations of the CPUs (G) to (I) are started by an interrupt as described below, most of the operations are performed by an interrupt handler.

In the case of the operation (G), the bus bridge circuit 17 receives write data from the host computer 11,
, A write transaction of PPRAM-Link is performed.

At this time, as described above, the asynchronous write request packet from the host computer 11 is stored in the receive FIFO of the LLC 37 and an interrupt is generated through the external interrupt signal line 39. The CPU 21 of the shared chip 20 jumps to an interrupt handler for processing an external interrupt.

In this interrupt handler, the CPU 21
First reads the status register of the LLC 37 and confirms that a write request has been received, reads the header of the write request packet and the added write data from the receive FIFO, and reads the internal memory 2
Write to 3.

After that, the CPU 21 converts the address contained in the header information of the write request packet into the PPRAM node identifier and the memory address offset of the processor element 14 into which the data is to be written. Further, a header of a write request packet of the PPRAM-Link is generated based on these pieces of information, and stored in a predetermined position of the internal memory 23 together with the data.

Thereafter, by performing exactly the same operation as in (E) described in the description of the function of the processor element 14, the data stored at a predetermined position in the internal memory 23 is transferred to the corresponding processor element 14. Write to the internal memory 23. At the same time, the bus bridge circuit 17
Sends a write response packet to the asynchronous write request packet to the system bus 13 which is an IEEE 1394 serial bus. In this operation, first, a write response packet is generated in the internal memory 23 by the CPU 21, and the generated write response packet is stored in the LLC 37 as described above.
By writing to the transmit FIFO and control register.

The processing contents of the operation (I) are the same as the processing contents of the above (G). Bus bridge circuit 1
When receiving a read request from the host computer 11, the processor element 1 to be read is
4, a read transaction of the PPRAM-Link is generated to receive the data, and thereafter, the data is transmitted to the host computer 11 by a response packet.

At this time, the asynchronous read request packet from the host computer 11 is transmitted to the LLC 37
Is stored in the receiving FIFO and an interrupt is generated through the external interrupt signal line 39, so that the CPU 21 of the shared chip 20 of the bus bridge circuit 17 jumps to an interrupt handler for processing the external interrupt.

Then, in the interrupt handler, LL
When it is determined that a read request has been received by reading the status register of C37, this read request packet is read from the receive FIFO and written to the internal memory 23. Thereafter, the CPU 21 converts the address included in the header information of the read request packet into a PPRAM node identifier and a memory address offset of the processor element from which data is read.

Further, based on these information, the PPR
The header of the read request packet of the AM-Link is generated and stored in a predetermined position of the internal memory 23. Thereafter, by performing exactly the same operation as in (F) described in the description of the function of the processor element, data is read from the memory of the corresponding processor element 14 and the internal memory of the shared chip 20 of the bus bridge circuit 17 is read. 23, the read data is written.

At the same time, the shared chip 20 of the bus bridge circuit 17 sends out a read response packet to the asynchronous read request packet to the system bus 13 composed of the IEEE 1394 bus. At this time, since data is added to the read response packet, first, a header of the read response packet is generated by the CPU 21, and the header and the read data stored in the internal memory 23 are transferred to the LLC 37.
Then, a read response packet is sent out by writing to the transmission FIFO of the above and then writing to the control register as described above.

In the operation (H), (G)
Unlike the operation of (I), the bus bridge circuit 17
An asynchronous write transaction to the EEE1394 serial bus must be performed.

In addition, as described above, in this operation, a certain processor element 14 sends a signal from the host computer 11 to the host computer 11.
Of the internal memory 2 of the bus bridge circuit 17 from the processor element 14.
3, a special format data is written using a PPRAM-Link write request. The data in the special format includes information such as performing a write operation on the host computer 11, a memory address on the host computer 11 for performing the write, and write data for the address. Therefore, when a write request is received from the processor element 14, the bus bridge circuit 17 generates a transaction for the IEEE 1394 serial bus based on the information and writes the transaction to the host computer 11. Hereinafter, this operation will be described in detail.

At this time, in the bus bridge circuit 17, first, substantially the same operation as in the above (A) is performed. That is, the board bus interface 28 in the shared chip 20
Stores the data contained in the write request packet from the processor element 14 in the internal memory 23,
An interrupt is issued to the PU 21. When the CPU 21 receives the interrupt, it jumps to the interrupt handler that processes the interrupt from the board bus interface 28, and
Operation causes the processor element 14 to
An M-Link write response packet is issued.

The subsequent operation is different between the operation described in (A) and the bridge mode. First, in the operation (A), the process immediately returns to the main routine from the interrupt handler, and the operation ends. However, in the case of the bridge mode, an operation of continuously issuing a packet of the IEEE 1394 serial bus is performed as follows without returning from the interrupt handler.

At this point, since the memory address of the host computer 11 and the data to be written are stored in the internal memory 23 through the data of the special format described above, the CPU 21
The header of the asynchronous write request packet of the IEEE 1394 serial bus is generated on the internal memory 23.

Thereafter, as described above, the header and data are written in the transmission FIFO of the LLC 37 and written in the control register, thereby transmitting a write request packet to the system bus 13 which is an IEEE 1394 serial bus. . After that, the CPU 21
Returns from the interrupt handler from the board bus interface 28 to the main routine.

In such an operation, a program for issuing an IEEE 1394 serial bus standard packet is added to the interrupt handler for processing the interrupt from the board bus interface 28 for performing the operation (A) just before returning from the handler. It can be realized by doing.

Furthermore, as described above, LLC 37
Since the processing is performed only up to the processing level of the asynchronous packet, the processing at the transaction level must be performed by the bus bridge circuit 17. Therefore, it is necessary to confirm that the write response packet corresponding to the IEEE 1394 bus standard write request packet transmitted at this time returns.

If a write response packet does not return within a certain period of time after issuing a write request packet, it is necessary to take measures such as resending the write request packet. This operation is performed by the CPU 21 before the interruption is performed, as described immediately before the description of (G).
Is performed by a normally executed program.

At this time, the CPU 21 still outputs the LLC 37
The request packet from which no write response packet has been returned from the CPU 21 is stored in the internal memory 23 and the CPU 21 responds to each of the write request packets one by one.
A variable such as a counter is provided on an internal integer register or the like, and this counter is incremented at regular intervals. When the counter becomes equal to or more than a predetermined value, an operation such as resending the write request packet is performed again. The CPU 21 repeats this operation indefinitely as a normally executed program.

When the write response packet is returned, the LLC 37 interrupts the shared chip 20 of the bus bridge circuit 17 through the external interrupt signal line 39 as described above.
Jump to the interrupt handler for the same external interrupt as in (I). Then, the following operation is added to this interrupt handler.

When the packet read from the receive FIFO is a write response packet, the write request packet held in the internal memory 23 is removed from the internal memory 23 as described above. Return from the interrupt handler. CPU 21 above
In the program normally executed in the above, the count is performed only for the write request packet for which the response packet is not returned. Therefore, the program is removed from the count target by the processing of the interrupt handler.

As described above, the operation of the bridge circuit is performed. Here, since processing according to the IEEE 1394 serial bus standard is performed by the CPU 21, speed may be an issue. However, a high-speed processing originally developed for performing a floating-point multiply-accumulate operation by a processor element at high speed is considered. Since a simple CPU is used, sufficient performance can be ensured for an application with a relatively small communication amount, such as molecular orbital calculation.

As described above, according to the above-described embodiment, the mode required for the processor element 14 is switched between the arithmetic processing mode and the bridge mode by the mode selection signal SEL.
When the interface 21 is in the operating state, the P
An EC (peripheral circuit controller) 25 is added, a program is loaded from a loader generator 27 at the time of initialization, and the timing of an external interface of the CPU 21 is changed so that the same LSI 20 can be connected to a bus bridge. Since it can be used as a part of the circuit 17, the number of steps for circuit development can be drastically reduced.

In the above embodiment, since the density matrix and the like are sent by the transaction generated from the host computer 11, the operation contents of the bus bridge circuit 17 are limited to the above (G) to (I). However, in order to make the system more flexible, a function for generating a transaction for reading the density matrix stored in the memory of the host computer 11 from the processor element 14 may be added. In this case, the following operation (J) is newly required for the bus bridge circuit 17.

(J) From each processor element 14,
Processing of a request to write data in the memory on the host computer 11.

This process can be realized by the following operations.

First, from the processor element 14,
As in the case of (H), a special format indicating a read request from the host computer 11 is written to the internal memory 23 of the shared chip 20 of the bus bridge circuit 17 by generating a write transaction of the PPRAM-Link. This special format includes the fact that the data is to be read from the memory of the host computer and the memory address at which the data is to be read.

Therefore, the bus bridge circuit 17 executes the process (A) in the same manner as the process (H), and then transmits a read request packet of the IEEE 1394 serial bus standard through the LLC 37. , Causing a read transaction and terminating the interrupt handler from the board bus interface 28. Further, as described above, the response packet to the read packet is monitored by the program normally executed by the CPU 21.

Further, the LL is sent from the host computer 11.
When the read response packet is returned via C37,
As described above, since an external interrupt is generated from the LLC 37, a part for processing the read response packet is also added to the handler for performing the external interrupt processing. This process includes an operation not included in the process (H).

First, in this transaction, since the read data is added to the read response packet, the interrupt handler writes the header and data of the read response packet into the internal memory 23. Thereafter, by the same procedure as in the above (C) or (D), the processor element 14 that first generated the read request is sent to the PP for the specific memory address.
Generate a RAM-Link write transaction. It is assumed that the address information of the processor element at this time is included in the special format. As a result, the read data from the host computer 11 stored in the internal memory 23 of the bus bridge circuit 17 is written on the memory of the processor element 14. Thus, a new PPRAM-L
An ink write transaction is not generated in the case of the above (H).

In this interrupt handler, as well as the operation (H), of course, the operation of removing the response packet from the monitoring target of the response packet normally performed in the PU is also performed.

It should be noted that grs is
Is completed, the host computer 11 notifies that fact.
To read the value of grs from the host computer 11, but using the operation (H) of the bus bridge circuit 17, the value of grs is directly transmitted from the processor element 14 to the host computer 11. You may send it.

In the above embodiment, when a request packet from the PPRAM-Link comes to the board bus interface 28, an interrupt is issued to the CPU 21. However, an interrupt is not issued, and a register is provided. Alternatively, each time a request packet arrives, writing to a register may be performed to notify the CPU 21 of that fact.

If the LLC 37 is set so as not to issue an interrupt and the status register is periodically read from the CPU 21, the above-described function can be realized. By doing so, the function of the CPU 21 for processing the interrupt becomes unnecessary, and the number of steps for function verification at the time of development of the shared chip 20 is reduced.

In the above-described embodiment, the internal memory 23 included in the processor element 14 is provided with a plurality of ports to store integer data and floating-point data at the same time. A memory for storing the data and a memory for storing the floating-point data may be separately prepared.

Further, in the above-described embodiment, a 64-bit double-precision floating-point number is handled, but it goes without saying that the format of floating-point data is not limited to this. For example, the bit width of the LM bus and local memory may be 80 bits, and a floating point format represented by a bit length of 80 bits or less may be used.

Furthermore, in the above-described embodiment, an example is shown in which an IEEE 1394 standard serial bus is used for the system bus 13 and a PPRAM-Link is used for the board bus 16. You may comprise.

Further, in the above-described embodiment, the molecular orbital calculation has been described as an example. However, it is needless to say that the present invention can be applied to other applications different from the molecular orbital calculation.

[0268]

As described above, according to the present invention, there is provided a processor element circuit in which the configuration as a processor element has been extended to a minimum necessary, and an operation processing mode and a bridge mode are provided by a mode selection signal. And the same LSI,
Since it can be shared as a part of the bus bridge circuit with the processor element, the man-hour for circuit development can be dramatically reduced, and the system development period and cost can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram when an embodiment of a processor element circuit according to the present invention is used as a processor element of a parallel computing system.

FIG. 2 is a block diagram showing a configuration of an embodiment of a parallel computing system according to the present invention.

FIG. 3 is a block diagram when an embodiment of a processor element circuit according to the present invention is used as a part of a bus bridge circuit of a parallel computing system.

FIG. 4 is a diagram illustrating a configuration of a PPRAM-Link used for a board bus of the parallel computing system according to the embodiment;

FIG. 5 is a diagram illustrating a transaction of a PPRAM-Link used for a board bus of the parallel computing system according to the embodiment;

FIG. 6 is a block diagram showing an internal configuration of a board bus interface according to the embodiment of the processor element circuit.

FIG. 7 is a block diagram showing an example of a dedicated system for parallel calculation.

[Explanation of symbols]

 1,11 host computer 2,12 board 3,13 system bus 4,14 processor element 5,15 local memory 6,16 board bus 7,17 bus bridge circuit 20 shared chip 21 CPU 22 floating point arithmetic unit 23 internal memory 24 local Memory controller 25 Peripheral circuit controller 26 Multiplexer 27 Load generator 28 Board bus interface 30 Processor element internal bus 31 Local memory internal bus 32 Instruction bus 33 Floating point data bus 34 Input terminal of mode selection signal SEL 35 Interrupt signal line 36 ROM 37 Link layer Controller 38 Physical layer controller 39 External interrupt signal line 40 Address decoder 41 FIFO for bypass 42 Flow control Over La 43 input queue 44 receives the packet generator 45 output queues 46 interrupt generation block 47 the memory access block 48 control status register

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Satoru Yamada 430 Nakaicho Sakai, Ashigarakami-gun, Kanagawa Prefecture Green Tech Nakai Fuji Xerox Co., Ltd. (72) Kazuaki Murakami, Inventor 4-1-2-307, Kasuga Park, Kasuga City, Fukuoka Prefecture Ichiyasu 3-24-1, Takada, Toshima-ku, Tokyo F-term (reference) 5B045 AA07 BB11 BB12 BB14 BB42 FF02 FF06 GG11 HH01 KK04 5B056 BB00 BB31 FF15 5B061 FF01 FF02 GG01 GG13

Claims (5)

[Claims] 1. A processor element circuit used in a parallel computing system having a function of performing arithmetic operations in parallel, a plurality of buses, and a bridge circuit for bridging the plurality of buses. An internal memory for storing data; and a first register therein, wherein an operation is performed on the data read from the internal memory or the first register, and the operation result is stored in the internal memory or the first memory. A processor to be stored in one register, a mode selector for selecting whether to operate the processor element circuit in an arithmetic processing mode or a bridge mode, and the arithmetic processing mode is selected by the mode selector. The mode selection means between the processor element circuit and the external memory. When the ridge mode is selected, interface means for inputting and outputting data between the processor element circuit and the peripheral circuit; and when the arithmetic processing mode is selected by the mode selection means, the apparatus stands by at startup. State, and becomes an operating state by a subsequent start operation. When the bridge mode is selected by the mode selecting means, the state becomes a boot state at the time of start, and becomes an active state by a subsequent transition operation, and further stores data therein. Operating in accordance with an instruction sequence, and at least a function of controlling the arithmetic unit, and the external memory or the peripheral circuit and the second circuit in accordance with a selection result by the mode selection means. Input / output data to / from a register or the first register Processor means having a function; supplying a specific instruction sequence to the processor means in the boot state; storing the instruction sequence read from the ROM by the specific instruction sequence in the internal memory; After the supply of the sequence is completed, the transition operation is performed on the processor, and when the processor is in the operating state, an instruction selecting unit that reads an instruction sequence from the internal memory and supplies the instruction to the processor, The input data is stored in the internal memory or the external memory, the data stored in the internal memory or the external memory is read and output to the external bus, and the processor is operated in response to an input from the external bus. External bus interface means for performing the starting operation on the means. Instrument circuit. 2. The processor means comprises means for processing an interrupt, wherein the interface means receives an interrupt from the peripheral circuit when a bridge mode is selected by the selection input, and 2. The processor according to claim 1, wherein said external bus interface means includes means for supplying an interrupt to said processor means when specific data is input from said external bus. Element circuit. 3. A host for controlling the entire system in a parallel computing system having a function of performing arithmetic operations in parallel, a plurality of buses, and a bridge circuit for bridging the plurality of buses. 3. A computer, and the processor element circuit according to claim 1 or 2, wherein the processor is set to the arithmetic processing mode by the mode selection means, and a plurality of boards each mounting a plurality of the processor elements. A first bus for connecting the external bus interface means of the plurality of processor elements on each of the boards; a second bus for connecting the host computer and the plurality of boards; A bus, and a processor element circuit according to claim 1 or 2. A mode is set to a bridge mode by the mode selecting means. On each of the boards, the external bus interface means is connected to the first bus, and the interface means is connected to the second bus through a conversion circuit. The first bus and the second bus
And a bus bridge for mutually performing protocol conversion between the bus and the bus. 4. The parallel computing system according to claim 3, wherein said first bus and said second bus having different protocols are provided.
A bus bridge method for performing a protocol conversion between the first bus and a bus, wherein a write request including a write request, a write address, and write data to a node located outside the first bus is transmitted from the processor element to a second bus. Receiving a write data based on the write information, and writing the write data to the write address based on the write information based on the write procedure of the second bus. A bus bridge method, characterized in that: 5. The parallel computing system according to claim 3, wherein said first bus and said second bus having different protocols are provided.
A bus bridge method for performing protocol conversion between the processor element and a bus, wherein the processor element stores a read request from a node located outside the first bus, a read address, and an address of a processor element that stores read data. Receiving read information including the following based on a write procedure of the first bus; and reading data from the read address based on the read procedure of the second bus based on the read information. And a procedure for writing the read data to an address of a processor element included in the read information based on a write procedure for the second bus.