JP2000269906A - Seamless multiplexer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To decrease delays caused in a processing stage from an input time unitl a multiplexing processing time and to minimize accumulated errors caused when replacing time referencing information. SOLUTION: A signal system conversion circuit 11 selectively converts a TS signal of an M system into a TS signal of a required N system, a multiplexer circuit 12 multiplexes the converted TS signal on a TS signal, a PCR extract circuit 13 extracts a packet including a PCR denoting a reference time required to configure a program from the TS signal of the M system, a PCR reproducing circuit 14 rewrites contents of the PCR in this packet into contents, to which the time required for signal conversion processing by the signal system conversion circuit 11 is added, and the multiplexer circuit 12 multiplexes the rewritten contents on the TS signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention selects and multiplexes a required transport stream from a plurality of transport streams in the field of digital media processing for communicating, storing, and broadcasting encoded data. The present invention relates to a seamless multiplexing device.

[0002]

2. Description of the Related Art In recent years, in the field of digital media processing for performing communication, storage, broadcasting, etc. of encoded / compressed signals, the transmitting device side has, for example, an MPEG (Moving Picture C).
In some cases, video, audio, and data constituting a program are compressed and multiplexed using a coding and compression method standardized by the odingExperts Group 2 to generate a single transport stream (TS) and broadcast. . In particular, for this multiplexing process, a seamless multiplexing device as shown in FIG. 5 is used.

In FIG. 5, a seamless multiplexing apparatus includes seamless splicers 51 and 52 and a multiplexing unit 53, each of which has a function completed as a single device. That is, a part of the input TS signals of a plurality of systems is directly supplied to the multiplexing unit 53, and the remaining systems are supplied to the seamless splicers 51 and 52, respectively. The seamless splicers 51 and 52 transmit a plurality of T-inputs in accordance with the instructions of the corresponding control units 54 and 55.
A required TS signal is selected from the S signals and output to the multiplexing unit 53. The multiplexing unit 53 multiplexes the input TS signals of a plurality of systems according to an instruction from the control unit 56, and
It generates and outputs two TS signals.

By the way, the seamless splicer 5
1, and 52 and the multiplexing unit 53 each include a PCR (Program Clock Reference) indicating a reference time required for composing a program,
In accordance with the processing of each of the seamless splicers 51 and 52 and the multiplexing unit 53, it is necessary to rewrite the contents of the PCR with the contents obtained by adding the time required for each processing and newly replace the contents. However, if the rewriting and replacement processing of the PCR is performed by the single devices of the seamless splicers 51 and 52 and the multiplexing unit 53, a fixed delay occurs in the signal processing of each single device, and finally, P
An error due to the replacement of the CR, that is, the PCR jitter is cumulatively increased.

On the other hand, as a countermeasure, the P
Although it is considered to suppress the CR jitter, executing the process of suppressing the PCR jitter in each single device leads to a complicated process such as a flow control and an increase in hardware cost. It will also be.

[0006]

As described above, in the conventional seamless multiplexing apparatus, since the rewriting and replacement processing of the PCR is performed by each single device, a fixed delay occurs in the signal processing of each single device. And finally P
There is a problem that CR jitter is cumulatively increased. In addition, if the processing for suppressing the PCR jitter is executed by each single device, the processing such as the flow control becomes complicated, and the cost of the hardware increases.

Therefore, an object of the present invention is to reduce a delay generated in a process from input to multiplexing.
It is an object of the present invention to provide a seamless multiplexing apparatus capable of minimizing a cumulative error of replacement of time reference information and reducing a processing load on each component device.

[0008]

SUMMARY OF THE INVENTION A seamless multiplexing device according to the present invention is a seamless multiplexing device for multiplexing a plurality of transmission signals constituting a program, in which a plurality of packets are arranged in one system and a program is transmitted. Signal system conversion means for selectively converting an M (M is a natural number) transmission signal including a packet to which time reference information indicating a reference time required for the configuration is added into an N (N is a natural number) transmission signal When,
A time reference for extracting a packet including time reference information from the transmission signal of the M system, and rewriting the time reference information in the packet to information obtained by adding a time required for processing of the transmission signal input by the signal system conversion unit. Information extraction / rewriting means; multiplexing means for multiplexing the N-system transmission signal converted by the signal system conversion means and the time reference information rewritten by the time reference information extraction / rewriting means into a multiplexed signal; Control for controlling the signal system conversion unit so as to output a transmission signal of an arbitrary system from the system conversion unit, multiplexing the transmission signal of the arbitrary system, and controlling the multiplexing unit so as to add time reference information Means.

According to this configuration, the M transmission signals are selectively converted into the required N transmission signals, and then multiplexed into one multiplexed signal. Is extracted, and the time reference information is rewritten into information to which the time required for the signal conversion processing from the M system to the N system is added and multiplexed into the multiplexed signal. As a result, the rewriting and replacement of the time reference information need only be performed once, so that it is possible to reduce the delay in the processing process from the time of input to the time of multiplexing. It is possible to minimize the information rewriting and replacement replacement errors.

In the above configuration, the signal system conversion means includes a system conversion input signal storage means for temporarily storing the input M transmission signals for each system, and an N system transmission signal output to the multiplexing means. System conversion output signal storage means for temporarily storing signals for each system, and system conversion connection means for selectively connecting between the system conversion input signal storage means and the system conversion output signal storage means. The multiplexing means includes multiplexing input signal storage means for temporarily storing N transmission signals output from the signal system conversion means for each system, and multiplexing signal storage means for temporarily storing multiplexed signals. The output signal storage means, the multiplex output signal storage means and the multiplex input signal storage means are connected in a time-division manner, and the time reference information extraction / rewrite means is connected to the multiplex output signal storage means. Multiplex connection A time reference information extracting / rewriting means for extracting time reference information from the M-system transmission signal; and a time reference information extracted by the time reference information extracting means. Means for rewriting information to which the time required for processing of the transmission signal input by the system conversion means and the multiplexing means has been added and providing the information to the multiplexing connection means of the multiplexing means. And a means for controlling the connection processing in the connection means for use and the connection processing in the multiplex connection means.

The input signal storage means for system conversion includes M
Input buffers are arranged in parallel, and there are means for accumulating transmission signals of M systems in the input buffers for each system for each packet, and the output signal storage means for system conversion comprises N
Output buffers are arranged in parallel, and N transmission signals selectively derived by the system conversion connection means are output by one.
The multiplexing input signal storage means includes means for accumulating the data in an output buffer for each system for each packet, and the multiplexing input signal storage means includes N input buffers arranged in parallel, and is output from the system conversion output signal storage means. Means for accumulating N transmission signals in corresponding input buffers for each packet, the multiplexing output signal storage means having at least one output buffer capable of accumulating a maximum of N packets, Means for accumulating in the output buffer packets of the N systems sequentially derived by the multiplexing connection means, and accumulating the time reference information given by the time reference information extraction / rewriting means in the output buffer. .

Therefore, according to this configuration, in the process of selecting the required N transmission signals from the M transmission signals and multiplexing them into the multiplexed signal, the buffer memory capable of storing one packet is (M + 2N). And one buffer memory capable of storing a maximum of N packets can be used to minimize the buffer memory capacity required for the multiplexing process.
Since the optimal control flow can be realized by integrating the signal system conversion processing and the multiplexing processing, it is highly reliable and can contribute to cost reduction.

In the above arrangement, the control means controls the multiplexing means of the multiplexing means so that the transmission rate of the multiplexed signal output from the multiplexing means is the same as the transmission rate when the M packets are serially arranged. Means for adding an invalid dummy packet having the number of bits corresponding to the unit packet length to the N packets derived by the above. By doing so, it becomes possible to match the transmission rate of the multiplexed signal to the transmission rate when serially arranging M packets to be transmitted at the time of input.

In the above configuration, there is provided a signal separating means provided before the signal system converting means and separating a part of the M transmission signals to be input to the signal system converting means from one multiplexed signal. Transmission rate changing means for changing the transmission rate of the transmission signal of a part of the transmission signals of the plurality of transmission signals separated by the signal separation means to an arbitrary transmission rate and sending the transmission signal to the signal system conversion means, The control means
It is characterized by comprising means for controlling the signal separation processing of the signal separation means and the transmission rate in the transmission rate changing means.

[0015] With this configuration, when the signal format of the M system transmission signals differs from system to system and signal separation and transmission rate change are required for multiplexing, first, a necessary part is required. By performing the signal separation process and the transmission rate change process on the transmission signal of the system, if the signal format is adjusted to the same signal format that can be processed by the signal system conversion unit and the multiplexing unit for each system,
Thereafter, the signal system conversion process and the multiplexing process can be easily executed, and the signal separation process, the transmission rate change process, the signal system conversion process, and the signal multiplexing process can be controlled collectively by one control means. In addition, it is possible to determine the processing routing of the transmission signal to be multiplexed, and to optimize the flow control in the multiplexing of the transmission signals of a plurality of systems based on the processing routing, thereby reducing the processing burden of each component device. Can be reduced.

Further, in the above configuration, the signal separating means,
At least two of the transmission rate changing means, the signal system converting means, and the multiplexing means insert a separately provided program information signal relating to the program into the transmission signal, or replace the program information signal multiplexed with the transmission signal. Is performed.

According to this configuration, it is possible to make distributed processing for local management of the program information signal effective.

[0018]

Embodiments of the present invention will be described below in detail with reference to the drawings. (First Embodiment) FIG. 1 is a circuit block diagram showing an embodiment of a seamless multiplexer according to the present invention. In FIG. 1, reference numeral 1 denotes a multiplex processing unit. And
The M (M is a natural number) TS signal constituting the program is converted into an N (N is a natural number) TS signal by the signal system conversion circuit 11 of the multiplex processing unit 1 and multiplexed by the multiplexing circuit 12. To generate one TS signal.

The TS signal of the M system is an MPEG signal.
This is a signal encoded by the -2 encoding method, and includes a packet in which a plurality of packets are arranged in one system and a PCR is added. The TS signal may be a single program in which video, audio, and data are composed of one type of component, or may be a multi-program TS in which a plurality of programs are multiplexed.

The TS signal of the M system is supplied to
And one signal is supplied to the PCR extraction circuit 13. The PCR extraction circuit 13 extracts a PCR packet included in the TS signal of one of the input M systems. The content of the extracted PCR packet signal is rewritten by the PCR reproducing circuit 14 to the content obtained by adding the time required for processing the transmission signal input by the signal system conversion circuit 11, and It is multiplexed with the TS signal.

Further, the multiplexing processing unit 1 includes an M-system TS
The signal system conversion circuit 11 is controlled to select and output a TS signal of an arbitrary system from the signals, multiplex the TS signal of the arbitrary system, and add a packet signal of the PCR output from the PCR reproduction circuit 14 A control unit 3 for controlling the multiplexing circuit 12 is provided.

FIG. 2 is a circuit block diagram showing a specific configuration of the signal system conversion circuit 11. As shown in FIG. That is, the signal system conversion circuit 11 temporarily stores the input M-system TS signals for each system, and temporarily stores the N-system TS signals output to the multiplexing circuit 12 for each system. An output signal storage unit 111 for accumulating data and a connection unit 112 for selectively connecting the input signal storage unit 110 and the output signal storage unit 111 are provided.

The input signal storage section 110 has M buffer memories 1101 to 110M arranged in parallel, and the output signal storage section 111 has N buffer memories 1 to 110M.
111 to 111N are arranged in parallel. That is, the input M-system TS signal is input to the M buffer memories 1.
One packet is stored in 101 to 110M for each system. The control unit 3 reads out the M-system TS signals stored in the M buffer memories 1101 to 110M from the buffer memories 1101 to 110M in packet units.

The TS signals of the N systems selected by the connection unit 112 are stored in N buffer memories 1111 to 111N, one packet for each system. The N-system TS signals stored in these N buffer memories 1111 to 111N are transmitted to the buffer memory 1 by the control unit 3.
It is read from 111 to 111N in packet units. The connection unit 112 controls the buffer memories 1101 to 110M and the buffer memories 110 and 110M so that the control unit 3 selects TS signals of a required system from the M TS signals read from the M buffer memories 1101 to 110M. 11
The connection processing between the communication terminals 11 to 111N is controlled. Also,
The control unit 3 instructs which TS signal is to be switched seamlessly from which TS signal, and also specifies the switching timing.

FIG. 3 is a circuit block diagram showing a specific configuration of the multiplexing circuit 12. As shown in FIG. That is, the multiplexing circuit 1
2 is the N system T output from the signal system conversion circuit 11
Input signal storage unit 12 for temporarily storing S signals for each system
1, a buffer memory 122 capable of storing a maximum of N packet signals, and a connection between the buffer memory 122 and the input signal storage unit 121.
2 and a connection section 123 for connecting the PCR reproduction circuit 14 to the PCR reproduction circuit 14.

The input signal storage unit 121 has N buffer memories 1211 to 121N arranged in parallel. The N-system TS signals output from the signal-system conversion circuit 11 include N buffer memories 1211 to 1212.
One packet is stored in 1N for each system. These N
The N-system TS signals stored in the buffer memories 1211 to 121N are read by the control unit 3 from the buffer memories 1211 to 121N in packet units. The read N packet signals are transmitted to the connection unit 1
At 23, the data is selectively derived in a time division manner and sequentially stored in the buffer memory 122.

The signal stored in the buffer memory 122 is output by the control unit 3 as one read and multiplexed TS signal. Note that the packet signal of the PCR is also selected and derived by the connection unit 123 as necessary, and stored in the buffer memory 122, so that the TS
Multiplexed with the signal.

In the above configuration, the difference between the bit rate at the time of multiplexing of the M-system TS signals to be converted into a broadcast wave and transmitted and the bit rate of the TS signals multiplexed by the multiplexing circuit 12 is different. Come up. Therefore, the control unit 3
The dummy packet generation circuit 15 generates an invalid dummy packet having the number of bits corresponding to the unit packet length,
The connection section 123 derives the dummy packets and stores the required number of them in the buffer memory 122. By doing so, the M-system TS to transmit the bit rate of the TS signal multiplexed by the multiplexing circuit 12 should be transmitted.
It is possible to match the bit rate at the time of multiplexing of signals, and it is possible to absorb the difference in bit rate between the time of input and the time of multiplexing.

As described above, according to the above embodiment, the signal system conversion circuit 11 requires M system TS signals.
After selectively converting to the TS signal of the system, the multiplexing circuit 12
Multiplexed into one TS signal, and the T
A packet including a PCR indicating a reference time required for composing a program from the S signal is extracted by the PCR extraction circuit 13,
The contents of the PCR are rewritten to the contents to which the time required for the signal conversion process by the signal system conversion circuit 11 is added by the PCR reproduction circuit 14 and are multiplexed with the TS signal by the multiplexing circuit 12, so that the PCR is replaced. The processing only needs to be performed once, so that it is possible to reduce the delay generated in the processing process from the time of input to the time of multiplexing, and it is possible to further minimize the PCR jitter.

Further, according to the above embodiment, the signal system conversion circuit 11 selects the necessary N system TS signals from the M system TS signals, and the multiplexing circuit 12 multiplexes the TS signals into one TS signal. In the process, (M + 2N) buffer memories capable of accumulating one packet and one buffer memory capable of accumulating a maximum of N packets can be used to minimize the buffer memory capacity required for the multiplexing process. Since the processing of the circuit 11 and the processing of the multiplexing circuit 12 can be collectively performed to realize an optimal control flow, the reliability is high and the cost can be reduced.

In the above embodiment, PMT (Program MapTable) and PAT (Pr (Pr
A packet signal such as a gram association table) is collectively inserted into the TS signal by the multiplexing circuit 12. Also,
The multiplexing circuit 12 also processes the TS signal derived from the signal system conversion circuit 11 and which does not conform to the MPEG standard, and removes incomplete PCR and the like from the continuous PCR.
And outputs a TS signal conforming to the MPEG standard.

(Second Embodiment) A second embodiment of the present invention relates to a case where the signal formats of M-system TS signals are different from each other for each system, and signal separation and transmission rate change are required for multiplexing. Prior to the signal system conversion process, a signal separation process and a transmission rate change process are performed on some of the systems so as to match the signal format that is the same for each system and can be processed by the multiplex processing unit. is there.

FIG. 4 is a circuit block diagram showing a second embodiment of the seamless multiplexer according to the present invention. In FIG. 4, the same portions as those in FIG. 1 are denoted by the same reference numerals, and detailed description will be omitted.

That is, a signal demultiplexing unit 41 and transcoder units 42 and 43 are arranged at a stage preceding the multiplex processing unit 1. Some of the M TS signals (three in the figure) encoded by the MPEG-2 encoding method are signals directly supplied to the multiplex processing unit 1, and the remaining TS signals are the remaining signals. The system is a signal separated by the signal separation unit 41.
In accordance with an instruction from the control unit 44, the signal separation unit 41 classifies the input multiplexed TS signal for each PID (program ID), and outputs a TS signal for each PID. A part of this output is supplied to the multiplex processing unit 1, and the rest is supplied to the transcoder units 42 and 43, respectively.

That is, the signal separating section 41 is controlled by the control section 44
Switch the output line in accordance with the instruction, and output the TS to the multiplex processing unit 1 and the transcoder units 42 and 43.
Distribute the signal. Regarding this switching, simple switching is performed for a TS signal that is not connected at the time of power-on or when a new program is generated. On the other hand, seamless switching is performed from one program to another program or a TS signal that is continuously continued, such as insertion of a commercial (CM).

Each of the transcoders 42 and 43 changes the bit rate of the input TS signal to the bit rate specified by the control unit 44 and sends the signal to the multiplex processing unit 1.

As described above, according to the second embodiment, the signal formats of the M TS signals are different from each other for each system, and depending on the multiplex processing unit 1, signal separation processing and transmission rate change must be performed. If this is not the case, first, signal separation processing by the signal separation unit 41 and transmission rate change processing by the transcoder units 42 and 43 are performed on TS signals of some systems, so that multiplexing processing is the same for each system. If the signal format is adjusted to a signal format that can be processed by the unit 1, the multiplex processing unit 1 can easily execute the signal system conversion process and the multiplexing process. Further, the signal separation processing in the signal separation section 41, the transmission rate change processing in the transcoder sections 42 and 43, the signal system conversion processing in the signal system conversion circuit 11, and the signal multiplexing processing in the multiplexing circuit 12 are collectively performed by one control section 44. Therefore, the related equipment can be integrated and the processing routing of the TS signal to be multiplexed can be obtained. Based on this processing routing, the flow control in the multiplexing of the TS signals of a plurality of systems can be optimized. Therefore, the processing load on each component device can be reduced.

In the second embodiment, a PSI (Program Service) indicating information on a separately provided program is provided.
e Information) / SI (Service Information) signals are normally inserted or edited in the multiplex processing unit 1 in a unified manner.
Insertion or editing may be performed by at least two or more circuits such as the transcoder units 42 and 43. By doing so, it becomes possible to make distributed processing for local management of PSI / SI effective. Also, TS
When a PSI / SI signal is multiplexed on a signal, the multiplexing processing unit 1, the signal separation unit 41, the transcoder unit 42,
PSI / SI in at least two of the circuits 43
A signal exchange process may be performed.

In the second embodiment, the outputs of the signal separation unit 41 and the transcoder units 42, 43
Although it is a signal, even a signal in a provisional format that does not conform to the MPEG-2 standard may be a signal that is identifiable by the multiplex processing unit 1. The cost can be reduced as compared with the case of connecting.

In the second embodiment, the PC
Since it is not necessary to replace R in each single device, unnecessary jitter given to the PCR signal by each device can be suppressed.
Furthermore, since only the necessary TS signal is separated in the signal separation unit 41, no delay occurs in the TS signal that has been passed through, and the PCR jitter of the output of the multiplex processing unit 1 is suppressed. Further, in the multiplex processing unit 1, as shown in the first embodiment, a PMT (Program Map Table), PA
It goes without saying that packet signals such as T (Program Association Table) are collectively inserted into the TS signal.

(Other Embodiments) The present invention is not limited to the above embodiments. For example, in each of the embodiments described above, a PCR signal is described as an example of time reference information. However, for example, a DTS (Decoder Time S
tance) or PTS (Presentation Time Stance)
And so on. In addition, the configuration of the multiplex processing unit, the configuration of the signal separation unit, the configuration of the transcoder unit, and the like can be variously modified without departing from the scope of the present invention.

[0042]

As described in detail above, according to the present invention,
It is possible to provide a seamless multiplexing apparatus capable of reducing a delay generated in a processing process from an input time to a multiplexing process, minimizing a cumulative error of replacement of time reference information, and reducing a processing load on each component device. it can.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram showing an embodiment of a seamless multiplexer according to the present invention.

FIG. 2 is a circuit block diagram showing a specific configuration of the signal system conversion circuit shown in FIG. 1;

FIG. 3 is a circuit block diagram showing a specific configuration of the multiplexing circuit shown in FIG. 1;

FIG. 4 is a circuit block diagram showing a second embodiment of the present invention.

FIG. 5 is a circuit block diagram showing a conventional seamless multiplexer.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Multiprocessing part, 2 ... Signal distribution part, 3,44 ... Control part, 11 ... Signal system conversion circuit, 12 ... Multiplexing circuit, 13 ... PCR extraction circuit, 14 ... PCR reproduction circuit, 15 ... Dummy packet generation circuit 41, a signal separation unit, 42, 43 a transcoder unit, 110, 121 an input signal storage unit, 111 an output signal storage unit, 112, 123 a connection unit, 1101 to 110M, 1111 to 111N a buffer memory, 1211 ~ 121N, 122 ... buffer memory.

Continued on the front page F-term (reference)

Claims (6)

[Claims] 1. A seamless multiplexing device for multiplexing transmission signals of a plurality of systems constituting a program, wherein a plurality of packets are arranged in one system and a time reference indicating a reference time required for constituting the program. Signal system conversion means for selectively converting an M (M is a natural number) system transmission signal including a packet to which information is added into an N (N is a natural number) system transmission signal; and time reference information from the M system transmission signal. A time reference information extracting and rewriting means for extracting a packet including the time reference information in the packet, and rewriting the time reference information in the packet to information obtained by adding a time required for processing of the transmission signal input by the signal system converting means; Multiplexing means for multiplexing the N-system transmission signals converted by the signal-system conversion means and the time reference information rewritten by the time reference information extraction rewriting means to generate one multiplexed signal; Controlling the signal system conversion means so as to output a transmission signal of an arbitrary system from the signal system conversion device, multiplexing the transmission signals of an arbitrary system, and performing the multiplexing so as to add the time reference information. Control means for controlling the means. 2. The apparatus according to claim 1, wherein the signal system conversion unit receives the input M
System conversion input signal storage means for temporarily storing system transmission signals for each system, and system conversion output signal storage means for temporarily storing N system transmission signals to be output to the multiplexing means, System conversion connecting means for selectively connecting between the system conversion input signal storage means and the system conversion output signal storage means, wherein the multiplexing means is output from the signal system conversion means. Multiplexing input signal storage means for temporarily storing the N transmission signals for each system, multiplexing output signal storage means for temporarily storing the multiplexed signal, and multiplexing output signal storage means And the multiplexing input signal storage means are connected in a time-division manner, and the multiplexing connection means connects the multiplexing output signal storage means and the time reference information extraction / rewriting means. Reference information playback The time reference information extracting means for extracting the time reference information from the transmission signal of the M system, and the time reference information extracted by the time reference information extracting means, Means for rewriting to the information obtained by adding the time required for processing the transmission signal, and providing the information to the multiplexing connection means of the multiplexing means, the control means comprising: a connection process in at least the system conversion connection means; 2. The seamless multiplexing apparatus according to claim 1, further comprising means for controlling connection processing in said multiplexing connection means. 3. The system conversion input signal storage means includes:
A plurality of input buffers arranged in parallel with each other, and a means for accumulating transmission signals of the M systems in the input buffers for each system for each packet, wherein the system conversion output signal storage means comprises N Output buffers are arranged in parallel, and a means for accumulating transmission signals of the N systems selectively derived by the system conversion connection means in an output buffer for each system for each packet, The multiplexing input signal storage means has N input buffers arranged in parallel, and transfers the N transmission signals output from the system conversion output signal storage means to the input buffer corresponding to each packet. The multiplexing output signal storage means has at least one output buffer capable of storing a maximum of N packets, and the N systems of the N systems sequentially derived by the multiplexing connection means. With accumulating packets to the output buffer, seamless multiplexing apparatus of claim 2, wherein said time reference information provided by the time reference information extracting rewriting means, characterized by comprising a means for storing to the output buffer. 4. The multiplexing means for multiplexing the multiplexed signal output from the multiplexing means so that the multiplexed signal output from the multiplexing means has the same transmission rate when the M packets are serially arranged. 3. The seamless multiplexing method according to claim 1, further comprising means for adding an invalid dummy packet having a bit number corresponding to a unit packet length to the N packets derived by the connection means. apparatus. 5. A signal provided before the signal system conversion means and for separating a part of the M transmission signals to be inputted to the signal system conversion means from one multiplexed signal. Separating means, and a transmission rate changing means for changing a transmission rate of a transmission signal of a part of transmission signals of a plurality of systems separated by the signal separation means to an arbitrary transmission rate and sending the transmission signal to the signal system conversion means 2. The seamless multiplexing apparatus according to claim 1, wherein said control means includes means for controlling a signal separation process of said signal separation means and a transmission rate in said transmission rate changing means. 6. At least two or more of said signal separating means, said transmission rate changing means, said signal system converting means and said multiplexing means insert a separately provided program information signal relating to said program into a transmission signal. 6. The seamless multiplexing apparatus according to claim 1, wherein a program information signal multiplexed on the transmission signal is exchanged.