JP2000267620A - Plane display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To avoid the occurrence of discontinuity of a picture in the case of switching at least two different scanning control processings in a vertical scanning period and to avoid the flickering of a scanning line such as line flicker from being conspicuous in the case of increasing the size of a display panel. SOLUTION: In a scanning line control circuit 76, a first scanning control consisting of a first operation period or second scanning control consisting of a second operation period is selected based on a previously set period value, and the selected first scanning control consisting of the first operation period is switched to the second scanning control consisting of the second operation period based on a screen display mode signal inputted from outside. Switching of the two scanning controls is controlled to switch with the timing of period interval in the scanning control of either of them.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flat panel display, and more particularly, to a flat panel display having an enlargement / reduction display function.

[0002]

2. Description of the Related Art In recent years, as a flat display device represented by a liquid crystal display device, a device having a 9:16 effective display area called a wide screen has been developed.

As an image signal input to such a flat display device, there is, for example, a high-vision system (or EDTVII system) having image information with an aspect ratio of 9:16. There is an NTSC system and a PAL system having 3: 4 image information. The different scanning methods include, for example, the current standard TV signal by the interlaced scanning method of the NTSC system and the PAL system, and the non-standard TV signal of the progressive scanning system used as a video signal of a computer or a car navigation device. .

Under such circumstances, for example, as a method of displaying an image on a flat display device having an effective display area having an aspect ratio of 9:16 while maintaining an aspect ratio of 3: 4, a display area is used. Is divided into a first area having an aspect ratio of 9:12 and a second area obtained by removing the first area from an effective display area having an aspect ratio of 9:16, and having an aspect ratio of 3: 4 to be displayed in the first area. The video signal is sampled during a period excluding the horizontal blanking period from one horizontal scanning period,
There is known a method of sampling a video signal to be displayed in an area in a horizontal blanking period.

[0005] This display method is a display method in which video signals having different aspect ratios are displayed while changing only the control of horizontal scanning (hereinafter, a first display method). FIG. 8 is a circuit diagram showing a specific example of the flat display device according to the first display method. Hereinafter, an image display by the first display method will be described with reference to FIG.
This will be described with reference to FIG.

The liquid crystal display device 10 comprises a liquid crystal panel 30 whose screen aspect ratio is set to 9:16, and a panel control section 11 for controlling the liquid crystal panel 30.

The liquid crystal display panel 30 includes a plurality of pixel electrodes 31 arranged in a matrix, and a plurality of scanning lines 33 formed along the rows of the pixel electrodes 31 and transmitting scanning signals.
(Y1, Y2...), A plurality of data signal lines 34 formed along the columns of the pixel electrodes 31, and thin film transistors formed corresponding to intersections of the scanning lines 33 and the data signal lines 34 (TFT), an array substrate including a plurality of switching elements 32, a counter substrate (not shown) including a counter electrode facing the pixel electrodes 31, and a light modulation layer held between the array substrate and the counter substrate. It comprises a liquid crystal layer (not shown). The TFT constituting each switching element 32 includes a scanning line 33.
, A drain electrode connected to the pixel electrode 31, and a source electrode (both not shown) connected to the data signal line.

The scanning signal supplied through the scanning line 33 causes conduction between the source and drain electrodes,
The potential of the data signal line 34 set according to the data signal is applied to the pixel electrode 31.

The effective display area of the liquid crystal panel 30 includes a pixel electrode 31, a counter electrode (not shown), and the pixel electrode 31.
And a plurality of display pixels composed of a liquid crystal layer disposed between the counter electrodes. The light transmittance of each display pixel is controlled by a potential difference between the pixel electrode 31 and the counter electrode.

The panel control section 11 includes an auxiliary video signal generation circuit 13, a timing generation circuit 14, a video selection circuit 15,
It includes a first switch circuit 16a, a second switch circuit 16b, a third switch circuit 18, a video signal processing circuit 19, a horizontal scanning circuit 20, a vertical scanning circuit 21, a level inversion circuit 22, and a common voltage generation circuit 23.

The video signal processing circuit 19 performs video processing such as gamma correction to appropriately drive the liquid crystal display panel 30.

The vertical scanning circuit 21 performs a driving operation for sequentially supplying scanning signals to a plurality of scanning lines 33. The vertical scanning circuit 21 has a shift register circuit (not shown) including a plurality of flip-flops connected in series to internally transmit a vertical scanning start signal STV corresponding to the plurality of scanning lines 33. This shift register circuit performs a shift operation of the vertical scanning start signal STV in response to the vertical scanning clock signal CPV.
And outputs a scanning signal to the scanning line 33 corresponding to the flip-flop that has latched. The period during which the scanning signal is output to the scanning line 33 is controlled by the gate output control signal GOE.

The horizontal scanning circuit 20 includes a video signal processing circuit 1
Video signals supplied from 9 through the level inversion circuit 22 are sequentially sampled and held as data signals, and a driving operation of driving a plurality of data signal lines 34 in accordance with the data signals is performed. The horizontal scanning circuit 20 is a driver configured similarly to each other, and includes a first driver IC 20a to a fourth driver IC 20d that respectively drive four blocks of data signal lines 34. First to fourth drivers I
At least C20a to 20d are connected in series to internally transmit the horizontal scanning start signal STH, and each is constituted by a plurality of flip-flops connected in series corresponding to the data signal line 34 of one block. It has one shift register (not shown). Each shift register responds to the horizontal scanning clock signal CPH to generate a horizontal scanning start signal S.
The shift operation of TH is performed. First to fourth driver ICs 20
Samples a to 20d sample and hold the video signal at the timing at which each flip-flop outputs the horizontal scanning start signal STH, and supply the data signal to the data signal line 34 corresponding to this flip-flop.

The auxiliary video signal generating circuit 13 generates an auxiliary image such as channel information displayed in a remaining area when a video signal having an aspect ratio of 3: 4 is displayed on the liquid crystal panel 30 set to an aspect ratio of 9:16. The auxiliary signal to be represented is generated using the horizontal blanking period of the video signal.

The video selection circuit 15 outputs, to the switches 16a and 16b, a selection signal for selecting, for example, a Hi-Vision video signal input from the terminal 41 or an NTSC video signal input from the terminal 42 by an external input from the terminal 40. At the same time, the selected video signal having an aspect ratio of 3: 4 is displayed in a full display mode for displaying the entire effective display area or in a first area of the effective display area, and an auxiliary image is displayed in a second area which is a remaining area. The display mode to be selected is selected, and a mode selection signal corresponding to the selection result is output to the timing generation circuit 14.

The timing generation circuit 14 controls the auxiliary video signal generation circuit 13, the switch circuit 18, the video signal processing circuit 19, the horizontal scanning circuit 20, and the vertical scanning circuit 2 at the timing corresponding to the selection mode by controlling the mode selection signal.
Control 1

When a high-definition video signal is selected, the switch circuit 16a supplies the horizontal and vertical synchronizing signals obtained from the high-definition video signal input from the terminal 41 to the timing generation circuit 14, and inputs the same from the terminal 42. When the NTSC video signal is selected, the video selection circuit 15 supplies the horizontal and vertical synchronization signals obtained from the NTSC video signal to the timing generation circuit 14.
Is controlled by the selection signal from.

The switch circuit 16b similarly supplies the high definition video signal to the video signal processing circuit 19 when the high definition video signal is selected, and converts the NTSC video signal to the video signal processing circuit when the NTSC video signal is selectively output. Supply to 19.

When the NTSC video signal is selected and the mode signal corresponds to the full display mode, the switch circuit 18 guides the NTSC video signal to the video signal processing circuit 19 via the switch circuit 16b. When the NTSC video signal is selected and the mode signal is a display mode other than the full display mode, the switch circuit 18 performs an operation of allocating the auxiliary video signal from the auxiliary video signal generation circuit 13 to the horizontal blanking period of the NTSC video signal. Then, the multiplexed video signal is guided to the video signal processing circuit 19 via the switch 16b.

The common voltage generation circuit 23 generates a common voltage VCOM whose level is inverted with respect to the reference voltage in each horizontal scanning period and each vertical scanning period by controlling the polarity inversion signal POL from the timing generation circuit 14. Supply to counter electrode.

The level inversion circuit 22 controls the polarity inversion signal POL from the timing generation circuit 14 to control the high-definition video signal supplied from the video signal processing circuit 19,
The level of the NTSC video signal or the multiplexed video signal is inverted with respect to the reference voltage in the opposite phase in synchronization with the inversion of the level of the common voltage VCOM, and is output. As a result, the polarity of the liquid crystal applied voltage is periodically inverted.

FIG. 9 is a circuit diagram showing a specific example of the timing generation circuit 14. As shown in FIG. This timing generation circuit 14
Has a video processing control circuit 51, a PLL circuit 52, a vertical timing generation circuit 57, a horizontal scanning control circuit 61, a vertical scanning control circuit 71, and a polarity inversion signal generation circuit 80.

The PLL circuit 52 includes a voltage controlled oscillator (VC
O) 53, a loop filter 54, a phase comparison circuit 55, and a counter 56. In the PLL circuit 52, the phase comparison circuit 55 detects a phase error between the horizontal synchronization signal supplied from the switch circuit 16a and the reference horizontal signal supplied from the counter 56, and generates an error signal corresponding to the phase error. The loop filter 54 includes a phase comparison circuit 55
A signal voltage is generated by removing high-frequency components and noise from the error signal obtained from. The counter 56 counts the number of pixels in one row, divides the frequency of the reference clock signal in accordance with the number of pixels, and supplies the frequency to the phase comparison circuit 55 as a reference horizontal signal. The reference horizontal signal and the reference clock signal are further supplied to a horizontal scanning control circuit 61, a video processing control circuit 51, and a polarity inversion signal generation circuit 80.

The video processing control circuit 51 includes a video selection circuit 1
5 based on the mode signal from the counter 5 and the count signal from the counter 56.
8 and the video signal processing circuit 19 are controlled. In a display mode in which a video signal having an aspect ratio of 3: 4 is displayed in a first area of the effective display area and an auxiliary image is displayed in a second area which is a remaining area, the auxiliary video signal is enabled during a horizontal blanking period of the video signal. The video switching signal is supplied from the video processing control circuit 51 to the auxiliary video signal generation circuit 13 and the switch circuit 18 in order to perform the above operation.

The polarity inversion signal generation circuit 80 generates a polarity inversion signal POL supplied to the level inversion circuit 22 and the common voltage generation circuit 23. This polarity inversion signal POL
Is a signal whose level is inverted in each horizontal scanning period and each horizontal scanning period based on the mode signal from the video selection circuit 15 and the count signal from the counter 56 in order to periodically invert the polarity of the liquid crystal application voltage. is there.

The vertical timing generation circuit 57 detects the vertical synchronization timing from the synchronization signal supplied from the switch circuit 16a, and detects the vertical timing based on the reference clock signal from the voltage controlled oscillator 53 and the count signal from the counter 56. A vertical timing signal, which is a signal, is generated and supplied to the vertical scanning control circuit 71. The vertical timing signal includes a field signal, a frame signal, and the like detected by the vertical timing generation circuit 57 based on the synchronization signal supplied from the switch circuit 16a.

The horizontal scanning control circuit 61 includes a video selection circuit 1
The horizontal scanning circuit 20 is controlled based on the mode signal from the control signal 5, the reference clock signal from the voltage controlled oscillator 53, and the count signal from the counter 56. That is, the horizontal scanning control circuit 61 controls the horizontal scanning start control circuit 62 for controlling the start timing of the sampling operation of the video signal and the PLL.
A clock adjusting circuit 63 for adjusting the reference clock signal supplied from the circuit 52.

The horizontal scanning start control circuit 62 generates control signals such as a horizontal scanning start signal STH and a phase control signal at a predetermined timing in synchronization with a horizontal reference clock signal based on a count signal supplied from the counter 56. . The phase of the horizontal scanning start signal STH is the full display mode, or a two-screen display in which a video signal having an aspect ratio of 3: 4 is displayed in a first area of an effective display area and an auxiliary image is displayed in a second area which is a remaining area. The phase is switched to a preset individual phase by a mode signal supplied from the video selection circuit 15 such as a mode.

The clock adjusting circuit 63 converts the reference clock signal from the horizontal scanning clock signal CP having the first or second frequency.
A horizontal scanning clock signal generating circuit 65 for generating H, a horizontal scanning start control circuit 62 and a clock for generating a frequency switching signal for controlling switching between the first and second frequencies, which are controlled by mode signals from the video selecting circuit 15. It has a frequency control circuit 64, a horizontal scan start control circuit 62, and a clock stop control circuit 66 which is controlled by a mode signal and generates a prohibition signal for temporarily stopping the horizontal scan clock signal CPH.

When the display mode based on the mode signal is a full display mode or a two-screen display mode, the first frequency is a sampling frequency corresponding to the full display mode,
The second frequency is a sampling frequency corresponding to the two-screen display mode. The frequency switching signal selects the first frequency in the full display mode, selects the first frequency in the horizontal blanking period of the video signal having the aspect ratio of 3: 4 in the two-screen display mode, and performs one horizontal scan of the video signal. The second frequency is selected in a period excluding the horizontal blanking period from the period. The prohibition signal is not generated in the full display mode, but is generated corresponding to the frequency transition period of the horizontal scanning clock signal CPH in the two-screen display mode. That is, in the horizontal scanning clock signal generation circuit 65, the frequency of the horizontal scanning clock signal CPH is switched according to the frequency switching signal during the duration of the inhibition signal. At this time, the phase of the horizontal scanning clock signal CPH is appropriately adjusted by the phase control signal from the horizontal scanning start control circuit 62.

The vertical scanning control circuit 71 includes a vertical scanning start control circuit 72, a thinning scanning control circuit 73, a vertical scanning clock signal generation circuit 74, and a gate output control signal generation circuit 75.
And generates a vertical scanning start signal STV in synchronization with the horizontal scanning start signal STH for each frame period based on the mode signal from the video selection circuit 15 and the vertical timing signal from the vertical timing generation circuit 57, A vertical scanning clock signal CPV is generated for each horizontal scanning period and supplied to the vertical scanning circuit 21 as a control signal.

In the first display method, the thinning-out scanning control circuit 73 controls the vertical scanning clock signal generating circuit 74 based on the mode signal from the video selection circuit 15 so that the vertical scanning clock signal CPV is continuously generated. The output of the vertical scanning circuit 21 to the scanning signal line is controlled so as not to be inhibited by the gate output control signal GOE generated by the gate output control signal generation circuit 75.

On the other hand, as one method of displaying an image in the effective display area while maintaining an aspect ratio of 9:16 on a flat display device having an effective display area having an aspect ratio of 3: 4, for example, The display area is divided into a first area having an aspect ratio of 9:16 and a second area obtained by removing the first area from the effective display area, and a video signal having an aspect ratio of 9:16 to be displayed in the first area is 1 There is known a method of performing thinning-out scanning during a period excluding a vertical blanking period from a vertical scanning period, and scanning a video signal to be displayed in a second area during a vertical blanking period.

This display method is a display method for displaying video signals having different aspect ratios by changing only the control of the vertical scanning (hereinafter, the second display method). As a conventional example of such scanning control, for example, a display device disclosed in Japanese Patent Application Laid-Open No. 3-44178 is known.

Next, the second display method will be described.
FIG. 10 is a timing chart showing an example of the operation of thinning-out scanning control in which one of seven scanning lines is thinned out.

The clock frequency control circuit 64 shown in FIG.
The clock stop control circuit 66 is controlled to perform the same operation as the full display mode by a mode signal indicating the thinned display mode supplied from the video selection circuit 15.

The vertical scanning start control circuit 72 synchronizes with the horizontal scanning start signal STH for each frame period based on the mode signal and the vertical timing signal from the vertical timing generation circuit 57, and outputs the vertical scanning start signal shown in FIG. STV
Occurs.

When the mode signal supplied from the video selecting circuit 15 is the thinning-scan display mode, the thinning-scanning control circuit 73 controls the field information based on the vertical timing signal and the signal supplied from the vertical-scanning start control circuit 72. According to the timing information of the vertical scanning start signal STV, the phase of the thinning control signal set to be periodically generated in advance is reset to generate a thinning scanning control signal,
It is supplied to a vertical scanning clock signal generation circuit 74 and a gate output control signal generation circuit 75.

The vertical scanning clock signal generating circuit 74 is shown in FIG.
As shown in FIG.
In synchronization with the vertical scanning clock signal CPV. Further, the gate output control signal generation circuit 75 generates the gate output control signal GOE based on the vertical timing signal from the vertical timing generation circuit 57 so as not to output the scanning signal to the scanning line 33 during the period W.

The scanning signals G1, G2, G3,.
G9 is a signal supplied from the vertical scanning circuit 21 to the scanning line 33. As shown in FIG. 10, the shift operation of the scanning signal is stopped during the period W and the scanning signal is not output, so that the period W is not output. Are thinned out.

[0041]

A flat display device such as a current liquid crystal TV or a car navigation system has a display panel for displaying an NTSC video image having about 485 effective scanning lines. About 240
This prevents a decrease in contrast due to an increase in scanning lines. However, in some flat display devices, the size of the display panel is increased, and in such a device, the number of scanning lines is reduced, so that flickering of scanning lines such as line flicker is easily noticeable. There was a problem.

Also, as in the case where an image is displayed on a flat display device having an effective display area having an aspect ratio of 3: 4 while maintaining an aspect ratio of 9:16, the number of scanning lines of the display panel is different. In the vertical scanning line conversion processing when displaying the video signal of the effective scanning lines on the screen, when the processing of thinning the scanning lines and the processing of simultaneously scanning a plurality of scanning lines are used, the scanning control processing is switched off. There is a problem in that discontinuity of the image occurs near the boundary where the image changes.

The present invention has been made in order to solve the above-described problems. When two or more different scanning control processes are switched during a vertical scanning period, image discontinuity does not occur. Further, it is an object of the present invention to provide a flat display device in which flickering of scanning lines such as line flicker is not noticeable even when a display panel is enlarged.

[0044]

In order to achieve the above object, a flat panel display according to the present invention comprises: a display panel having a plurality of horizontal pixel lines including a plurality of display pixels;
A horizontal scanning circuit that supplies a data signal corresponding to a video signal to each display pixel of each horizontal pixel line, a vertical scanning circuit that sequentially supplies a scanning signal to the horizontal pixel line, a horizontal scanning clock signal and a A horizontal scanning control circuit that supplies a horizontal scanning start signal; and a vertical scanning clock signal, a vertical scanning control circuit that supplies a vertical scanning start signal and a gate output control signal to the vertical scanning circuit. Vertical scanning clock generating means for generating at least two types of vertical scanning clock signals each having an integral multiple of a horizontal scanning frequency synchronized with a horizontal scanning period; and a plurality of vertical scanning clock signals generated by the vertical scanning clock generating means. And a clock selecting means for selecting a signal so as to stop the clock, or a specific period. A gate output control unit that controls supply of a scanning signal to a specific scanning line; and a scanning line control unit that controls the vertical scanning clock generation unit, a clock selection unit, and a gate output control unit. Selecting means for selecting either the first scanning control comprising the first operation cycle or the second scanning control comprising the second operation cycle based on a preset cycle value; Scanning control signal switching means for switching the first scanning control consisting of the first operation cycle selected by the above to the second scanning control consisting of the second operation cycle based on an externally input screen display mode signal. Controlling the switching of the two scanning controls by the scanning control signal switching means so as to be switched at a timing of a periodic interval in one of the scanning controls. And it features.

In the flat display device having the above configuration,
For example, by switching between two or more different scanning control processes during the vertical scanning period, it is possible to display an enlarged or reduced image such as a non-linear zoom. In this case, since the scanning line processing near the boundary where the scanning control processing is switched does not differ from the scanning line processing displayed on the display panel, there is no discontinuity of the image.

Further, at present, a display panel in which a decrease in contrast is not a problem compared to the conventional display panel has been developed.
For example, the necessity of reducing the number of scanning lines of a display panel for displaying an NTSC video image having approximately 485 effective scanning lines to approximately 240 lines is reduced, and a scanning line such as a line flicker is used in a large-sized display panel. It is desired to increase the number of scanning lines in order to prevent flicker from being noticeable and to improve image quality.

For example, when the number of scanning lines of the display panel is set to 480, the vertical resolution is improved by performing two-line simultaneous scanning by shifting one line between the odd field and the even field in consideration of the interlaced scanning of the video signal. I do.

A case where a video signal having 525 scanning lines (about 485 effective scanning lines) and a video signal having 625 scanning lines (about 576 effective scanning lines) are displayed on a display panel. Considering that, the ratio of the number of effective scanning lines is 485: 576 =
1: 1.19, but the ratio of integers close to this ratio is 6:
7 = 1: 1.17 or 5: 6 = 1: 1.20,
Assuming that the number of scanning lines of the display panel is 1440, for example, a video signal having 525 scanning lines (about 485 effective scanning lines) is obtained by shifting the multiplex scanning for simultaneously scanning 6 lines by 3 lines in odd fields and even fields. By doing so, almost the entire effective scanning line area can be displayed with improved vertical resolution, and a video signal having 625 scanning lines (approximately 576 effective scanning lines) can be multiplexed by simultaneously scanning 5 lines. Scans 2 or 3 in odd and even fields
By shifting the lines, it is possible to display almost the entire effective scanning line with improved vertical resolution.

Further, as described above, as the number of scanning lines increases, the enlargement / reduction display of an image such as a nonlinear zoom can be performed finely.

[0050]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a flat panel display according to the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram showing a specific example of the timing generation circuit of the flat panel display according to this embodiment. Note that the basic configuration of the flat panel display device is the same as that in FIG. 8, and the configuration of the timing generation circuit includes some equivalent parts. Here, the same portions as those of the configuration of the conventional example shown in FIG. 9 are denoted by the same reference numerals, and the description of the operation will be omitted except for particularly different points.

The clock frequency control circuit 64 and the clock stop control circuit 66 are controlled by a mode signal supplied from the video selection circuit 15, and receive a horizontal scanning clock signal CPH.
Is controlled to change the frequency.

The vertical scanning control circuit 71 has a vertical scanning start control circuit 72, a scanning control circuit 76, a vertical scanning clock signal generation circuit 74, and a gate output control signal generation circuit 75. Based on the vertical timing signal from the vertical timing generation circuit 57, the vertical scanning start signal STV and the vertical scanning clock signal C are synchronized with the horizontal scanning start signal STH for each frame period.
A PV and a gate output control signal GOE are generated and supplied to the vertical scanning circuit 21 as control signals.

The vertical scanning control circuit 76 controls the sequential scanning in the full display mode and the two-screen display mode in accordance with the mode signal indicating the display mode, and performs the thinning-out scanning control and the simultaneous multi-line control in the vertical compression and enlargement display modes, respectively. Performs scanning control.

In the sequential scanning control, the vertical scanning clock signal generation circuit 74 is controlled so that the vertical scanning clock signal CPV is generated in synchronization with the horizontal scanning start signal STH, and the vertical scanning circuit 21 is controlled by the gate output control signal GOE.
The gate output control signal generation circuit 75 is controlled so that the supply of signals to the scanning lines 33 stops in the order in which the scanning lines 33 are arranged.

In the thinning scanning control, the field information based on the vertical timing signal and the vertical scanning start control circuit 7
2, the phase of the thinning control signal set in advance to be periodically generated is reset based on the timing information of the vertical scanning start signal STV based on the signal supplied from the second scanning signal, and the thinning scanning control signal CON1 is generated. During this period, the gate output control signal generation circuit 75 is controlled so as to prohibit the supply of the signal to the scanning line 33, and the generation of the vertical scanning clock signal CPV is stopped, and in synchronization with the horizontal scanning start signal STH outside the thinning scanning period. The vertical scanning clock signal generation circuit 74 is controlled so as to generate the vertical scanning clock signal CPV.

In the simultaneous scanning control for a plurality of lines, a multiplex set in advance to be periodically generated based on a vertical timing signal and timing information of a vertical scanning start signal STV based on a signal supplied from the vertical scanning start control circuit 72. The phase of the line simultaneous scanning control signal is reset to generate the multiple line simultaneous scanning control signal CON2.
The gate output control signal generation circuit 75 is controlled so as to simultaneously supply signals to the vertical scanning clock signal generation circuit 74, and the vertical scanning clock signal generation circuit 74 is controlled so as to switch the frequency of the vertical scanning clock signal CPV only during the same period as the multiple line simultaneous scanning period.

For simplicity of description, the sequential scanning control is for scanning one scanning line at a time, the thinning-out scanning control is scanning for thinning out one of seven scanning lines of a video signal, and simultaneous scanning for a plurality of lines. The scanning control is to scan two adjacent scanning lines simultaneously, and the configuration and operation of each unit will be described in further detail.

FIG. 2 shows a vertical scanning clock signal generation circuit 7.
FIG. 3 is a timing chart for explaining the operation of the vertical scanning clock signal generation circuit 74.

This vertical scanning clock signal generating circuit 74
Has a first clock generation circuit 81, a second clock generation circuit 82, and a selection circuit 83. The first clock generation circuit 81 generates a first vertical clock signal CK1 having the same frequency as the horizontal scanning frequency synchronized with the horizontal scanning start signal STH based on the vertical timing signal supplied from the vertical timing generation circuit 57. It is generated and supplied to the selection circuit 83. Similarly, the second clock generation circuit 82
Generates a second vertical clock signal CK2 having a frequency twice as high as the horizontal scanning frequency synchronized with the horizontal scanning start signal STH based on the vertical timing signal supplied from the vertical timing generating circuit 57. To supply.

The selection circuit 83 is controlled to generate a vertical scanning clock signal CPV supplied to the vertical scanning circuit 21 in synchronization with the vertical timing signal supplied from the vertical timing generation circuit 57. This control is based on the simultaneous scanning control signal C for plural lines supplied from the vertical scanning control circuit 76.
ON2 to select either the first vertical clock signal CK1 or the second vertical clock signal CK2, and control to stop the clock by the thinning-out scanning control signal CON1 supplied from the vertical scanning control circuit 76. Consists of

That is, the vertical scanning clock signal generation circuit 74 stops the vertical scanning clock signal CPV during the period W and the vertical scanning clock signal CPV having a frequency that is an integral multiple of the horizontal scanning frequency during the period V, as shown in FIG. Occurs.

FIG. 4 is a timing chart for explaining the operation of the sequential scanning control, the thinning-out scanning control, and the simultaneous scanning control of a plurality of lines by the scanning control circuit 76.

The vertical scanning start control circuit 72 controls the horizontal scanning start signal S for each frame period based on the mode signal and the vertical timing signal from the vertical timing generation circuit 57.
In synchronization with TH, a vertical scanning start signal STV shown in FIG. 4 having a width in which three adjacent scanning lines are simultaneously scanned is generated, and the timing information of the vertical scanning start signal STV is output to the scanning control circuit 76 and the gate output. Control signal generation circuit 75
To supply.

The scanning control circuit 76 includes the timing information of the vertical scanning start signal STV supplied from the vertical scanning start control circuit 72, the mode signal supplied from the video selection circuit 15, and the vertical signal supplied from the vertical timing generation circuit 57. Thinning-out scanning control signal CON1 based on the timing signal
And a multiple line simultaneous scanning control signal CON2, which are supplied to a vertical scanning clock signal generating circuit 74 and a gate output control signal generating circuit 75.

The gate output control signal generation circuit 75 receives the gate output control signal GO based on the timing information of the vertical scan start signal STV supplied from the vertical scan start control circuit 72.
Initialization of the E1, GOE2 and GOE3 signals is performed,
The thinning-out scanning control signal C supplied from the scanning control circuit 76
Gate output control signals GOE1, GOE2, and GOE based on ON1, the multiple line simultaneous scanning control signal CON2, and the vertical timing signal from the vertical timing generation circuit 57.
The three signals are generated and supplied to the vertical scanning circuit 21. And
The gate output control signals GOE1, GOE2, GOE3 are used in response to the gate output control signals GOE1, GOE2, GOE.
3 corresponding to the scanning lines G 3n and G 3n +
1, the output period from the vertical scanning circuit 21 to G 3n + 2 (n = 1, 2, 3,...) Is controlled.

That is, the operations of the sequential scanning control, the thinning-out scanning control, and the multiple-line simultaneous scanning control by the scanning control circuit 76 are as follows.

When performing the sequential scanning, both the simultaneous scanning control signal CON2 and the thinning-out scanning control signal CON1 are set to the H level, and are synchronized with the horizontal scanning start signal STH in a period excluding the periods W and V in FIG. And controls the vertical scanning clock signal generation circuit 74 to generate the vertical scanning clock signal CPV, and outputs the gate output control signal GO.
The scanning signal lines G1 and G1 are provided by E1, GOE2 and GOE3.
The gate output control signal generation circuit 75 is controlled such that 2, G3,... Are periods other than the period W and the period V in FIG.

When performing the thinning-out scanning, the simultaneous scanning control signal CON2 for a plurality of lines is set to H level, the initial setting of the thinning-out scanning control signal CON1 is performed by the field information based on the vertical timing signal and the vertical scanning start control circuit 7.
This is performed based on the timing information of the vertical scanning start signal STV based on the signal supplied from the signal 2, and is generated so as to be at the L level at a preset cycle after the initial setting. Thus, the vertical scanning clock signal generation circuit 74 is controlled so as to stop the generation of the vertical scanning clock signal CPV in the period W, and the scanning signals G1, G2, G3 are controlled during the period W by the gate output control signals GOE1-3. ,... Are not supplied, the gate output control signal generation circuit 75 is controlled. In this way, during the period W, the shift operation of the scanning signal is stopped and the scanning signal is not output, so that the scanning line of the video signal corresponding to the period W is thinned out, and the image is compressed in the vertical direction.

Further, when performing simultaneous scanning of a plurality of lines,
The thinning-out scanning control signal CON1 is set to the H level, and the initial setting of the multiple-line simultaneous scanning control signal CON2 is initialized by the field information by the vertical timing signal and the vertical scanning start signal S by the signal supplied from the vertical scanning start control circuit 72.
This is performed based on the TV timing information, and is generated so as to be at the L level at a preset cycle after the initial setting, so that the frequency is twice the horizontal scanning frequency synchronized with the horizontal scanning start signal STH in the period V. The vertical scanning clock signal generation circuit 74 is controlled so as to generate the vertical scanning clock signal CPV, and the gate output control signals GOE1 to GOE1.
.. Controls the gate output control signal generation circuit 75 so that the scanning signal lines G1, G2, G3,... Are supplied with a scanning signal simultaneously to two adjacent scanning lines during the period V in FIG. By scanning two adjacent scanning lines simultaneously during the period V, the image of the video signal corresponding to the period V is extended in the vertical direction.

FIG. 5 is a circuit diagram showing an embodiment of the scanning control circuit 76.

The scanning control circuit 76 includes a vertical display mode signal generation circuit 91, a scanning control signal selection switching circuit 92, a sampling circuit 96, a scanning control signal generation circuit 97,
It has a count value generation circuit 100 and a count circuit 101.

The vertical display mode signal generation circuit 91 supplies the timing information of the vertical scanning start signal STV supplied from the vertical scanning start control circuit 72, the mode signal supplied from the video selection circuit 15 and the vertical timing generation circuit 57. A vertical display mode signal is generated based on the vertical timing signal and supplied to the sampling circuit 96 and the count value generation circuit 100.

The count value generation circuit 100 selects one from a plurality of preset cycle values related to the cycle in which the count circuit 101 circulates based on the vertical display mode signal, and supplies it to the count circuit 101. This cycle value is set to 0 when the vertical display mode signal is a signal indicating sequential scanning.

The counting circuit 101 generates a coincidence signal by detecting that the count value of the down counter circuit is 0, and a down counter circuit 103 for counting based on the vertical timing signal supplied from the vertical timing generation circuit 57. And a comparison circuit 102, which outputs a count signal to the scanning control signal generation circuit 97 and a coincidence signal to the sampling circuit 96.
To supply. The down counter circuit 103 is a comparison circuit 1
02, the count value generating circuit 1
The cycle value supplied from 00 is read as a new count value, and the value from the cycle value to 0 is circulated.

The scanning control signal generating circuit 97 includes a counting circuit 10
A scanning control signal selection switching circuit including a first decoding circuit for generating a first timing signal from a count value signal supplied from the first and a second decoding circuit for generating a second timing signal; 92.

The sampling circuit 96 samples the vertical display mode signal supplied from the vertical display mode signal generation circuit 91 based on the coincidence signal supplied from the counting circuit 101 and the vertical timing signal supplied from the vertical timing generation circuit 57. And the scanning control signal selection switching circuit 92
To supply.

The scanning control signal selection switching circuit 92 has a detection circuit 93, a first prohibition circuit 94, and a second prohibition circuit 95. The detection circuit 93 uses the sampled vertical display mode signal supplied from the sampling circuit 96 to
A first display period signal indicating a period in which thinning scanning is performed and a second display period signal indicating a period in which simultaneous scanning of a plurality of lines are performed are detected and supplied to a first inhibition circuit 94 and a second inhibition circuit 95, respectively. . The first prohibiting circuit 94 uses the first display period signal as the first timing signal supplied from the scanning control signal generating circuit 97 in the thinning display period, and in the other periods, inhibits the thinning scanning in the other periods. The signal CON1 is generated and supplied to the vertical scanning clock signal generation circuit 74 and the gate output control signal generation circuit 75. Similarly, the second prohibition circuit 95 uses the second display period signal as a second timing signal supplied from the scan control signal generation circuit 97 during a period in which a plurality of lines are simultaneously scanned, and a plurality of signals in other periods. A multiple line simultaneous scanning control signal CON2 for inhibiting simultaneous line scanning is generated and supplied to a vertical scanning clock signal generation circuit 74 and a gate output control signal generation circuit 75.

According to the above configuration, the video selection circuit 15
The mode signal supplied from is switched during the vertical scanning period, and an image by different scanning control is displayed on the display panel, or the vertical display mode signal generation circuit 91 previously displays a combination of images by different scanning control on the display panel. When a vertical display mode signal is generated for display, the count value generating circuit 1
By using the down counter circuit 103 that reads in the cycle value supplied from 00 as a new count value, the switching of the count value signal can be synchronized with the count value generation circuit 100 itself.

When the first and second timing signals generated by the first and second decoding circuits 98 and 99 of the scanning control signal generating circuit 97 have different timings, the thinning scanning is performed. A vertical display mode signal is sampled by a sampling circuit 96 to a detection circuit 93 that generates a first display period signal and a second display period signal that limit the output periods of the control signal CON1 and the multiple line simultaneous scanning control signal CON2, respectively. The first display period signal and the second display period signal can be synchronized with the count value generation circuit 100 itself.

Therefore, in the above configuration, when an image is displayed by different scanning control, the switching does not occur at a period other than the operation period of the count value generation circuit 100. In addition, when the vertical display mode signal is a signal indicating sequential scanning, by setting the cycle value to 0, it is possible to switch to another scanning control at any timing.

FIG. 6 is a circuit diagram showing another embodiment of the scanning control circuit 76. However, the description of FIG. 6 is omitted except for the points different from FIG.

The vertical display mode signal generation circuit 91 supplies the timing information of the vertical scanning start signal STV supplied from the vertical scanning start control circuit 72, the mode signal supplied from the video selection circuit 15 and the vertical timing generation circuit 57. A vertical display mode signal is generated based on the vertical timing signal and supplied to the detection circuit 93 and the count value generation circuit 100 of the scanning control signal selection switching circuit 92.

The first decoding circuit 98 of the scanning control signal generating circuit 97 generates a timing signal from the count value signal supplied from the counting circuit 101, and outputs the timing signal to the first inhibit circuit 94 of the scanning control signal selection switching circuit 92. The signal is supplied to the second inhibition circuit 95.

According to the above-described configuration, the first inhibition circuit 9
4 and the second prohibition circuit 95 have the same timing signal, so that the vertical display mode signal supplied via the detection circuit 93 is not sampled by the sampling circuit 96 as shown in FIG. It can be synchronized with itself.

FIG. 7 is a circuit diagram showing still another embodiment of the scanning control circuit 76. In FIG. Also in FIG. 7, the description is omitted except for the points different from FIG.

The vertical display mode signal generation circuit 91 supplies the timing information of the vertical scanning start signal STV supplied from the vertical scanning start control circuit 72, the mode signal supplied from the video selection circuit 15, and the vertical timing generation circuit 57. A vertical display mode signal is generated on the basis of the vertical timing signal supplied to the sampling circuit 96 and the counting circuit 10.
Feed to 1.

The sampling circuit 96 includes a counting circuit 101
The vertical display mode signal supplied from the vertical display mode signal generation circuit 91 is sampled based on the reset signal supplied from the It is supplied to the count value generating circuit 100.

The count value generating circuit 100 includes a counting circuit 101
The sampling circuit 96 calculates a cycle value related to the cycle of
Is generated based on the signal supplied from the
To supply.

The counting circuit 101 counts up based on the vertical timing signal supplied from the vertical timing generation circuit 57, the count value of the up counter circuit, and the period value supplied from the count value generation circuit 100. And a comparison circuit 10 which compares the two to generate a coincidence signal
2 and a first reset signal composed of the coincidence signal and a second reset signal generated when the vertical display mode signal supplied from the vertical display mode signal generation circuit 91 is a signal indicating sequential scanning, and then output. And a reset circuit 104 for supplying a count signal to the scanning control signal generating circuit 97 and a coincidence signal to the sampling circuit 96. The up counter circuit 103 circulates a value from 0 to a cycle value in response to a reset signal supplied from the reset circuit 104. If the vertical display mode signal is a specific signal, it is held at 0.

According to the above-described configuration, the counter circuit constituting the counting circuit 101 is a down counter circuit 103
, The means for configuring the counting circuit 101 is different, and the vertical display mode signal generation circuit 91, the sampling circuit 96, the scanning control signal selection switching circuit 92, the count value generation circuit 100 5 and the basic functions are the same as those in FIG.

The counting circuit 101 shown in FIGS. 5 and 6 detects that the count value of the down counter circuit is 0 by using the comparison circuit 102 as the coincidence signal generating means. The function is not limited to the comparison circuit 102 as long as it is a function of detecting that the scanning control signal is detected by the first decoding circuit 98 and the like constituting the scanning control signal generation circuit 97.

In the above-described embodiment, the thinning-out scanning control signal CON1 is obtained from the first timing signal generated by the first decoding circuit 98. However, the current standard TV using the interlaced scanning method (interlace) is used. In the reduced display in the vertical direction of the signal, in order to reduce the deterioration of the resolution, it is possible to adopt a configuration in which different count values are generated in the odd field and the even field, respectively.

Also, a plurality of lines simultaneous scanning control signal CON
2 also has a configuration obtained from the second timing signal generated by the second decoding circuit 99. This also controls a display panel having twice or more the number of scanning lines of the video signal. In consideration of the interlaced scanning of the video signal, different odd-field and even-field fields are used so that the simultaneous scanning of multiple lines is shifted by about half the number of scanning lines that are scanned simultaneously in the odd and even fields. It can be configured to generate from different count values.

Further, in the case where the phase of the scanning control is changed between the odd field and the even field without using the sampling circuit 96 shown in FIG.
Reference numeral 7 denotes the field information of the vertical timing signal supplied from the vertical timing generation circuit 57, the timing information of the vertical scanning start signal STV supplied from the vertical scanning start control circuit 72, and the mode signal supplied from the video selection circuit 15. A vertical display mode signal is generated based on the first control signal, and the first among a plurality of decode circuits constituting the scan control signal
By switching between the timing signal generated by the decoding circuit 98 of this embodiment and the timing signal generated by another decoding circuit based on the vertical display mode signal, the same effect as in the other configurations can be obtained.

[0096]

As described above, according to the flat display device of the present invention, when two or more different scanning control processes are switched during the vertical scanning period, the scanning near the boundary where the scanning control process is switched is performed. Since the line processing does not differ from the scanning line processing displayed on the display panel, no image discontinuity occurs. Further, even when the number of scanning lines is reduced due to an increase in size of the display panel, flickering of scanning lines such as line flicker can be made inconspicuous.

Further, even when two or more different scan control processes are used for vertical aspect ratio conversion, discontinuity of the image does not occur. A possible flat display device can be realized.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a specific example of a timing generation circuit of a flat panel display according to an embodiment.

FIG. 2 is a circuit diagram showing an embodiment of the vertical scanning clock signal generation circuit of FIG. 1;

FIG. 3 is a timing chart for explaining the operation of the vertical scanning clock signal generation circuit of FIG. 2;

FIG. 4 is a timing chart for explaining operations of sequential scanning control, thinning scanning control, and multiple line simultaneous scanning control by the scanning control circuit of FIG. 2;

FIG. 5 is a circuit configuration diagram showing an embodiment of a scanning control circuit.

FIG. 6 is a circuit diagram showing another embodiment of the scanning control circuit.

FIG. 7 is a circuit configuration diagram showing still another embodiment of the scanning control circuit.

FIG. 8 is a circuit diagram showing a specific example of a conventional flat display device.

FIG. 9 is a circuit configuration diagram showing a specific example of the timing generation circuit of FIG. 8;

FIG. 10 is a timing chart showing an operation example of thinning-out scanning control in which one of seven scanning lines is thinned out.

[Explanation of symbols]

 Reference Signs List 10 liquid crystal display device 11 panel control unit 14 timing generation circuit 15 video selection circuit 19 video signal processing circuit 20 horizontal scanning circuit 21 vertical scanning circuit 22 level inversion circuit 23 common voltage generation circuit 30 liquid crystal display panel 31 pixel electrode 32 switching element 33 scanning Line 34 data signal line 51 video processing control circuit 52 PLL circuit 53 voltage controlled oscillator 54 loop filter 55 phase comparator 56 counter 57 vertical timing generation circuit 61 horizontal scanning control circuit 71 vertical scanning control circuit 72 vertical scanning start control circuit 74 vertical scanning Clock signal generation circuit 75 Gate output control signal generation circuit 76 Scan control circuit 80 Polarity inversion signal generation circuit 81 First clock generation circuit 82 Second clock generation circuit 83 Selection circuit 91 Vertical display mode signal generation circuit 92 Scanning control signal selection switching circuit 93 Detection circuit 94 First inhibition circuit 95 Second inhibition circuit 96 Sampling circuit 97 Scanning control signal generation circuit 100 Count value generation circuit 101 Counting circuit 102 Comparison circuit 103 Down counter circuit 104 Reset circuit 105 Up Counter circuit

 ──────────────────────────────────────────────────続 き Continuing on the front page F term (reference) 2H093 NA16 NA43 NA47 NC09 NC21 NC27 ND10 ND60 5C006 AA01 AA11 AB01 AC11 AC24 AF44 AF45 AF47 BB16 BC03 BC11 FA04 FA05 FA23 5C080 AA10 BB06 DD02 DD06 EE26 EE29 FF11 GG12 GG08 GG09

Claims (9)

[Claims] A display panel provided with a plurality of horizontal pixel lines each including a plurality of display pixels; a horizontal scanning circuit for supplying a data signal corresponding to a video signal to each display pixel of each horizontal pixel line; A vertical scanning circuit for sequentially supplying a scanning signal to a line, a horizontal scanning control circuit for supplying a horizontal scanning clock signal and a horizontal scanning start signal to the horizontal scanning circuit, a vertical scanning clock signal and a vertical scanning start signal to the vertical scanning circuit And a vertical scanning control circuit for supplying a gate output control signal, wherein the vertical scanning control circuit generates at least two types of vertical scanning clock signals consisting of an integral multiple of a horizontal scanning frequency synchronized with a horizontal scanning period. In the case where the vertical scanning clock generating means and the vertical scanning clock signal generated by the vertical scanning clock generating means comprise a plurality of Or a clock selection means for selecting a signal to stop the clock, a gate output control means for controlling supply of a scanning signal to a specific scanning line in a specific period, the vertical scanning clock generating means, and a clock selection means And a scanning line control means for controlling a gate output control means, wherein the scanning line control means is either a first scanning control comprising a first operation cycle or a second scanning control comprising a second operation cycle. And a first scanning control comprising a first operation cycle selected by the selecting means, based on a screen display mode signal input from the outside. Scanning control signal switching means for switching to a second scanning control comprising a second operation cycle, wherein switching of the two scanning controls by the scanning control signal switching means is performed by: Flat panel display and controls so switched at the timing of the periodic interval in displacement or the other of the scan control. 2. The scanning line control means according to claim 1, wherein the first or second scanning control is performed in one horizontal scanning cycle such that scanning of one line or multiple scanning for simultaneously scanning at least two or more scanning lines is continued. Has the same operation cycle as described above, and is one of the sequential scanning controls including a control in which the supply of the scanning signal is sequentially stopped in the order in which the scanning lines are arranged. The second or first scanning control includes: A second sequential scan control that is the same as or different from the first sequential scan control that is the sequential scan control, and a multiplex scan that simultaneously scans at least two or more scan lines or a thinning scan that thins out at least one scan line A scan control in which the combination of the controls is defined as a basic cycle, and the basic cycle is controlled so as to be repeated. 2. The flat display device according to claim 1, wherein the switching is performed at a timing of an operation cycle interval of the progressive scanning control. 3. The scanning line control means, wherein the first and second scanning controls are performed in one horizontal scanning cycle such that one-line scanning or multiplex scanning for simultaneously scanning at least two or more scanning lines is continued. A first sequential scan control, which is one of the sequential scan controls that have the same operation cycle as that of the scan lines and is configured to sequentially stop the supply of the scan signal in the order in which the scan lines are arranged, and at least two lines or more. Scanning control in which a basic cycle is a combination of multiple scanning for simultaneously scanning the scanning lines or thinning-out scanning control for thinning out at least one scanning line, wherein the basic cycle is controlled to be repeated. The switching control from the first scanning control to the second scanning control by the means is controlled so as to be switched at a timing of a first operation cycle of the first scanning control. Flat display device according to claim 1, characterized in that. 4. The scanning line control means includes: a counting means for counting a predetermined count value; a means for controlling the counting means to circulate at a cycle value consisting of the basic cycle; and the first sequential scan control. In the first or second scanning control, the counting value of the counting means is set to a preset cycle value, and the operation of the scanning control switching means is stopped. 3. The flat display device according to claim 2, wherein the switching is performed at a timing of an operation cycle interval of the first progressive scanning control. 5. At least two or more operation cycles, or
Scanning line control means for switching between different scan controls; a counting means for counting a predetermined count value; a control means for controlling the counting means so as to cycle in each operation cycle; and a counting means for selecting a count value of the counting means. Numerical value selecting means, wherein the selection of the multiple scanning or the thinning-out scanning by the count value selecting means is generated from the same count value regardless of the difference in the operation cycle, between scan line controls having different cycles, or 4. The flat display device according to claim 3, wherein a transition between different scan line controls of the scan control is not at a cycle interval other than the operation cycle interval of the counting means. 6. A display signal comprising an interlace signal is supplied to a data signal line drive circuit, and includes a thinning-out scanning control in which an operation frequency in an odd field is equal in an even field and a phase in an odd field is different in an even field. Scanning line control means for switching scan line control including at least two or more operation cycles; counting means for counting a predetermined count value; means for controlling the counting means so as to cycle in each operation cycle; Means for selecting a count value of the means, and selecting at least one of an odd field and an even field by the count value selecting means to select the thinning-out scanning and the other scanning by the difference in the operation cycle. Regardless of the fact that they are generated from the same count value,
It is characterized in that a transition between scanning line controls having different periods in at least one of the odd field and the even field or a switching between scanning line controls having different scanning control is not a period interval other than the operation period interval of the counting means. The flat panel display according to claim 3. 7. The scanning control switching means comprises a scanning selection means and a sampling means, and outputs a screen display mode signal input from the outside at an interval of one of a first operation cycle and a second operation cycle. 7. The flat display device according to claim 1, wherein sampling is performed at a timing, and the first scanning control and the second scanning control are switched according to the sampled signal. 8. At least two or more operation cycles, or
Scanning line control means for switching between different scan controls; a counting means for counting a predetermined count value; a means for controlling the counting means so as to cycle in each operation cycle; and a count value for selecting a count value of the counting means. Selecting means for selecting the multiple scanning or the thinning-out scanning by the count value selecting means from the same or different count values irrespective of the difference in the operation cycle. Irrespective of this, by generating from the same count value, it is possible to prevent a transition between scan line controls having different cycles or between scan line controls having different scan controls from being a cycle interval other than the operation cycle interval of the counting means. The flat panel display according to claim 7, wherein: 9. The scanning line control means includes: a counting means for counting a predetermined count value; a means for controlling the counting means so as to cycle in a cycle comprising the basic cycle; and a first sequential scanning control. Means for setting the counting means to a preset count value at the time of the first or second scanning control, and means for stopping the operation, wherein the preset count value and the count value generated by the sampling means are provided. 9. The flat display device according to claim 8, wherein the control is performed such that the switching control by the scanning control switching unit is switched at the timing of the operation cycle interval of the first sequential scanning control.