JP2000232153A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a technique by which an STI can be formed without performing CMP(chemical mechanical polishing) which raises a dishing problem nor requiring any active dummy pattern. SOLUTION: A semiconductor device manufacturing method in which an element isolating area is formed by forming active area isolating grooves 15 into a semiconductor substrate 11 and filling up the grooves 15 with insulating films 18 includes a step of forming a resist film 19 on the insulating films 18 after forming the insulating films 18 on the semiconductor substrate 11 so that the films may fill up the grooves 15, a step of generating data about the positions of patterns in an active area isolated by the element isolating area by directly reading the positions, and a step of forming an opening 20 through the resist film 19 on the active area by exposing and developing the film 19, based on the data. The method also includes a step of selectively removing the insulating films 18 on the active area from the opening 20.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to an STI (Shallow Trench Isolati).
on), the active dummy pattern is not used, and ST is set in accordance with the area ratio of every active region.
The present invention relates to a method for manufacturing a semiconductor device capable of forming I.

[0002]

2. Description of the Related Art A conventional technique for forming an STI (Shallow Trench Isolation) will be described with reference to manufacturing process diagrams shown in FIGS.

As shown in FIG. 5A, a pad oxide film 12 is formed on a silicon substrate 11 by, for example, 10 nm to 20 nm.
It is formed to a thickness of about. Then, the chemical vapor deposition method (C
VD), a silicon nitride film 13 is formed on the pad oxide film 12 to a thickness of, for example, about 150 nm to 200 nm. Next, a resist active pattern 14 made of a resist film is formed on the silicon nitride film 13 by resist coating and lithography technology. Here, the center of the drawing is an isolated active region 11S where an isolated active pattern is formed, and one side thereof is DR.
The other side is the circuit area 11C.

After that, as shown in FIG. 5B, the silicon nitride film 13 and the pad oxide film 12 are patterned by etching, and the resist active pattern 14 [see FIG. 5A] is removed.

Next, using the silicon nitride film 13 as a mask, the silicon substrate 11 is
The trench 15 is formed by etching to about m. This groove 15 is formed by a groove 15D for element isolation in the DRAM area 11D, an element isolation groove 15C in the circuit area 11C, and the silicon substrate 1 in a peripheral area to be an isolated active pattern.
Etching 1 results in grooves 15M and the like for forming isolated active patterns 16.

[0006] Thereafter, as shown in FIG.
A thermal oxide film (not shown) is formed on the inner wall of
An insulating film 18, for example, a high-density plasma CVD film is deposited so as to bury the inside of 5. The above-mentioned HDP film is deposited on the bottom portion of the groove 15 and on the active region without being deposited on the edge portion of the groove 15 because the HDP film is subjected to CVD while being sputtered.

Next, as shown in FIG. 6D, the insulating film 1 is formed by resist coating and lithography.
A resist pattern 31 made of a resist film is formed on the resist pattern 8. The resist pattern 31 is formed, for example, in the circuit region 1
An opening 32 is provided on a wide active area 11W of 1C. Here, a wide active area is an active area as narrow as possible in a range where a mask can be formed, and is not the inversion data of the active pattern itself.

Then, as shown in FIG. 6 (5), the insulating film 18 on the wide active region 11W is removed by using the resist pattern 31 (see FIG. 6 (4)) as an etching mask. After that, the resist pattern 31 is removed. In (5) of FIG. 6, the resist pattern 3
1 shows the state where 1 was removed.

Thereafter, as shown in FIG. 7 (6), the insulating film 18 is polished by chemical mechanical polishing (hereinafter referred to as CMP). At this time, since the ratio of the active region is higher than the ratio of the element isolation region in the DRAM region 11D and the circuit region 11C, even if excessive polishing is performed, the groove 15 is formed by the silicon nitride film 13 serving as a polishing stopper. Although the occurrence of dishing in the buried insulating film 18 is suppressed, there is no problem.
Since the density of the silicon nitride film 13 serving as a polishing stopper is low in the field portion of FIG.
Dishing occurs and becomes concave. Therefore, the portion to be the isolated active pattern 16 protrudes from the surface of the surrounding insulating film 18.

As for the polishing characteristics of the CMP, the polishing selectivity between the insulating film 18 made of a silicon oxide film and the silicon nitride film 13 changes according to the area ratio occupied by the active portion. Specifically, as shown in FIG. 7 (6), in the isolated active pattern 16 in a wide field, the selectivity of the silicon nitride film 13 cannot be obtained, and excessive polishing is performed, and conversely, the area occupied by the active region is reduced. In a region where the ratio is high, a selection ratio with respect to the silicon nitride film 13 can be obtained, so that polishing is difficult to progress.

Thereafter, the silicon nitride film 13 is removed by, for example, wet etching using hot phosphoric acid. As a result, as shown in FIG.
The insulating film 18 in the circuit region 11C is formed so as to protrude from the silicon substrate 11. Further, the pad oxide film 12 (see FIG. 5B) is removed by wet etching using, for example, hydrofluoric acid. At this time, the insulating film 18
Although the upper layer is also etched, the insulating film 18 in the DRAM region 11D and the circuit region 11C is still formed to protrude from the silicon substrate 11.

Then, although not shown, a sacrificial oxide film is formed, ion implantation for forming a well, ion implantation for adjusting a threshold value, and the like are performed. It is removed by the used wet etching. At this time, the upper layer of the insulating film 18 is also etched.

As a result, as shown in FIG.
The active region (silicon substrate 11) of the RAM region 11D and the circuit region 11C is formed lower than the surrounding insulating film 18, and the step between the active region (silicon substrate 11) and the field region (insulating film 18) becomes large. On the other hand, the insulating film 18 around the isolated active pattern 16 is formed lower than the isolated active pattern 16,
The steps are small. The insulating film 18 embedded in the groove 15
A recess 19 is formed at the end of the recess.

[0014]

As a characteristic of polishing by CMP, the selectivity between the insulating film made of a silicon oxide film and the silicon nitride film changes according to the area ratio of the active region (silicon substrate). More specifically, as shown in FIG. 7 (6) described in the prior art, in the isolated active pattern 16 existing in a wide field, the selectivity of the silicon nitride film 13 cannot be obtained and excessive polishing is performed. In addition, in a region where the ratio of the area of the active region is high, a selection ratio with respect to the silicon nitride film 13 can be obtained, so that polishing is difficult to proceed.

[0015] For this reason, FIG.
As shown in (7), polishing variations occur, and for example, it is difficult to fabricate an STI in a chip in which a DRAM and a logic are mixed.

In view of this, a technique for forming an active dummy pattern in a wide active area has been proposed. However, it is difficult to generate data required for forming an active dummy pattern, for example, pattern information of an upper layer is required. Has occurred.

[0017]

SUMMARY OF THE INVENTION The present invention is a method for manufacturing a semiconductor device which has been made to solve the above-mentioned problems.

A first method of manufacturing a semiconductor device is a method of manufacturing a semiconductor device in which a groove for isolating an active region is formed in a semiconductor substrate and an element isolation region is formed by embedding an insulating film in the groove. After forming an insulating film on the semiconductor substrate in a state where the groove is buried, a process of forming a resist film on the insulating film and directly reading a pattern position of the active region to obtain data of a pattern position of the active region. The method includes a step of forming, a step of exposing and developing a resist film based on the data to form an opening on the active region, and a step of removing the insulating film on the active region from the opening.

In the first manufacturing method, the data of the pattern position of the active area is created by directly reading the pattern position of the active area on the semiconductor substrate, and the groove is filled based on the data. The resist film formed on the insulating film on the semiconductor substrate is exposed and developed to form an opening on the active region, and the insulating film on the active region is removed from the opening. Only will be selectively removed. Therefore, the insulating film is left only inside the groove.

According to a second method of manufacturing a semiconductor device, there is provided a method of manufacturing a semiconductor device in which a groove for isolating an active region is formed in a semiconductor substrate and an element isolation region is formed by embedding an insulating film in the groove. After forming an insulating film on a semiconductor substrate in a state where the groove is filled, a step of forming a resist film on the insulating film, a step of preparing an information file indicating a pattern position of an active area, and reading from the information file Exposing and developing the resist film based on the information on the pattern position of the active area to form an opening on the active area, and removing the insulating film on the active area from the opening. .

According to the second manufacturing method, an information file indicating the pattern position of the active area is prepared, and the resist film is exposed and developed based on the information on the pattern position of the active area read from the information file, and is developed. After the opening is formed thereon, the insulating film on the active region is removed from the opening, so that only the insulating film on the active region is selectively removed. Therefore, the insulating film is left only inside the groove.

According to a third method of manufacturing a semiconductor device, there is provided a method of manufacturing a semiconductor device in which a groove for isolating an active region is formed in a semiconductor substrate, and an insulating film is embedded in the groove to form an element isolation region. Forming an insulating film on the semiconductor substrate in a state where the groove is buried, forming a resist film on the insulating film, preparing an information file indicating a pattern position of the active region, and pattern position of the active region By reading directly
A step of creating pattern position data in the active area; and a step of exposing and developing a resist film based on the pattern position data obtained by directly reading and the data in the information file to form an opening in the active area. And removing the insulating film on the active region from the opening.

In the third manufacturing method, an information file indicating the pattern position of the active area is prepared, and data on the pattern position of the active area is created by directly reading the pattern position of the active area. Then, the resist film is exposed and developed based on the data of the pattern position and the data of the information file obtained by directly reading, and after forming an opening on the active area by developing,
Since the insulating film on the active region is removed from the opening, only the insulating film on the active region is selectively removed. Therefore, the insulating film is left only inside the groove.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One example of an embodiment according to a first method for manufacturing a semiconductor device of the present invention will be described with reference to FIG. In FIG. 1, manufacturing process diagrams are shown in (1) to (4),
(5) is an explanatory view of a data reading method, and (6) is an explanatory view of exposure.

As shown in FIG. 1A, after a pad oxide film 12 is formed on a semiconductor substrate (for example, a silicon substrate) 11, a silicon nitride film 13 is formed thereon. Next, after patterning the silicon nitride film 13 and the pad oxide film 12 by lithography and etching, a groove (trench) 15 is formed in the semiconductor substrate 11 using the silicon nitride film 13 as a mask. Then, after forming a thermal oxide film (not shown) on the inner wall of the groove 15, the groove 1 is formed.
An insulating film 18, for example, a high-density plasma CVD film is deposited so as to bury the inside of 5. Since the above-mentioned HDP film is deposited on the bottom of the groove 15 and the active region 11A without being deposited on the edge of the groove 15 because the HDP film is subjected to CVD while being sputtered, the edge is inclined in the final shape.

Thereafter, a resist is applied to form a resist film 1
9 is formed.

Next, as shown in FIG. 1 (5), the pattern position of the active region 11A of the semiconductor substrate 11 is
By reading directly, for example by image processing,
The data of the pattern position of the active area 11A is created. For example, the image capturing device that captures the image is scanned, for example, along a path indicated by the arrow A, and the pattern position is read and data (for example, coordinate data) is created. The created data may be temporarily stored in a storage medium (not shown), for example.

Note that reading the pattern position of the active region 11A may be reading the position of the groove 15 formed for forming the element isolation region.

Next, as shown in (6) of FIG. 1, based on the data, a resist formed on the semiconductor substrate 1 by the electron beam E using, for example, an electron beam exposure apparatus (not shown). The film 19 is exposed. Further, the resist film 19 is developed to form an opening 20 in the resist film 19 on the active region 11A, as shown in FIG. As described above, since the electron beam exposure apparatus was used,
The opening 20 can be formed with high precision in the active region 11A.

Next, as shown in FIG. 1B, the insulating film 18 on the active region 11A is removed from the opening 20 by etching using the resist film 19 as an etching mask. At this time, the silicon nitride film 13 serves as an etching stopper. The opening 20
Is formed with high precision by an electron beam exposure apparatus, so that only the insulating film 18 on the active region 11A can be selectively removed.

After that, the resist film 19 is removed.
As a result, as shown in FIG. 1C, the insulating film 18 is buried inside the groove 15, and the insulating film 18 on the active region 11A is removed.

Further, after removing the silicon nitride film 13 and the pad oxide film 12, a pre-oxide film (or a sacrificial oxide film) is formed.
After forming (not shown), various ion implantations are performed, and the pre-oxide film (or sacrificial oxide film) is removed.
Then, as shown in FIG. 1 (4), the surface of the insulating film 18 which becomes the element isolation region and the surface of the active region 11A are almost flattened.

Thereafter, although not shown, a gate insulating film and the like are formed on the surface of the active region (the semiconductor substrate 11 not covered with the insulating film 18), and semiconductor elements such as transistors and capacitors are formed.

In the first manufacturing method, the semiconductor substrate 11
By directly reading the pattern position of the active region, data of the pattern position of the active region is created, and based on the data, the resist 15 formed on the insulating film 18 on the semiconductor substrate 11 with the groove 15 buried. The film 19 is exposed and developed to form an opening 20 on the active area.
Is formed, and the insulating film 18 on the active region is removed from the opening 20, so that only the insulating film 18 on the active region is selectively removed. Therefore, the insulating film 18 is left only inside the groove 15. In this manufacturing method, it is possible to omit the flattening step by CMP which has been conventionally used. Therefore, dishing that has occurred due to CMP does not occur. Therefore, for example, a semiconductor device having an isolated active pattern with a DRAM can be formed on the same substrate. Therefore, the DRAM and the logic element can be mixedly mounted on the same substrate.

Next, an example of a specific manufacturing process according to the above embodiment will be described with reference to FIGS.

First, as shown in FIG. 2A, a pad oxide film 12 is formed on a semiconductor substrate (for example, a silicon substrate) 11.
Is formed to a thickness of, for example, about 10 nm to 20 nm. After that, a silicon nitride film 13 of, eg, 150 nm is formed on the pad oxide film 12 by a chemical vapor deposition method (CVD method).
It is formed to a thickness of about 200 nm.

Next, as shown in FIG. 2B, a resist active pattern 14 made of a resist film is formed on the silicon nitride film 13 by resist coating and lithography techniques. Here, the center of the drawing is an isolated active area 11S, and one side thereof is a DRAM area 1S.
1D, and the other side is a circuit area 11C.

Thereafter, as shown in FIG. 2C, the silicon nitride film 13 and the pad oxide film 12 are patterned by etching, and the resist active pattern 14 [see FIG. 2B] is removed.

Next, as shown in FIG. 3D, using the silicon nitride film 13 as a mask, the semiconductor substrate 11 is etched to a depth of about 300 nm to 400 nm to form a trench (trench) 15. This groove 15 is
Groove 15D for element isolation in region 11D, circuit region 11
A groove 15C for element isolation of C, and a groove 15M for forming an isolated active pattern 16 by etching the semiconductor substrate 11 in a peripheral region to be an isolated active pattern.

Thereafter, as shown in FIG.
A thermal oxide film (not shown) is formed on the inner wall of
An insulating film 18, for example, a high-density plasma CVD film is deposited so as to bury the inside of 5. Since the above-mentioned HDP film is deposited on the bottom of the groove 15 and the active region 11A without being deposited on the edge of the groove 15 because the HDP film is subjected to CVD while being sputtered, the edge is inclined in the final shape.

Thereafter, as shown in FIG. 3 (6), the insulating film 1 is formed by resist coating and lithography.
A resist film 19 is formed on 8.

Next, the pattern position of the active area 11A is created by directly reading the pattern position of the active area by, for example, image processing. For example, an image capturing device (not shown) for capturing an image scans, for example, the surface of the semiconductor substrate 11, reads the pattern position of the active area 11A, and creates data (for example, coordinate data). The created data may be temporarily stored in a storage medium (not shown), for example.

Reading the pattern position of the active area 11A may be reading the position of the groove 15 formed for forming the element isolation area.

Next, based on the data, the resist film 19 is exposed using, for example, an electron beam exposure apparatus (not shown). Further, the resist film 19 is developed to form an opening 20 in the resist film 19 on the active area 11A, thereby exposing the insulating film 18 on the active area 11A. Conventionally, since exposure is performed using an inversion mask,
It is necessary to take the misalignment margin in advance, so
No opening could be made in a narrow area. For example, the misalignment margin needs to have a length of about 0.3 μm from the end of the active region 11A, and the minimum exposure dimension is i
When a line stepper was used, the limit was 0.5 μm. For this reason, the inversion pattern of the active region of 1.1 μm or less could not be generated in the resist film 19. On the other hand, in the manufacturing method of the present invention, since the electron beam exposure apparatus is used, the opening 20 can be formed with high accuracy in the active area 11A.

Next, using the resist film 19 as an etching mask, the active region 1 is opened through the opening 20.
The insulating film 18 on 1A is removed by etching. Since the opening 20 is formed with high accuracy by an electron beam exposure apparatus, only the insulating film 18 on the active region 11A can be selectively removed.

As described above, since the position data of the active area 11A is directly read and the data is used as the drawing data of the electron beam exposure apparatus, it is not necessary to secure a margin for misalignment. The size of the opening 20 on the region 11A can be processed to the same size as the size of the active region 11A. Next, as shown in FIG. 4 (7), the insulating film 18 (see FIG. 3 (6)) formed on the active region 11A is removed by dry etching using the resist film 19 as a mask. FIG. 4 (7) shows a state after the insulating film 18 is removed. After that, the resist film 19 (see FIG. 3 (6)) is removed.

Next, the silicon nitride film 13 is removed by wet etching using, for example, hot phosphoric acid. Subsequently, for example, by wet etching using hydrofluoric acid,
The pad oxide film 12 is removed. As a result, (8) in FIG.
As shown in FIG. 7, the active region 11A is exposed.

Although not shown, after forming the sacrificial oxide film, various ions are implanted, and thereafter the sacrificial oxide film is removed by, for example, wet etching using hydrofluoric acid. By the above wet etching, the pad oxide film 12 is formed.
Each time the sacrificial oxide film is removed, the thickness of the insulating film 18 is reduced, and finally a gate insulating film (not shown) is formed. Then, as shown in FIG. The surface of the silicon substrate 11 on which the insulating film is formed is made flat. For that purpose, it is necessary to set the film thickness of the pad oxide film 12, the sacrificial oxide film, and the like by calculating backward from the wet etching amount. In the present invention, planarization by CMP becomes unnecessary.

Next, an example of an embodiment according to the second manufacturing method of the present invention will be described below.

A second method of manufacturing a semiconductor device is described in FIG.
In the first manufacturing method described above, only the method of creating data used when exposing the resist film 19 is different, and the other manufacturing methods are the same as the first manufacturing method. Therefore, here, a method of creating data will be described. Note that the same components as those described in the first manufacturing method are denoted by the same reference numerals for the components described below, and the description will be given.

A resist film 19 is formed in the same manner as described with reference to FIG. On the other hand, an information file (not shown) indicating the pattern position of the active area of the semiconductor substrate 11 is prepared. The resist film 19 is exposed by using an electron beam exposure device (not shown) based on the information on the pattern position of the active area read from the information file, and further developed to form the resist film 19 on the active area. An opening 20 is formed. Thereafter, as described with reference to FIG.
And the subsequent steps may be performed.

In the second manufacturing method, the semiconductor substrate 11
After an information file indicating the pattern position of the active area is prepared, the resist film 19 is exposed and developed based on the information on the pattern position of the active area read from the information file to form an opening 20 on the active area. , The insulating film 18 on the active region from the opening 20
Is removed, only the insulating film 18 on the active region is selectively removed. Therefore, the insulating film 18 is left only inside the groove 15. Further, as compared with the first manufacturing method, an information file indicating the pattern position of the active area of the semiconductor substrate 11 is prepared in advance, so that the data reading time can be reduced.

Further, in this manufacturing method, it is possible to omit the flattening step by CMP which has been conventionally used.
Therefore, dishing that has occurred due to CMP does not occur. Therefore, for example, a semiconductor device having an isolated active pattern with a DRAM can be formed on the same substrate. Therefore, the DRAM and the logic element can be mixedly mounted on the same substrate.

Next, an example of an embodiment according to the third manufacturing method of the present invention will be described below.

A third method of manufacturing a semiconductor device is described in FIG.
In the first manufacturing method described above, only the method of creating data used when exposing the resist film 19 is different, and the other manufacturing methods are the same as the first manufacturing method. Therefore, here, a method of creating data will be described. Note that the same components as those described in the first manufacturing method are denoted by the same reference numerals for the components described below, and the description will be given.

A resist film 19 is formed in the same manner as described with reference to FIG. On the other hand, an information file (not shown) indicating the pattern position of the active area of the semiconductor substrate 11 is prepared. On the other hand, by directly reading the pattern position of the active area of the semiconductor substrate 11 by, for example, image processing, data of the pattern position of the active area is created. For example, the image capturing device that captures an image is scanned, for example, as indicated by an arrow, the pattern position is read, and data (for example, coordinate data) is created. The created data may be temporarily stored in a storage medium (not shown), for example.

Note that reading the pattern position of the active area may be reading the position of the groove 15 formed for forming the element isolation region.

The resist film 19 is exposed using an electron beam exposure apparatus (not shown) based on the data of the pattern position and the data of the information file obtained by directly reading. At this time, the data of the information file is corrected based on the data of the pattern position of the active area obtained by directly reading, and the opening 20 is formed in the resist film 19 based on the corrected data of the pattern position of the active area.
Is exposed.

Subsequently, the resist film 19 is developed to form an opening 20 in the resist film 19 on the active area. After that, the insulating film 18 on the active area is removed from the opening 20 in the same manner as described with reference to FIG.

In the third manufacturing method, the semiconductor substrate 11
An information file indicating the pattern position of the upper active area is prepared, and the pattern position of the active area of the semiconductor substrate 11 is directly read to create data of the pattern position of the active area. Then, the resist film 19 is exposed based on the data of the pattern position and the data of the information file obtained by directly reading, and further developed to form an opening 20 in the resist film 19 on the active area. After that, the insulating film 18 on the active region is removed from the opening 20, so that only the insulating film 18 on the active region is selectively removed.
Therefore, the insulating film 18 is left only inside the groove 15.

As compared with the first manufacturing method, since an information file indicating the pattern position of the active area of the semiconductor substrate 11 is prepared in advance, the data reading time can be reduced. Furthermore, when compared with the second manufacturing method,
Since the data of the information file is corrected by the directly read data, a dimensional error of the active area (or the groove 15) due to exposure, etching, etc. performed before forming the resist film 19 can be corrected, so that more accurate data can be obtained. Thus, the resist film 19 can be exposed without taking much time.

Further, in this manufacturing method, it is possible to omit the flattening step by CMP which has been conventionally used.
Therefore, dishing that has occurred due to CMP does not occur. Therefore, for example, a semiconductor device having an isolated active pattern with a DRAM can be formed on the same substrate. Therefore, the DRAM and the logic element can be mixedly mounted on the same substrate.

[0063]

As described above, according to the method of manufacturing a semiconductor device of the present invention, only the insulating film on the active region can be selectively removed. Therefore, it is possible to flatten the surface of the semiconductor substrate irrespective of the area ratio of the active region, and it is possible to suppress variations in element characteristics. Moreover, since CMP is not required, it is not necessary to use an active dummy. In addition, when exposing the resist film used for removing and printing the insulating film on the active area, the pattern information of the lower layer is directly used. Therefore, even if there is no mask information such as wells and gates of the upper layer, it is possible to generate an exposure pattern. Becomes possible. Further, since the need for CMP is eliminated, the number of steps can be reduced. In addition, since an active inversion mask is not required, the cost of manufacturing a mask can be reduced.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram showing an example of an embodiment according to a first manufacturing method of the present invention.

FIG. 2 is a manufacturing process diagram showing an example of a specific method for manufacturing a semiconductor device.

FIG. 3 is a manufacturing step diagram (continued) showing an example of a specific method for manufacturing a semiconductor device.

FIG. 4 is a manufacturing process diagram (continued) illustrating an example of a specific method for manufacturing a semiconductor device.

FIG. 5 is a manufacturing process diagram showing an example of a conventional technique.

FIG. 6 is a manufacturing process diagram (continued) showing an example of a conventional technique.

FIG. 7 is a manufacturing process diagram (continued) showing an example of a conventional technique.

[Explanation of symbols]

11 semiconductor substrate, 15 groove, 18 insulating film, 19 resist film, 20 opening

Claims (4)

[Claims] 1. A method of manufacturing a semiconductor device, comprising: forming a groove for isolating an active region in a semiconductor substrate; and embedding an insulating film in the groove to form an element isolation region. A step of forming a resist film on the insulating film after forming an insulating film on the semiconductor substrate; and directly reading a pattern position of the active area to generate data of a pattern position of the active area. Exposing and developing the resist film based on the data to form an opening on the active region; and removing the insulating film on the active region from the opening. A method for manufacturing a semiconductor device. 2. A method of manufacturing a semiconductor device, comprising: forming a groove for separating an active region in a semiconductor substrate; and forming an element isolation region by burying an insulating film in the groove. A step of forming a resist film on the insulating film after forming the insulating film on a semiconductor substrate; a step of preparing an information file indicating a pattern position of the active area; and the active area read from the information file. Exposing the resist film based on the information of the pattern position of
A method of manufacturing a semiconductor device, comprising: a step of forming an opening on the active region by developing; and a step of removing the insulating film on the active region from the opening. 3. A method of manufacturing a semiconductor device, wherein a groove for isolating an active region is formed in a semiconductor substrate, and an insulating film is buried in the groove to form an element isolation region. After forming an insulating film on the semiconductor substrate, forming a resist film on the insulating film, preparing an information file indicating a pattern position of the active area, and directly reading the pattern position of the active area The step of creating data of the pattern position of the active area, and exposing and developing the resist film based on the data of the pattern position and the information file obtained by directly reading the active area Forming an opening thereon; and removing the insulating film on the active region from the opening. Method of manufacturing a semiconductor device characterized in that it comprises a. 4. The step of forming an opening in the resist film based on data obtained by directly reading a pattern position of the active area and data of the information file, 4. The method according to claim 3, wherein the data of the information file is corrected based on the data of the pattern position of the area, and an opening is formed in the resist film based on the corrected data of the pattern position of the active area. A method for manufacturing a semiconductor device.