JP2000209503A - Solid state image pickup device and its video signal output device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate a state where every boundary of areas is conspicuous as a fixed pattern noise by outputting the partial images of areas adjacent to each other for every divided area. SOLUTION: A solid state image pickup device with which the image signals are read out of the divided areas in parallel to each other is provided with plural horizontal and/or vertical scanning circuit which reads the image signals overlapping each other out of the vertical and/or horizontal line pixel string respectively. With such a constitution, the characteristics of signal reading circuits placed in every divided area are averaged by an averaging circuit. For instance, the horizontal scanning circuits 1-4 of a MOS amplification type solid state image pickup device are driven by the horizontal start pulses which start at the same time and the vertical scanning circuits 1 and 2 are also driven by the vertical start pulses which start at the same time. The image signals which are read by these horizontal and vertical scanning circuits are outputted from the reading circuits 1-4 simultaneously with and in parallel to each other.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state imaging device of the type in which video signals are simultaneously read in parallel from respective divided regions, and more particularly to a solid-state imaging device in which boundaries between regions are made inconspicuous and an image for the same. The present invention relates to a signal output device.

[0002]

2. Description of the Related Art FIG. 5 shows an example of the configuration of a conventional MOS amplification type solid-state imaging device of this type. In FIG. 5, a pixel p ₁₁ to a pixel p _aa (divided area 1) are divided into pixels p by a horizontal scanning circuit (configured by a shift register and a selection switch) 1 and a vertical scanning circuit (configured by a shift register) 1. from _1b to the pixel p _an, by (divided area 2) the horizontal scanning circuit 2 and the vertical scanning circuit 1, a pixel p _b1 to the pixel p _na (divided regions 3) by the horizontal scanning circuit 3 and the vertical scanning circuit 2 and the pixel, The horizontal scanning circuit 4 from p _bb to pixel p _nn (divided area 4)
And the vertical scanning circuit 2 scans the pixels to read out the imaged video signals.

As described above, each video signal read from the divided areas 1 to 4 simultaneously and in parallel is supplied to a read circuit (a circuit including an amplifier and an AD converter) shown in the figure.
The data is output via 1 to 4 and temporarily stored in an image memory (not shown).

[0004]

However, in the above-described conventional solid-state image pickup device, when a video signal obtained from each divided area is synthesized on a monitor screen, the characteristics of a readout circuit are different due to the difference in characteristics. The boundaries of the regions are noticeable as fixed pattern noise, and the quality of the displayed image is degraded.

[0005] Further, when a video signal is converted into a digital signal and an arbitrary pixel is subjected to arithmetic processing (hereinafter referred to as two-dimensional image processing) using the pixel values around the pixel, the center of the screen is also located at the edge of the screen. In order to obtain an equivalent operation result, the output image, which is the operation result constituting the final effective pixel area, is one-dimensional or two-dimensional when photographing.
Although a video signal (hereinafter, referred to as "extended image") in a dimensionally wider area is required, a conventional solid-state imaging device cannot directly obtain an extended image at an area boundary portion from an image signal from each divided area. In this case, it is necessary to take the parallel readout output once into a frame memory or the like, and then use the video signals of the other divided areas to create a marginal video.

A first object of the present invention is to provide a conventional method for synthesizing a video signal obtained from a solid-state imaging device of a type in which a video signal is simultaneously read in parallel from each divided area on a monitor screen. Is to make it less noticeable as a fixed pattern noise.

A second object of the present invention is to provide a two-dimensional image processing by converting a video signal obtained from a solid-state imaging device into a digital signal, and the end of the screen for each divided area is equivalent to the center of the screen. Is to be able to perform the arithmetic processing.

[0008]

In order to achieve the above object, the present invention provides a solid-state imaging device of the type in which video signals are read from each divided area simultaneously and in parallel.
A plurality of horizontal scanning circuits and / or a plurality of horizontal scanning circuits for reading video signals overlapping with each other from a vertical pixel row and / or a horizontal line row near the boundary of the region.
Alternatively, a vertical scanning circuit is provided.

The solid-state imaging device according to the present invention may further include a part of a part of the video signal read by the plurality of horizontal scanning circuits and / or the vertical scanning circuit which overlaps each other.
It is characterized in that it is formed into a marginal image for two-dimensional image processing.

Further, the video signal output device for a solid-state imaging device according to the present invention performs reading of a video signal from a vertical pixel row and / or a horizontal line pixel row near the boundary of each area so as to overlap each other. A video signal output device that outputs a video signal from a solid-state imaging device of a type that includes a plurality of horizontal scanning circuits and / or vertical scanning circuits and is configured to simultaneously read video signals from respective divided regions in parallel,
Regarding the region where the video signal is read out in duplicate,
An averaging circuit for outputting an image signal by performing an averaging process in accordance with the number of duplications is provided.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below based on embodiments of the present invention with reference to the accompanying drawings. FIG.
1 shows an embodiment of a solid-state imaging device in which the present invention is applied to a MOS amplification type solid-state imaging device. In FIG. 1, horizontal scanning circuits 1, 2, 3, and 4 are driven by horizontal start pulses that start simultaneously, and vertical scanning circuits 1 and 2 are also driven by vertical start pulses that start simultaneously. Are output from the readout circuits 1 to 4 simultaneously and in parallel.

The above is described in more detail. Horizontal running
Pixel p that constitutes the scanning line₁₁From pixel p_1bPixel values up to
Selective reading by direct scanning circuit 1 and horizontal scanning circuit 1
Then, they are sequentially output through the readout circuit 1. this
At the same time, the pixel p which also forms the horizontal scanning line_1aFrom pixel
p_1nThe pixel values up to are applied to the vertical scanning circuit 1 and the horizontal scanning circuit 2.
Therefore, they are selectively read and sequentially passed through the read circuit 2.
It is output next. Hereinafter, another (lower) horizontal run
Pixel p that constitutes the scanning line_b1From pixel p_bb, And pixel p_ba
From pixel p_bnPixel values of the vertical scanning circuit 1 and the water
For the flat scanning circuit 1 and the vertical scanning circuit 1 and the horizontal scanning circuit 2
Therefore, the data is selectively read out, so that the
Pixel p₁₁From pixel p _bbPixel values up to read circuit 1
From one frame at a time.
Pixel p during the period_1aFrom pixel p_bnPixel values up to
The data is sequentially output from the road 2.

As described above, the solid-state image pickup device according to the present invention comprises a horizontal scanning circuit 1 and a horizontal scanning circuit 2 for reading video signals overlapping with each other from horizontal pixels near the boundary of each region.
It has. In the above, portions are duplicates is from pixel p _1a to the pixel p _bb.

The same applies to the horizontal scanning circuit 3 and the horizontal scanning circuit 4. The overlapping part in this case is
Pixels from p _aa to pixel p _nb . The vertical scanning circuits 1 and 2 also have an overlap from the pixel p _a1 to the pixel p _bn .

Again, the horizontal scanning circuit 1 and the horizontal scanning circuit 2
I will talk about The horizontal scanning circuit 1 includes a pixel p in the first column.
₁₁, -----, pixel p_a1, Pixel p_b1Line connected to
Bottom, vertical readout line), and finally the b-th column
Eye pixel p_1b, -----, pixel p _ab, Pixel p_bbConnected to
Video signals are read out sequentially from vertical readout lines
The scanning is performed as follows.

On the other hand, the horizontal scanning circuit 2 starts scanning at the same time as the horizontal scanning circuit 1, and the pixels connected to the vertical readout line to be read first are the pixels p _1a ,.
_Since the pixel is _aa and the pixel p _ba , even after the video signal is read from these pixels, the horizontal scanning circuit 1 cannot read the video signal later unless the same amount of charge remains in the pixel as before the reading. From the above, it is assumed that the solid-state imaging device of the present invention is a nondestructive readout type.

In addition to the nondestructive readout (that is, the accumulated charge does not decrease until it is reset), the horizontal scanning period is shorter than the frame period. 1 and the accumulated charge amount at the time read by the horizontal scanning circuit 2 hardly differ from each other. In reading, output currents of almost the same value are obtained. The same can be said for the horizontal scanning circuit 3 and the horizontal scanning circuit 4.

The horizontal lines selected by the vertical scanning circuits 1 and 2 are read once in one frame period, and thereafter, the reset operation of the accumulated charges of the pixels is performed simultaneously for each horizontal line (line reset operation). Shall be. Specifically, the pixels from the pixel p _a1 to the pixel p _bn but read multiple times by the vertical scanning circuit 1 and 2,
These horizontal lines that are read repeatedly do not perform a line reset operation after reading by the vertical scanning circuit 1,
The line reset operation is performed only after reading by the vertical scanning circuit 2 of the next frame performed immediately after reading by the vertical scanning circuit 1. Therefore, for the horizontal lines that are read in duplicate, the pixel accumulation time t1 at the time read by the vertical scanning circuit 1 is shorter than the pixel accumulation time t2 at the time read by the vertical scanning circuit 2. Since the difference (t2−t1) between the accumulation times is equal to the scanning time of the number of overlapping horizontal lines, the number of horizontal lines connected to each vertical scanning circuit (in this example, b−1 lines which are the same as each other) And n−a) are sufficiently large, the difference in the accumulation time is sufficiently small compared to the frame period. This situation is shown in FIGS. 2A and 2B.

As described above, in the pixel configuration of FIG. 1, the pixels from the pixel p _1a to the pixel p _bb are readout circuits 1
And 2, the pixels from the pixel p _aa to the pixel p _nb are read out by the readout circuits 3 and 4 from the pixels p _a1 to p
_Some of the pixels up to _bb are read out by the readout circuits 1 and 3, and some of the pixels from the pixels p _aa to p _bn are read out by the read out circuits 2 and 4, respectively.

Next, an example in which two-dimensional image processing is performed after converting a read signal into a digital signal will be described.
In this example, it is assumed that a parallel output signal from the solid-state imaging device according to the present invention is subjected to analog-to-digital conversion, stored in an image memory, and then subjected to two-dimensional image processing.

FIG. 3 shows two-dimensional image processing according to the present embodiment. 3, the vertical, is divided by the horizontal dotted line, although the pixels included in the divided region 1 of the upper left portion is a pixel p ₁₁ to the pixel p _aa, from pixel p ₁₁ to the pixel p _bb from the read circuit 1 Are read out and the digital data M
₁₁ to _Mbb are stored in the memory 1, and the data stored in the memory 1 is subjected to two-dimensional image processing using surrounding pixel values. For example, when implementing a spatial enhancement filter, an example of a calculation formula for each pixel data is shown by the following formula. _Ovw = 2 · _Mvw− (M _{(v−1) w} + _{Mv (w−1)} + _{Mv (w + 1)} + M
_{(v + 1) w} ) / 4 where O _vw is a calculation result, M _vw is image data to be calculated, and v and w are spatial coordinates (v increases downward from the screen, w
Is increasing from left to right on the screen).

As described above, the pixel data M_vwSecondary to
When performing the original image processing, the pixel p_vwPixel data M around
_{(v-1) w}, M_{v (w-1)}, M_{v (w + 1)}, M_{(v + 1) w}(Each picture
Element p _vwThe upper, left, right, and lower pixel data)
Required. Data stored in memory is stored in divided area 1.
On the other hand, there is a marginal video data for each pixel around.
The result of the two-dimensional image processing is the extra video data
Becomes unnecessary, and the data O_{twenty two}From O_aa
Is stored in the memory 5 (the pixel shown in the memory 1 of FIG. 3).
Data M_2aWhen this two-dimensional image processing is performed on
Is O_2a= 2 · M_2a− (M_1a+ M_2a'+ M_2b+ M_3a) /
4) and stored as a processing result of the divided area 1.
Direct output is possible.

In the above-described example (examples shown in FIGS. 1 to 3), the pixels that are read redundantly are described as having two rows and two columns. However, this is not limited to two rows and two columns.
It goes without saying that there may be one row and / or one column, or three rows and / or three columns, and even more.
Further, the number of divisions of the divided region is not limited to four in the above-described example, and the present invention can be applied to arbitrary plural divisions.

Finally, a video signal output device for a solid-state imaging device according to the present invention will be described. Here, each region 1 to 4
The apparatus of the present invention for forming a composite signal by combining video signals obtained simultaneously and in parallel from each other into one will be described. FIG. 4 shows a configuration example of the device of the present invention. In FIG. 4, signals read from the divided area 1 are stored in the areas a, b, c, and d of the memory 1. Similarly, the signals read from the divided area 2 are the signals e, f,
In each of the areas g and h, the signal read from the divided area 3 is applied to each of the areas i, j, k, and l of the memory 3, and the signal read from the divided area 4 is applied to m, n, and m of the memory 4. It is stored in each area of o and p.

Now, assuming that reading is started from each of the divided areas 1, 2, 3, and 4 simultaneously and in parallel, the signals stored in the areas i, j, m, and n of the memories 3 and 4 are Since the read signal is earlier than the signals stored in the areas c, d, g, and h by (vertical scanning time of each divided area)-(scanning time of the overlapping horizontal line between the divided areas), the read signal is read in FIG. A delay circuit for one frame is inserted after the circuits 1 and 2 to match temporal continuity. Since the signals stored in the areas b and e of the memories 1 and 2 correspond to the same pixel of the image sensor, they are stored as signals of the area q of the memory 6 after the averaging process. Similarly, memory 1,
Signals stored in areas c and i of area 3 are areas r of memory 6 after averaging processing, areas h and n of memories 2 and 4 are areas of area s of memory 6 after averaging processing and areas of memories 3 and 4 l and o
Represents the area t of the memory 6 after the averaging process and the memory 1
Since the areas d, g, j, and m overlapping with all of the elements from 4 to 4 are the same pixel signals, they are stored as signals in the area u of the memory 6 after the averaging process. The signal stored in each area of the memory 6 is output as a composite signal by the video signal output device of the present invention. In the averaging process described above, since the regions d, g, j, and m overlap four divided regions, the regions are reduced to 1/4, and all other regions are reduced to 1/2.

In the example shown in FIG. 4, the outputs (digital signal outputs) of the readout circuits 1 to 4 are temporarily stored in the memories 1 to 4, and then, the averaging process is performed on the overlapped portion, and the data is stored in the memory 6 again. However, the outputs of the read circuits 1 to 4 may be written directly into the memory 6 and the overlapping portion may be averaged with the already written data to update the memory contents. Alternatively, the synthesized signal may be directly obtained from the above-described (4) to (4). As described above, in any case, differences in output signal characteristics due to differences in readout circuits are averaged, and fixed pattern noise between regions is reduced.

[0027]

According to the present invention, in a solid-state imaging device of a type in which video signals are read out from each divided region simultaneously and in parallel, a part of the image of an adjacent region is output overlapping each other for each divided region. Therefore, the characteristics of the signal readout circuit provided for each divided area are averaged by the averaging processing circuit, so that the boundary between the areas does not become conspicuous as fixed pattern noise unlike the related art.

Further, by outputting an image including a marginal image according to the present invention, it becomes possible to digitize the simultaneous parallel readout signal as it is and perform two-dimensional image processing, thereby increasing the speed of image processing and the processing circuit. The size can be reduced.

[Brief description of the drawings]

FIG. 1 shows an embodiment of a solid-state imaging device in which the present invention is applied to a MOS amplification type solid-state imaging device.

FIG. 2 shows a comparison of the accumulation time of video signals read by vertical scanning circuits 1 and 2 in FIG.

FIG. 3 shows an example of two-dimensional image processing performed on a parallel output signal from a solid-state imaging device of the present invention.

FIG. 4 shows a configuration example of a video signal output device for a solid-state imaging device according to the present invention.

FIG. 5 shows a configuration example of a conventional region-divided parallel readout solid-state imaging device.

Claims (3)

[Claims] 1. A solid-state imaging device of a type in which video signals are read out from each divided region simultaneously and in parallel, wherein a video image is overlapped with a vertical pixel column and / or a horizontal line pixel column near a boundary of the region. A plurality of horizontal scanning circuits for reading signals and / or
Alternatively, a solid-state imaging device comprising a vertical scanning circuit. 2. The solid-state imaging device according to claim 1, wherein
A solid-state imaging device, wherein a part of an overlapping part of the video signals read by the plurality of horizontal scanning circuits and / or the vertical scanning circuits is formed as a marginal image for two-dimensional image processing. 3. A plurality of horizontal scanning circuits and / or vertical scanning circuits each of which reads a video signal in an overlapping manner from a vertical pixel row and / or a horizontal line pixel row near a boundary of each area. A video signal output device for outputting a video signal from a solid-state imaging device of a type in which a video signal is read out from each divided region simultaneously and in parallel, wherein the number of times of duplication is determined for the region where the video signal is read out in an overlapping manner. A video signal output device for a solid-state imaging device, comprising an averaging circuit for outputting a video signal by performing an averaging process according to the above.