JP2004260265A - Pixel extracting circuit having pixel turning over function, and image pickup apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain a pixel extracting circuit having a pixel turning over function. <P>SOLUTION: This circuit is provided with an input terminal A, (n×m) sets of image memories, (n-1) sets of line memories for storing (M-m) items of pixel values, [(n+1)/2] sets of data selectors, and a control unit. These devices are linked at a cycle of [m sets of pixel memories, a set of the a line memory, m sets of pixel memories and a set of a line memory], starting at the input terminal A. The control unit switches the Pth data selector from the input terminal A side to the input terminal A during a scanning input at the Pth line ((n+1)/2≥P≥2). Further, the control unit switches the output of the first data selector from the input terminal A to the output of the (2Q)th line memory while the Qth line ((n-1)/2≥Q≥1) is forwarded after the completion of the input of image data. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a pixel extraction circuit that extracts pixel blocks from image data in a scanning order. The present invention relates to an imaging device equipped with the pixel extraction circuit.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, there has been known an electronic camera that displays a captured image at a high frame rate (eg, 30 frames / second) on a monitor screen or an electronic viewfinder as a moving image. The user can appropriately determine the composition at the time of shooting while viewing the moving image display.
[0003]
The captured image at the high frame rate is also used as an evaluation signal for automatic exposure, automatic focus, and automatic white balance in the electronic camera. Normally, an electronic camera generates a captured image at the high frame rate using a high-speed draft mode of the image sensor. The high-speed draft mode is an operation mode in which a captured image is read out at high speed by adding or thinning out a captured image in a vertical direction (vertical direction) in the image sensor.
[0004]
The captured image at the high frame rate read in this way is subjected to image processing such as color interpolation, electronic zoom, resolution conversion for adjusting the display size, noise removal filter processing, and edge enhancement filter processing by the electronic camera. After that, the images are sequentially displayed on the electronic viewfinder.
In this type of image processing, image processing is performed while locally extracting pixel blocks from image data. In this case, the pixels constituting the pixel block are not aligned at the upper, lower, left, and right ends of the captured image. Therefore, each time one image processing is completed, the upper, lower, left, and right pixels of the captured image are lost, and the image size is reduced accordingly.
[0005]
As a conventional technique for preventing such image narrowing, Japanese Patent Application Laid-Open No. H11-163,098 is known. Patent Document 1 discloses an imaging device that duplicates both left and right ends of a captured image. By widening the captured image in the horizontal direction using this imaging device, it is possible to prevent the captured image from being narrowed in the horizontal direction in image processing.
[Patent Document 1]
JP 2001-69518 A (FIG. 3, paragraph 0051)
[0006]
[Problems to be solved by the invention]
By the way, in the captured image generated in the high-speed draft mode described above (hereinafter referred to as “draft image data”), the number of pixels in the vertical direction is more remarkable than the number of pixels in the horizontal direction because lines are thinned in the vertical direction. Less. Therefore, when image processing is performed on the draft image data, the effect of pixel omission in the vertical direction appears greatly, and the draft image data is significantly narrowed in the vertical direction. On the other hand, the influence of the pixel drop in the horizontal direction is negligible because the number of pixels in the horizontal direction is originally large.
[0007]
When such draft image data is displayed in a viewfinder, the viewfinder field becomes particularly narrow in the vertical direction. In this case, the user cannot accurately determine the imaging range in the vertical direction, which hinders composition determination.
In Patent Document 1 described above, since the width is increased in the horizontal direction, the above-described narrowing of the image in the vertical direction cannot be solved.
[0008]
Further, the circuit of FIG. 3 of Patent Document 1 requires circuits for the number of delay stages in the vertical direction for widening in the horizontal direction. Therefore, there is a disadvantage that the circuit configuration is complicated by the number of stages.
Further, the circuit shown in FIG. 3 of Patent Document 1 is a circuit for widening the left and right one pixel at a time in the horizontal direction. Therefore, it is not possible to widen the left and right by a plurality of pixels at a time. Note that, in paragraph 0051 of Patent Document 1, it is described that the width of a plurality of pixels can be increased in the horizontal direction. However, the circuit for the number of delay stages in the vertical direction is further complicated, and specific control for selection control is performed. There is no description. Therefore, the circuit configuration is completely different from the circuit configuration of the present invention described later.
[0009]
By the way, as a method of easily performing the above-described vertical widening, the draft image data for one frame is temporarily stored in the frame memory, and a part of the stored image data is copied on the area of the frame memory. It is conceivable to increase the width in the vertical (horizontal) direction.
However, in this method, the draft image data must be stored in the frame memory for each frame. In this case, the start of the image processing is delayed by at least one frame time, and the image data copy time for performing the widening in the vertical (horizontal) direction is further required. Therefore, the display time lag of the electronic viewfinder is further extended. Therefore, it becomes increasingly difficult to observe a subject in real time on the electronic viewfinder.
[0010]
Furthermore, this method consumes a great deal of power in reading and writing the frame memory. That is, during a long viewfinder display period, the draft image data is stored in the frame memory and the draft image data for image processing is read out every frame. As a result, a great deal of power is consumed for reading and writing the frame memory. For this reason, there is a problem that the battery consumption of the electronic camera is severe and the usable time of the electronic camera is shortened.
[0011]
In addition, there is a problem that the data flow of storing and reading out the draft image data in the frame memory frequently occurs, so that the traffic of the image data bus increases.
Therefore, an object of the present invention is to provide a pixel extraction circuit having a pixel folding function. Further, another object of the present invention is to provide an imaging device equipped with the image extraction circuit.
[0012]
[Means for Solving the Problems]
Hereinafter, the present invention will be described.
[0013]
<< Claim 1 >>
The invention according to claim 1 is a pixel extraction circuit that extracts pixel blocks of n pixels by m pixels in the scanning order from image data consisting of pixel values of N rows by M columns. Is an odd number, N> n ≧ 3, M> m ≧ 2).
This pixel extraction circuit has the following components.
.Input terminal A to which image data is scanned and input
・ (N × m) pixel memories that hold pixel values
-(N-1) line memories holding (M-m) pixel values
[(N + 1) / 2] data selectors for selecting and outputting pixel values
.Connecting paths that connect the above components
.Control unit that forwards pixel values to the route of the connecting road
An output terminal for outputting (n × m) pixel values held by the pixel memory as a pixel block
[0014]
The components described above are connected as follows by a connection path.
That is, with the input terminal A as a starting point, all of the above components are repeated in the repeating order of [one data selector, m pixel memories, one line memory, m pixel memories, and one line memory]. Connect in a row.
This pixel extraction circuit controls the data selector as follows.
That is, the control unit switches the output of the P-th data selector counted from the input terminal A to the input terminal A during the scanning input of the P-th row (where (n + 1) / 2 ≧ P ≧ 2) of the image data.
Further, the control unit outputs the output of the first data selector counting from the input terminal A during the forward period of the Q-th row (where (n-1) / 2 ≧ Q ≧ 1) after the input of the image data is completed. , (2Q) is switched to the output of the line memory.
This pixel extraction circuit is a circuit used when the number n of vertical pixels of a pixel block is an odd number. With the above-described circuit configuration and control operation, the pixel extraction circuit can extract a pixel block of a desired size in the scanning order while adding a pixel width of a desired width to the upper and lower ends of the image data.
[0015]
<< Claim 2 >>
According to a second aspect of the present invention, there is provided a pixel extracting circuit for extracting pixel blocks of n pixels by m pixels in the scanning order from image data having pixel values of N rows by M columns. Is an even number, N> n ≧ 2, M> m ≧ 2).
This pixel extraction circuit has the following components.
.Input terminal A to which image data is scanned and input
・ (N × m) pixel memories that hold pixel values
-(N-1) line memories holding (M-m) pixel values
[(N + 2) / 2] data selectors for selecting and outputting pixel values
.Connecting paths that connect the above components
.Control unit that forwards pixel values to the route of the connecting road
An output terminal for outputting (n × m) pixel values held by the pixel memory as a pixel block
[0016]
The components described above are connected as follows by a connection path.
That is, starting from the input terminal A, one data selector, m pixel memories, and one line memory are connected, and [one data selector, m pixel memories, and one line memory are connected. The above-mentioned components are all connected in a line in a repetition order of “book, m pixel memories, and one line memory”.
[0017]
This pixel extraction circuit controls the data selector as follows.
That is, the control unit switches the output of the (P + 1) -th data selector counted from the input terminal A side to the input terminal A during the scanning input of the P-th row (where n / 2 ≧ P ≧ 1) of the image data.
Further, after the input of the image data is completed, the control unit outputs the output of the first data selector counted from the input terminal A side during the forward period of the Q-th row (where n / 2 ≧ Q ≧ 1) to (2Q -1) Switching to the output of the line memory of the first line.
This pixel extraction circuit is a circuit used when the number n of vertical pixels of a pixel block is an even number. With the above-described circuit configuration and control operation, the pixel extraction circuit can extract a pixel block of a desired size in the scanning order while adding a pixel width of a desired width to the upper and lower ends of the image data.
[0018]
<< Claim 3 >>
According to a third aspect of the present invention, in the pixel extraction circuit according to the first or second aspect, the original image data consisting of pixel values of N rows by (Ms) columns is provided before the input terminal A. Is provided with a widening circuit that widens the image data of N rows × M columns by folding pixels at both ends of each row (where s = m−1, m when m is an odd number). Is even if s = m).
The widening circuit configured as described above adds pixel wrapping to the left and right ends of the original image data. Subsequently, after the image data is scanned and input from the input terminal A, pixel wrapping is added in the direction of the upper and lower ends. With such a two-stage process, it is possible to add pixel folding in four directions, that is, upper, lower, left, and right ends.
[0019]
<< Claim 4 >>
According to a fourth aspect of the present invention, in the pixel extracting circuit according to the third aspect, the widening circuit is configured as follows (where m is an odd number).
First, it has the following components.
An input terminal B to which original image data composed of pixel values of N rows × (M−m + 1) columns is scanned in
.M pixel memories that hold pixel values
[(M + 1) / 2] data selectors for selecting and outputting pixel values
.Connecting paths that connect the above components
.Control unit that forwards pixel values to the route of the connecting road
An output terminal for providing a pixel value held by the m-th pixel memory from the input terminal B to the input terminal A
[0020]
The components described above are connected as follows by a connection path.
That is, all of the above components are connected in a line in a repetition order of [one data selector and two pixel memories] starting from the input terminal B.
This pixel extraction circuit controls the data selector as follows.
That is, at the time of the L-th forward feeding (where (m + 1) / 2 ≧ L ≧ 2) from the start of the horizontal scanning of the original image data, the control unit outputs the output of the L-th data selector counted from the input terminal B side to the input terminal B. Switch to.
[0021]
Further, the control unit outputs the output of the first data selector counted from the input terminal B side at the time of the R-th forward feeding (where (m−1) / 2 ≧ R ≧ 1) from the end of the horizontal scanning of the original image data, The output is switched to the output of the (2R) -th pixel memory.
This widening circuit is a circuit used when the number m of horizontal pixels of a pixel block is an odd number. With the above-described circuit configuration and control operation, the widening circuit inputs the scan data of the original image data and adds the pixel wrap to the left and right ends of each row.
[0022]
<< Claim 5 >>
According to a fifth aspect of the present invention, in the pixel extracting circuit according to the third aspect, the widening circuit is configured as follows (where m is an even number).
First, it has the following components.
An input terminal B for scanning and inputting original image data consisting of pixel values of N rows × (Mm) columns
.M pixel memories that hold pixel values
[(M + 2) / 2] data selectors for selecting and outputting pixel values
.Connecting paths that connect the above components
.Control unit that forwards pixel values to the route of the connecting road
An output terminal for providing a pixel value held by the m-th pixel memory from the input terminal B to the input terminal A
[0023]
The components described above are connected as follows by a connection path.
That is, starting from the input terminal B, one data selector and one pixel memory are connected, and all of the above components are repeated in the order of [one data selector and two pixel memories]. Connect in a row.
This pixel extraction circuit controls the data selector as follows.
That is, at the time of the L-th (m / 2 ≧ L ≧ 1) forward feed from the start of the horizontal scanning of the original image data, the control unit outputs the output of the (L + 1) -th data selector counted from the input terminal B to the input terminal B. Switch to.
[0024]
Further, at the time of the R-th forward feed (where m / 2 ≧ R ≧ 1) from the end of the horizontal scanning of the original image data, the output of the first data selector counted from the input terminal B side is output to the (2R−1) -th pixel. Switch to memory output.
This widening circuit is used when the number m of horizontal pixels of a pixel block is an even number. With the above-described circuit configuration and control operation, the widening circuit inputs the scan data of the original image data and adds the pixel wrap to the left and right ends of each row.
[0025]
<< Claim 6 >>
An imaging device according to a sixth aspect includes an imaging unit, a “pixel extraction circuit according to any one of the first to fifth aspects”, a processing unit, and an interface unit.
The imaging unit captures a subject image and generates image data.
The pixel extraction circuit extracts pixel blocks of n pixels by m pixels from the image data in the order of scanning.
The processing unit performs signal processing using the pixel block extracted by the pixel extraction circuit as a processing unit.
The interface unit performs one of the group consisting of recording, image display, and external output on the image data on which the signal processing has been performed by the processing unit.
In the above configuration, the pixel extraction circuit outputs the pixel blocks in the order of scanning while adding pixel wrapping to the upper and lower ends (or upper, lower, left, and right ends) of the image. The processing unit can perform a pipeline type signal processing for each pixel block output in the scanning order as a processing unit. As a result, a plurality of processes such as "pixel folding", "pixel block extraction", and "pixel block processing" can be executed at high speed by a pipeline type work.
[0026]
<< Claim 7 >>
According to a seventh aspect of the present invention, in the imaging apparatus according to the sixth aspect, the imaging unit reduces the number of lines of the image data and reads the image data, thereby obtaining a draft having a lower resolution and a higher frame rate than a recording still image. An imaging mode for continuously generating image data is provided.
On the other hand, the pixel extraction circuit extracts pixel blocks of n pixels by m pixels in the scanning order while performing pixel folding at least at the upper end and the lower end of the draft image data.
The processing unit sequentially performs signal processing on the draft image data using the pixel block extracted by the pixel extraction circuit as a processing unit.
On the other hand, the interface unit sequentially performs moving image display of the draft image data on which signal processing has been performed by the processing unit.
With the above configuration, most of a series of processing processes until the draft image data is displayed as a moving image is a pipeline process. As a result, it is possible to greatly reduce the time required for displaying the moving image of the draft image data.
Further, in the pixel extraction circuit, pixel folding is added to the upper and lower ends (or upper, lower, left, and right ends) of the image, so that a situation in which the screen size of the moving image display becomes narrow in the vertical direction can be improved.
[0027]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0028]
《Explanation of electronic camera configuration》
FIG. 1 is a schematic block diagram of an electronic camera 11 according to the present embodiment.
In FIG. 1, a photographing lens 12 is attached to an electronic camera 11. The light receiving surface of the image sensor 13 is arranged in the image space of the photographing lens 12. The imaging device 13 has two imaging modes: a still mode and a high-speed draft mode. The still mode is a mode in which a full-resolution image signal is read from the image sensor 13 by interlace scanning (or progressive scanning). On the other hand, the high-speed draft mode generates draft image data with a reduced number of lines by performing pixel addition or pixel thinning in the vertical direction of the image inside the image sensor 13, and reads out the draft image data by progressive scanning. Mode.
[0029]
Normally, the timing generator 14 drives the image sensor 13 in the high-speed draft mode, and generates draft image data for viewfinder display and control signals at a high frame rate. When the electronic camera 11 is released from this state, the timing generator 14 drives the image sensor 13 in the still mode, and generates a high-definition image for recording (hereinafter, referred to as “still image data”).
[0030]
The scanning output from the image sensor 13 is subjected to gain adjustment (PGA: Programmable Gain Amp) in accordance with the imaging sensitivity, and then digitized by the A / D converter 15 in pixel units. Note that the signal processing unit 16 can also perform gain adjustment (sensitivity adjustment) by digital processing.
The digitized scanning output is subjected to signal processing (pixel defect correction, optical black level correction, white balance adjustment, gradation conversion, etc.) in real time by the signal processing unit 16.
[0031]
Here, when the still mode of the image pickup device 13 is interlaced scanning, the output (field image) of the signal processing unit 16 is output to the CCD image data in the image memory 16a in preparation for image processing (such as color interpolation) in frame units at the subsequent stage. Once stored in the area. On the memory area of the image memory 16a, a plurality of field images are combined to complete one frame of still image data. The still image data is read out from the image memory 16a in a line order (progressive), and supplied to the pixel extraction circuit 17.
[0032]
Incidentally, when the still mode of the image sensor 13 is progressive scanning, the scanning output from the signal processing unit 16 may be input to the pixel extraction circuit 17 without passing through the image memory 16a.
On the other hand, in the case of the high-speed draft mode, the scan output (progressive scan) of the signal processing unit 16 is directly input to the pixel extraction circuit 17 without passing through the image memory 16a.
[0033]
The pixel extraction circuit 17 extracts a pixel block, which is a processing unit of color interpolation, from the input scan data, and sequentially outputs the pixel block to the color interpolation unit 18. The color interpolation unit 18 performs a color interpolation process using this pixel block as a processing unit, and aligns the color components of all RGB colors for each pixel. Note that lines are thinned out in the draft image data so as to have the same color arrangement (for example, Bayer arrangement) as the still image data. Therefore, the color interpolation unit 18 can execute the color interpolation processing of the same algorithm for both images.
[0034]
The scanning output from the color interpolation unit 18 is input to a color conversion unit 19. The color converter 19 converts the input into color coordinates (including color correction, saturation modulation, and the like) in pixel units, converts the input into YCbCr pixel values, and outputs the YCbCr pixel values.
In some cases, a median filter is inserted on the color difference signal (CbCr) side to suppress false color. In this case, it is preferable to insert the pixel extraction circuit of the present invention at a stage preceding the median filter. Further, it is preferable to insert a delay circuit in the path on the luminance signal Y side in order to adjust the phase of YCbCr after the median processing.
[0035]
The resolution conversion section 21 performs resolution conversion. The resolution conversion unit 21 is used for enlarging an image by electronic zoom or reducing an image for creating a small thumbnail. Also, when a high-resolution still image is displayed (reproduced) on a monitor, the resolution converter 21 is used to adjust (reduce) the image size to the monitor.
Since the draft image data has an uneven resolution that is coarse in the vertical direction and dense in the horizontal direction, the viewfinder display is performed after the draft image data is converted into an image with uniform resolution in the vertical and horizontal directions by the resolution conversion unit 21. .
[0036]
The resolution conversion unit 21 can also input image data from the image memory 16a (not shown). When reproducing a shot moving image or still image, the resolution conversion unit 21 converts the image data input from the image memory 16a. The size is displayed on the monitor. In the case of image data that does not require resolution conversion (that is, in the case of the same size), the resolution conversion unit 21 is bypassed.
[0037]
The scanning output from the resolution conversion unit 21 or the color conversion unit 19 is input to the pixel extraction circuit 22. The pixel extraction circuit 22 extracts a pixel block, which is a processing unit of the spatial filter processing, from the input scan data and sequentially outputs the pixel block to the spatial filter unit 23. The spatial filter unit 23 performs a spatial filter process (edge enhancement, noise removal, LPF process, and the like) using the pixel block as a processing unit.
[0038]
The draft image data and still image data processed by the spatial filter unit 23 are sequentially sent to the color difference thinning unit 26. The color difference thinning section 26 performs color difference thinning (a so-called 4: 2: 2 or the like).
The draft image data after the color difference thinning is stored in the viewfinder data area of the image memory 16a. The draft image data stored in this manner is sequentially read out by the image display unit 24 and displayed on the LCD monitor 30 built in the camera or the external TV monitor 31 at predetermined intervals to be used as a viewfinder. You. The image display unit 24 is also used for reproducing and displaying a still image (image output).
[0039]
On the other hand, the still image data after the color difference thinning is stored in the still image data area of the image memory 16a. The stored still image data is subjected to compression processing by the image compression unit 28. The compression code of the still image data generated by the image compression is temporarily stored in the compression code area of the image memory 16a. The compressed code stored in this manner is recorded on a recording medium (such as a memory card) by the recording unit 29.
[0040]
If the image compression unit 28 is a circuit that requires pixel folding in tile units, such as JPEG2000, it is preferable to insert the pixel extraction circuit of the present invention after tile division.
Although the above description has been given of the case of still image shooting, in the case of moving image shooting (motion JPEG, etc.), the draft image data (YCbCr) stored in the viewfinder data area of the image memory 16a is directly compressed by the compression processing unit. 28, the generated compressed codes of a plurality of frames may be sequentially stored in the compressed code area of the image memory 16a. The recording on the recording medium is performed later by the recording unit 29.
Note that the above-described image processing blocks are bypassed as necessary.
Next, specific circuit examples such as the above-described pixel extraction circuits 17 and 22 will be described in detail.
[0041]
<< First circuit example >>
[Description of configuration]
FIG. 2 is a diagram illustrating a first circuit example.
The first circuit example is a pixel extraction circuit 100 that extracts a pixel block of 5 pixels × 5 pixels in the scanning order from image data composed of pixel values of N rows × M columns. 5, m = 5)
This pixel extraction circuit 100 has the following components.
.Input terminal A to which image data is scanned and input
.Pixel memories D1 to D25 that hold pixel values
-Line memories H1 to H4 that hold (M-5) pixel values
Data selectors SE1 to SE3 for selectively outputting pixel values
A connecting path C for connecting the above components
A control unit 101 for sequentially transmitting pixel values to the path of the connection path C in accordance with the pixel clock;
An output terminal 102 that outputs the 25 pixel values held by the pixel memories D1 to D25 as a pixel block
[0042]
These components are connected by the connection path C as follows.
First, starting from the input terminal A, the data selector SE1, the pixel memories D1 to D5, the line memory H1, the pixel memories D6 to D10, the line memory H2, the data selector SE2, the pixel memories D11 to D15, the line memory H3, and the pixel memory D16 to D20, line memory H4, data selector SE3, and pixel memories D21 to D25 are connected in a line in this order.
[0043]
Further, the input terminal A is connected to the input sides of the data selectors SE2 and SE3. On the other hand, the outputs of the line memories H2 and H4 are connected to the input side of the data selector SE1.
Note that a vertical synchronizing signal, a horizontal synchronizing signal, and a pixel clock are input from outside (such as the timing generator 14 or a preceding circuit). These are synchronization signals of the image data scanned and input to the input terminal A. These synchronization signals are supplied to the control unit 101.
The control unit 101 performs sequential control of pixel values and switching control of the data selectors SE1 to SE3 based on these synchronization signals. Further, the control unit 101 generates a synchronization signal (pixel clock, horizontal synchronization signal, vertical synchronization signal) synchronized with the pixel block to be scanned and output, and outputs it to the subsequent stage.
[0044]
[Description of operation]
Subsequently, the circuit operation of the first circuit example will be described with reference to FIGS. First, the first row of scanning input (the first line including effective pixels) is input from the input terminal A. The pixel values of the first row are sequentially sent to the path of the connection path C, and are held in the pixel memories D1 to D5 and the line memory H1.
[0045]
When detecting the start of the second row of the scanning input based on the horizontal synchronization signal, the control unit 101 switches the selected output of the data selector SE2 to the input terminal A. By this switching control, the data selector SE2 outputs the signal of the input terminal A. FIG. 3 is a diagram showing a state where scanning input is performed up to the fifth pixel in the second row.
When the input of the second row is completed, the pixel values of the first row are held in the pixel memories D6 to D10 and the line memory H2. On the other hand, the pixel values of the second row are held in the pixel memories D1 to D5 and the line memory H1. Further, the pixel values of the second row are also held in the pixel memories D11 to D15 and the line memory H3.
[0046]
When detecting the end of the input of the second row based on the horizontal synchronization signal, the control unit 101 returns the selected output of the data selector SE2 to the output of the line memory H2. Further, when detecting the start of the third row of the scanning input based on the horizontal synchronization signal, the control unit 101 switches the selected output of the data selector SE3 to the input terminal A.
FIG. 4 is a diagram showing a state where the fifth pixel in the third row is scanned and input. That is, the m-th pixel in the [(n + 1) / 2] -th row has been scanned and input. At this point, the pixel memories D1 to D25 have pixel blocks of 5 × 5 pixels in which pixel folding is added to the upper end of the image. From this point, the output operation of the pixel block starts.
[0047]
The control unit 101 starts outputting the vertical synchronizing signal, the horizontal synchronizing signal, and the pixel clock in order to notify the subsequent stage (the image processing unit such as the color interpolating unit 18) of the start of the output of the pixel block.
Thereafter, each time one pixel is input to the input terminal A (each pixel clock), a pixel block is output.
[0048]
That is, for each one-pixel clock, pixel blocks shifted in position by one pixel in the horizontal direction are sequentially output. This pixel block is a pixel block suitable for image processing in which processing is performed with reference to a neighboring area for each pixel.
Such horizontal scanning of the pixel block continues until the input of the third row is completed. Thereafter, no pixel block is output until the m-th pixel in the next row is input to the input terminal A. In the subsequent stage, this horizontal blanking period can be known by counting the number of pixel blocks. (Note that, during this period, the control unit 101 may output a horizontal synchronization signal indicating a horizontal blanking period to the subsequent stage to notify the latter stage that the horizontal scanning of the pixel block has entered the horizontal blanking period.)
Thereafter, when the m-th pixel in the next row is scanned and input to the input terminal A, horizontal scanning of the next row of pixel blocks is started again.
[0049]
Thereafter, when detecting the completion of the scanning input of the image data (start of the vertical blanking period) based on the vertical synchronization signal, the control unit 101 switches the selected output of the data selector SE1 to the output of the line memory H2. FIG. 5 is a diagram showing a state in which five pixels have been sequentially fed after the completion of the input (after the switching of SE1).
When the control unit 101 completes the forward feed of one row after the input is completed, the control unit 101 switches the selected output of the data selector SE1 to the output of the line memory H4.
[0050]
FIG. 6 shows a state in which one row and m pixels have been sequentially moved after the completion of the input (a state in which m pixels have been sequentially moved after the second SE1 switching). As shown in FIG. 6, the pixel memories D1 to D25 have pixel blocks of 5 × 5 pixels in which pixel folding is added to the lower end of the image.
The scan output of the pixel block is completed at the point in time when the pixel sequential feed of [(n-1) / 2] rows is completed after the input of the input terminal A is completed.
[0051]
<< 2nd circuit example >>
[Description of configuration]
FIG. 7 is a diagram illustrating a second circuit example.
This second circuit example is a pixel extraction circuit 110 that extracts pixel blocks of 4 pixels by 4 pixels in the scanning order from image data consisting of pixel values of N rows by M columns. 4, m = 4)
This pixel extraction circuit 110 has the following components.
.Input terminal A to which image data is scanned and input
.Pixel memories D1 to D16 that hold pixel values
-Line memories H1 to H3 holding (M-4) pixel values
Data selectors SE1 to SE3 for selectively outputting pixel values
A connecting path C for connecting the above components
A control unit 111 for sequentially transmitting pixel values to the path of the connection path C in accordance with the pixel clock;
An output terminal 112 for outputting 16 pixel values held by the pixel memories D1 to D16 as a pixel block
[0052]
These components are connected by the connection path C as follows.
First, starting from the input terminal A, the data selector SE1, the pixel memories D1 to D4, the line memory H1, the data selector SE2, the pixel memories D5 to D8, the line memory H2, the pixel memories D9 to D12, the line memory H3, and the data selector SE3 and the pixel memories D13 to D16 are connected in a line in the order.
Further, the input terminal A is connected to the input sides of the data selectors SE2 and SE3. On the other hand, the outputs of the line memories H1 and H3 are connected to the input side of the data selector SE1.
[0053]
Note that a vertical synchronizing signal, a horizontal synchronizing signal, and a pixel clock are input from outside (such as the timing generator 14 or a preceding circuit). These are synchronization signals of the image data scanned and input to the input terminal A. These synchronization signals are supplied to the control unit 111.
The control unit 111 performs forward control of pixel values and switching control of the data selectors SE1 to SE3 based on these synchronization signals. Further, the control unit 111 generates a synchronization signal (pixel clock, horizontal synchronization signal, vertical synchronization signal) synchronized with the output of the pixel block, and outputs it to the subsequent stage.
[0054]
[Description of operation]
Next, the circuit operation of the second circuit example will be described with reference to FIGS.
First, the first row of the scanning input is input from the input terminal A.
When detecting the start of the first row of the scanning input based on the vertical synchronization signal and the horizontal synchronization signal, the control unit 111 switches the selected output of the data selector SE2 to the input terminal A. FIG. 8 is a diagram showing a state where the fifth pixel in the first row is scanned and input.
[0055]
Next, when detecting the end of the first row of the scanning input based on the horizontal synchronization signal, the control unit 111 returns the selected output of the data selector SE2 to the output of the line memory H1. Further, when detecting the start of the second row of the scanning input based on the horizontal synchronization signal, the control unit 111 switches the selected output of the data selector SE3 to the input terminal A. FIG. 9 is a diagram showing a state where the fifth pixel in the second row is scanned and input. That is, the m-th pixel in the [n / 2] -th row is in a state of being scanned and input. At this time, a pixel block of 4 pixels × 4 pixels, in which pixel folding is added to the upper end of the image, is first prepared in the pixel memories D1 to D16. From this point, the output of the pixel block starts.
[0056]
The control unit 111 starts outputting the vertical synchronizing signal, the horizontal synchronizing signal, and the pixel clock in order to notify the subsequent stage (the image processing unit such as the color interpolating unit 18) of the start of the output of the pixel block.
Thereafter, the pixel block is output (horizontal scanning) every one pixel clock. This horizontal scanning of the pixel block continues until the entire second row is input to the input terminal A. When the horizontal scanning of the pixel block is completed as described above, the pixel block is not output until the m-th pixel in the next row is input to the input terminal A. Thereafter, when the m-th pixel in the next row is scanned and input to the input terminal A, horizontal scanning of the next row of pixel blocks is started again.
[0057]
Thereafter, when detecting the completion of the scanning input of the input terminal A (start of the vertical blanking period) based on the vertical synchronization signal, the control unit 111 switches the selected output of the data selector SE1 to the output of the line memory H1. FIG. 10 is a diagram showing a state in which five pixels have been sequentially fed after the completion of the input (after the switching of SE1).
After finishing the forward feed for one row after the input is completed, the control unit 111 switches the selected output of the data selector SE1 to the output of the line memory H3.
[0058]
FIG. 11 shows a state in which one row and m pixels are sequentially forwarded after the input is completed (a state in which m pixels are sequentially forwarded after the second SE1 switching). As shown in FIG. 11, the pixel memories D1 to D16 have pixel blocks of 4 × 4 pixels in which pixel folding is added to the lower end of the image.
The horizontal and vertical scanning of the pixel block is completed at the time point when the pixel sequential feed for (n / 2) rows is completed after the input of the input terminal A is completed.
[0059]
<< 3rd circuit example >>
[Description of configuration]
FIG. 12 is a diagram illustrating a third circuit example (where m = 5).
In the third circuit example, pixel wrapping is added to the left and right ends of original image data composed of pixel values of vertical N rows × horizontal (M-4) columns to output vertical N rows × horizontal M image data. This is a widening circuit 200. The widening circuit 200 is a circuit that can be added as an option before the pixel extracting circuit 100 described above.
[0060]
The widening circuit 200 has the following components.
.Input terminal B to which original image data is scanned and input
.Pixel memories D1 to D5 that hold pixel values
Data selectors SE1 to SE3 for selectively outputting pixel values
A connecting path C for connecting the above components
A control unit 201 for sequentially transmitting pixel values to the path of the connection path C according to the pixel clock;
An output terminal 202 for scanning and outputting the pixel value held by the pixel memory D5
[0061]
These components are connected by the connection path C as follows.
First, the data selector SE1, the pixel memories D1 and D2, the data selector SE2, the pixel memories D3 and D4, the data selector SE3, and the pixel memory D5 are connected in a row starting from the input terminal B.
Further, the input terminal B is connected to the input sides of the data selectors SE2 and SE3. On the other hand, the outputs of the pixel memories D2 and D4 are connected to the input side of the data selector SE1.
[0062]
Note that a vertical synchronizing signal, a horizontal synchronizing signal, and a pixel clock are input from outside (such as the timing generator 14 or a preceding circuit). These are synchronization signals of the original image data scanned and input to the input terminal B. These synchronization signals are supplied to the control unit 201.
The control unit 201 carries out sequential control of pixel values and switching control of the data selectors SE1 to SE3 based on these synchronization signals. Further, the control unit 201 generates a synchronizing signal (pixel clock, horizontal synchronizing signal, vertical synchronizing signal) synchronized with the output signal of the output terminal 202, and outputs it to the subsequent stage.
[0063]
[Description of operation]
Next, the circuit operation of the widening circuit 200 will be described with reference to FIG.
First, the first pixel of the scanning input is input from the input terminal B. This pixel value is held in the pixel memory D1.
Next, the control unit 201 switches the selected output of the data selector SE2 to the input terminal B. In this state, the second pixel is input. FIG. 13A is a diagram illustrating a state where the second pixel is scanned and input.
[0064]
Subsequently, the control unit 201 returns the selected output of the data selector SE2 to the pixel memory D2. Further, the selection output of the data selector SE3 is switched to the input terminal B. In this state, the third pixel is input. FIG. 13B is a diagram illustrating a state where the third pixel is scanned and input. In this state, the pixel rows D1 to D5 each store a pixel row to which pixel folding is added at the left end of the image.
[0065]
At this time, that is, from the [(m + 1) / 2] -th forward feed, the pixel output of the widening circuit 200 starts. The control unit 201 starts outputting a vertical synchronizing signal, a horizontal synchronizing signal, and a pixel clock to a subsequent stage (the pixel extracting circuit 100 and the like) to notify the start of the output. Thereafter, the image data is output (horizontal scanning) from the output terminal 202 every pixel clock.
[0066]
FIG. 13C is a diagram illustrating a state where the horizontal scanning input for one row ((M−4) pixels) to the input terminal B is completed. When detecting the completion of the horizontal scanning input based on the horizontal synchronization signal, the control unit 201 switches the selected output of the data selector SE1 to the output of the pixel memory D2. In this state, when one pixel is forwarded, the state shown in FIG.
[0067]
Subsequently, the control unit 201 switches the selected output of the data selector SE1 to the output of the pixel memory D4. In this state, when one pixel is forwarded, the state shown in FIG. In this state, the pixel memory D1 to D5 stores a pixel row in which pixel folding is added to the right end of the image.
When a total of M pixel values are output from the output terminal 202, the horizontal scanning output for one row is completed.
[0068]
Subsequently, in response to the input of the horizontal synchronization signal of the next row, the widening circuit 200 starts processing again. When the first effective pixel (first pixel) of the next row is detected, the first pixel is taken in from the input terminal B and stored in the pixel memory D1. FIG. 13A is a diagram showing this state.
FIG. 13A 'shows that there is a horizontal blanking period for four pixels (four clocks) between rows of the original image. In the case of this example, by providing a horizontal blanking period of at least four pixels (four clocks), the processing of the next row can be started without any trouble. From this state, the processing of the next line starts again.
[0069]
By repeating the above operation for the number of lines, image data with pixel wrapping added to the left and right ends as shown in FIG.
By scanning and inputting this image data to the input terminal A of the pixel extraction circuit 100, it is possible to obtain a scanning output of the pixel block 71 with pixel wrapping added to the upper, lower, left and right ends as shown in FIG. .
[0070]
<< 4th circuit example >>
[Description of configuration]
FIG. 16 is a diagram showing this fourth circuit example (where m = 4).
In the fourth circuit example, pixel wrapping is added to the left and right ends of original image data composed of pixel values of N rows and N columns (M-4) to output N rows and M columns of image data. This is a widening circuit 210. The widening circuit 210 is a circuit that can be added as an option before the pixel extracting circuit 110 described above.
[0071]
The widening circuit 210 has the following components.
.Input terminal B to which original image data is scanned and input
.Pixel memories D1 to D4 that hold pixel values
Data selectors SE1 to SE3 for selectively outputting pixel values
A connecting path C for connecting the above components
A control unit 211 for sequentially transmitting pixel values to the path of the connection path C according to the pixel clock;
An output terminal 212 for scanning and outputting the pixel value held by the pixel memory D4
[0072]
These components are connected by the connection path C as follows.
First, the data selector SE1, the pixel memory D1, the data selector SE2, the pixel memories D2 and D3, the data selector SE3, and the pixel memory D4 are connected in a line starting from the input terminal B.
Further, the input terminal B is connected to the input sides of the data selectors SE2 and SE3. On the other hand, the outputs of the pixel memories D1 and D3 are connected to the input side of the data selector SE1.
[0073]
Note that a vertical synchronizing signal, a horizontal synchronizing signal, and a pixel clock are input from outside (such as the timing generator 14 or a preceding circuit). These are synchronization signals of the original image data scanned and input to the input terminal B. These synchronization signals are supplied to the control unit 211.
The control unit 211 performs forward control of pixel values and switching control of the data selectors SE1 to SE3 based on these synchronization signals. Further, the control unit 211 generates a synchronization signal (pixel clock, horizontal synchronization signal, vertical synchronization signal) synchronized with the output signal of the output terminal 212, and outputs it to the subsequent stage.
[0074]
[Description of operation]
Subsequently, the circuit operation of the widening circuit 210 will be described with reference to FIG.
First, the control unit 211 switches the selected output of the data selector SE2 to the input terminal B. In this state, the first pixel is input. FIG. 17A is a diagram illustrating a state where the first pixel is scanned and input.
[0075]
Subsequently, the control unit 211 returns the selected output of the data selector SE2 to the pixel memory D1. Further, the selection output of the data selector SE3 is switched to the input terminal B. In this state, the second pixel is input. FIG. 17B is a diagram illustrating a state where the second pixel is scanned and input. In this state, the pixel memories D <b> 1 to D <b> 4 store a pixel row in which pixel folding is added to the left end of the image.
[0076]
At this time, that is, at the time of the [m / 2] th forward feeding, the output of the widening circuit 210 is started. The control unit 211 starts outputting a vertical synchronizing signal, a horizontal synchronizing signal, and a pixel clock to a subsequent stage (the pixel extracting circuit 110 and the like) to notify the start of the output of the image data. Thereafter, the image data is output (horizontal scanning) from the output terminal 212 every one pixel clock.
[0077]
FIG. 17C is a diagram illustrating a state where the horizontal scanning input for one row ((M−4) pixels) to the input terminal B is completed. When detecting the completion of the horizontal scanning input based on the horizontal synchronization signal, the control unit 211 switches the selected output of the data selector SE1 to the output of the pixel memory D1. In this state, when one pixel is forwarded, the state shown in FIG. 17D is obtained. Note that this operation can also be realized by stopping the data update of the pixel memory D1.
[0078]
Subsequently, the control unit 211 switches the selected output of the data selector SE1 to the output of the pixel memory D3. In this state, when one pixel is forwarded, the state shown in FIG. In this state, the pixel memory D1 to D4 stores a pixel row in which pixel folding is added to the right end of the image.
When a total of M pixel values are output from the output terminal 212, the horizontal scanning output for one row is completed.
[0079]
Subsequently, in response to the input of the horizontal synchronization signal of the next row, the widening circuit 210 starts processing again. When detecting the first effective pixel (first pixel) of the next row, the control unit 211 takes in the first pixel of the next row from the input terminal B and stores it in the pixel memory D1. From this state, the processing of the next line starts.
By repeating the above operation for the number of lines, image data in which pixel wrapping is added to the left and right ends of the image is scanned and output from the output terminal 212.
By scanning and inputting the image data thus output to the input terminal A of the pixel extraction circuit 110, a pixel block in which pixel folding is added to the upper, lower, left and right ends of the image is obtained from the output terminal 112 of the pixel extraction circuit 110. It becomes possible.
[0080]
<< Effects of this embodiment >>
As described above, by using the pixel extraction circuits 100 and 110, it is possible to extract a pixel block while adding pixel wrapping to the upper and lower ends of an image.
[0081]
Further, by adding the widening circuits 200 and 210 in front of the pixel extracting circuits 100 and 110, it is possible to add pixel wrapping to the left and right ends of the image. As a result, it is possible to extract a pixel block while adding pixel wrapping to the upper, lower, left, and right ends of the image.
[0082]
In particular, in such a circuit configuration, "folding of pixels at left and right ends", "folding of pixels at upper and lower ends", and "extraction of pixel blocks" are performed by a kind of pipeline type work. Therefore, it is possible to achieve a high processing speed while having complicated processing contents including pixel folding.
[0083]
Further, in such a circuit configuration, a pixel block including a pixel turn is output in a correct scanning order. Therefore, the subsequent processing unit (such as the color interpolation unit 18) can process the sequentially output pixel blocks by a pipeline type work. Therefore, the processing time required for the entire processing can be further reduced.
[0084]
In addition, the widening circuits 200 and 210 according to the present embodiment insert pixel wraps at the left and right ends in units of rows in the flow of serial pixel values by horizontal and vertical scanning. Therefore, there is no need to provide a plurality of circuits for widening as many as the number of delay stages as in the conventional example. Therefore, a simple circuit configuration is realized.
[0085]
Further, such a circuit configuration is not limited to the size of the pixel block described above. That is, since a generalized circuit design is possible as described in the claims, it is possible to design a circuit flexibly corresponding to the pixel numbers n and m of the pixel block.
[0086]
In such a circuit configuration, inside the pixel extraction circuit (or the widening circuit), the control unit generates a synchronization signal for a subsequent stage in synchronization with a control operation of generating a pixel block. Therefore, there is no need to separately generate a synchronization signal for the subsequent stage when installing the pixel extraction circuit (or the widening circuit). In other words, it is only necessary to insert the pixel extraction circuit (or the widening circuit) as a functional component into the signal path of the image signal, which greatly facilitates the design of the entire circuit system.
[0087]
Further, in the electronic camera 11 of the present embodiment, the pixel extraction circuits 17 and 22 generate pixel blocks including upper and lower pixel turnarounds. Therefore, the conventional problem that the draft image data is significantly narrowed in the vertical direction by the signal processing can be improved.
[0088]
Further, in the electronic camera 11 of the present embodiment, the complicated process of adding the pixel folding is performed in each of the pixel extraction circuits 17 and 22, but the pipeline type work is not particularly interrupted. In particular, the draft image data undergoes high-speed signal processing along with the pipeline type work. As a result, the display time lag of the viewfinder can be extremely reduced. Therefore, the electronic camera 11 that is very easy to use is realized when the user determines the shooting composition while looking at the viewfinder (including the monitor screen).
[0089]
Further, the electronic camera 11 of the present embodiment does not temporarily store the draft image data in the frame memory during the image processing of the draft image data. Therefore, the number of times of reading and writing of the frame memory during the long viewfinder display period is significantly reduced, and the power consumption of the electronic camera 11 can be significantly reduced. As a result, the battery consumption of the electronic camera 11 is suppressed, and the usable time of the electronic camera 11 can be further increased.
[0090]
In addition, since there is no extra reading / writing of the frame memory, there is a merit that the traffic of the image data bus does not increase.
[0091]
<< Supplementary information of the embodiment >>
In the above-described embodiment, the case where the pixel extraction circuit is mounted on the electronic camera has been described. However, the imaging device of the present invention is not limited to this. Generally, the imaging device may be any imaging device that performs signal processing on a pixel block basis. For example, a scanner device may be used.
[0092]
In the above-described embodiment, it is preferable that the number of delay pixels of the line memory can be changed by providing an intermediate tap in the line memory. In such a circuit configuration, it is possible to cope with a change in the number of horizontal pixels of the input image by changing the number of delay pixels of the line memory. As a result, a common pixel extraction circuit can be used by switching the number of delay pixels even when image data having different numbers of horizontal pixels is input.
[0093]
In the embodiment described above, an output circuit for partially extracting the pixel value of the pixel memory may be provided. With such an output circuit, it is also possible to generate pixel blocks having different sizes, shape ranges, and pixel distributions, such as extracting a pixel block of 5 pixels × 3 pixels from a pixel block of 5 pixels × 5 pixels.
[0094]
【The invention's effect】
As described above, the pixel extraction circuit of the present invention extracts a pixel block while adding pixel wrapping to at least the upper and lower ends of an image.
In particular, in this pixel extraction circuit, two types of operations, "pixel folding" and "pixel block extraction" are performed at high speed by a flow operation.
Further, the pixel extraction circuit according to the present invention can output a pixel block including pixel wrapping in a correct scanning order while performing complicated processing for performing pixel wrapping. Therefore, in the subsequent stage, the pixel blocks can be processed in the scanning order, and high-speed pipeline-type signal processing can be easily realized.
[Brief description of the drawings]
FIG. 1 is a schematic block diagram of an electronic camera 11 according to an embodiment.
FIG. 2 is a diagram showing a circuit of a pixel extraction circuit 100 for extracting a 5 × 5 pixel block.
FIG. 3 is a diagram illustrating the operation of the pixel extraction circuit 100.
FIG. 4 is a diagram illustrating the operation of the pixel extraction circuit 100.
FIG. 5 is a diagram illustrating the operation of the pixel extraction circuit 100.
FIG. 6 is a diagram illustrating the operation of the pixel extraction circuit 100.
FIG. 7 is a diagram showing a circuit of a pixel extraction circuit 110 for extracting a 4 × 4 pixel block.
FIG. 8 is a diagram illustrating the operation of the pixel extraction circuit 110.
FIG. 9 is a diagram illustrating the operation of the pixel extraction circuit 110.
FIG. 10 is a diagram illustrating the operation of the pixel extraction circuit 110.
11 is a diagram illustrating the operation of the pixel extraction circuit 110. FIG.
FIG. 12 is a diagram showing a widening circuit 200.
FIG. 13 is a diagram illustrating the operation of the widening circuit 200.
FIG. 14 is a diagram illustrating an additional situation of pixel folding.
FIG. 15 is a diagram illustrating an additional situation of pixel folding.
FIG. 16 is a diagram showing a widening circuit 210.
FIG. 17 is a diagram illustrating the operation of the widening circuit 210.
[Explanation of symbols]
11 Electronic camera
12 Shooting lens
13 Image sensor
14 Timing Generator
15 A / D converter
16 signal processing unit
16a Image memory
17,22,100,110 Pixel extraction circuit
18 color interpolation unit
19 Color converter
21 Resolution converter
23 Spatial filter unit
24 Image display section
26 Color difference thinning section
28 Compression unit
29 Recorder
30 LCD monitor with built-in camera
31 TV monitor (external)
101, 111, 201, 211 control unit
200,210 Widening circuit

Claims (7)

A pixel extraction circuit for extracting pixel blocks of n pixels by m pixels in the scanning order from image data consisting of pixel values of N rows by M columns, where n is an odd number and N> n ≧ 3 , M> m ≧ 2),
An input terminal A to which the image data is scanned and input;
(N × m) pixel memories for holding the pixel values;
(N−1) line memories holding the (M−m) pixel values;
[(N + 1) / 2] data selectors for selectively outputting the pixel values;
Starting from the input terminal A, one line is arranged in a repetition order of [one data selector, one pixel memory, one line memory, one pixel memory, and one line memory] A connecting road connecting to
An output terminal for outputting the (n × m) pixel values held by the pixel memory as the pixel block;
A control unit for sequentially transmitting the pixel value to the path of the connection path,
The control unit includes:
During the scanning input of the P-th row (where (n + 1) / 2 ≧ P ≧ 2) of the image data, the output of the P-th data selector counted from the input terminal A side is switched to the input terminal A,
After the input of the image data is completed, the output of the first data selector counted from the input terminal A side is (2Q) during the forward period of the Q-th row (where (n-1) / 2 ≧ Q ≧ 1). A pixel extraction circuit, wherein the output is switched to the output of the first line memory. A pixel extraction circuit for extracting pixel blocks of n pixels by m pixels in the scanning order from image data consisting of pixel values of N rows and M columns, where n is an even number and N> n ≧ 2 , M> m ≧ 2),
An input terminal A to which the image data is scanned and input;
(N × m) pixel memories for holding the pixel values;
(N−1) line memories holding the (M−m) pixel values;
[(N + 2) / 2] data selectors for selectively outputting the pixel values;
With the input terminal A as a starting point, one data selector, m pixel memories, and one line memory are connected, and [one data selector, m pixel memories, A connection path connecting the one line memory, the m pixel memories, and the one line memory in a line in a repeating order;
An output terminal for outputting the (n × m) pixel values held by the pixel memory as the pixel block;
A control unit for sequentially transmitting the pixel value to the path of the connection path,
The control unit includes:
During the scan input of the P-th row (where n / 2 ≧ P ≧ 1) of the image data, the output of the (P + 1) -th data selector counted from the input terminal A side is switched to the input terminal A,
After the input of the image data is completed, the output of the first data selector counted from the input terminal A side is output from the (2Q-1) th line during the forward period of the Qth row (where n / 2 ≧ Q ≧ 1). A pixel extraction circuit for switching to an output of the line memory. The pixel extraction circuit according to claim 1 or 2,
Before the input terminal A,
A widening circuit is provided that widens original image data consisting of pixel values of N rows and M columns by folding pixels at both ends of each row into the image data of N rows and M columns. (However, s = m-1 when m is an odd number, s = m when m is an even number)
A pixel extraction circuit characterized in that: The pixel extraction circuit according to claim 3,
The widening circuit when m is odd is:
An input terminal B for scanning and inputting original image data composed of pixel values of N rows × (M−m + 1) columns;
M pixel memories for holding the pixel values,
[(M + 1) / 2] data selectors for selecting and outputting the pixel values;
A connection path connecting the input terminal B as a starting point in a line in a repeating order of [one data selector and two pixel memories];
An output terminal for providing the pixel value held by the m-th pixel memory from the input terminal B to the input terminal A;
A control unit for sequentially transmitting the pixel value to the path of the connection path,
The control unit includes:
At the time of L-th (where (m + 1) / 2 ≧ L ≧ 2) forward feeding from the start of horizontal scanning of the original image data, the output of the L-th data selector counted from the input terminal B side is switched to the input terminal B. ,
At the time of the R-th forward feeding (where (m-1) / 2 ≧ R ≧ 1) from the end of the horizontal scanning of the original image data, the output of the first data selector counted from the input terminal B side is changed to the (2R) th A pixel extraction circuit for switching to the output of the pixel memory. The pixel extraction circuit according to claim 3,
The widening circuit when m is an even number,
An input terminal B for scanning and inputting original image data composed of pixel values of N rows × H (M−m) columns;
M pixel memories for holding the pixel values,
[(M + 2) / 2] data selectors for selectively outputting the pixel values;
With the input terminal B as a starting point, one data selector and one pixel memory are connected, and further, one data selector and two pixel memories are connected in a line in a repeating sequence of [one data selector and two pixel memories]. Connecting road,
An output terminal for providing the pixel value held by the m-th pixel memory from the input terminal B to the input terminal A;
A control unit for sequentially transmitting the pixel value to the path of the connection path,
The control unit includes:
At the time of the L-th (m / 2 ≧ L ≧ 1) sequential feed from the start of horizontal scanning of the original image data, the output of the (L + 1) -th data selector counted from the input terminal B side is switched to the input terminal B. ,
At the time of forward R-th (where m / 2 ≧ R ≧ 1) forward from the end of horizontal scanning of the original image data, the output of the first data selector counted from the input terminal B side is changed to the (2R−1) -th A pixel extraction circuit characterized by switching to an output of a pixel memory. An imaging unit that captures a subject image and generates image data;
The pixel extraction circuit according to any one of claims 1 to 5, wherein a pixel block of n vertical pixels x m horizontal pixels is extracted from the image data in a scanning order.
A processing unit that performs signal processing on the pixel block extracted by the pixel extraction circuit as a processing unit,
An image pickup apparatus comprising: an interface unit that performs one of a group consisting of recording, image display, and external output on the image data signal-processed by the processing unit. The imaging device according to claim 6,
The imaging unit has an imaging mode for continuously generating low-resolution and high-speed frame rate draft image data by reducing the number of lines of image data and reading out the data,
The pixel extraction circuit, while performing pixel folding at least at the upper end and lower end of the draft image data, extracts a pixel block of n vertical pixels × m horizontal pixels in the scanning order,
The processing unit, with the pixel block extracted by the pixel extraction circuit as a processing unit, sequentially signal processing the draft image data,
The imaging apparatus according to claim 1, wherein the interface unit sequentially performs a moving image display of the draft image subjected to the signal processing by the processing unit.

Images