JP2000208408A - Chemical amplification resist pattern forming method - Google Patents
Chemical amplification resist pattern forming methodInfo
- Publication number
- JP2000208408A JP2000208408A JP1027399A JP1027399A JP2000208408A JP 2000208408 A JP2000208408 A JP 2000208408A JP 1027399 A JP1027399 A JP 1027399A JP 1027399 A JP1027399 A JP 1027399A JP 2000208408 A JP2000208408 A JP 2000208408A
- Authority
- JP
- Japan
- Prior art keywords
- resist
- pattern
- temperature
- heat
- chemically amplified
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
- G03F7/70466—Multiple exposures, e.g. combination of fine and coarse exposures, double patterning or multiple exposures for printing a single feature
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- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Photosensitive Polymer And Photoresist Processing (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Materials For Photolithography (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体の製造方
法、特にリソグラフィー工程の化学増幅系レジストパタ
ーン形成方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor, and more particularly to a method for forming a chemically amplified resist pattern in a lithography process.
【０００２】[0002]
【従来の技術】微細パターン形成処理において、設計寸
法０．１８μｍレベル以降のデバイスでは、ＫｒＦ光や
ＡｒＦ光を光源に用いたエキシマリソグラフィプロセス
が有望視され、その研究開発が進められている。2. Description of the Related Art In the process of forming a fine pattern, for a device having a design size of 0.18 μm or later, an excimer lithography process using KrF light or ArF light as a light source is considered promising, and research and development thereof are being promoted.
【０００３】露光波長２４８ｎｍのＫｒＦエキシマレー
ザーでは、露光波長よりも微細な最小寸法０．１５μｍ
レベルのパターン形成が要求されるようになり、このよ
うな微細寸法の露光は、従来の露光技術では困難な状況
にある。In a KrF excimer laser having an exposure wavelength of 248 nm, a minimum dimension of 0.15 μm finer than the exposure wavelength is used.
A level pattern formation has been required, and exposure of such fine dimensions is difficult with conventional exposure techniques.
【０００４】特に、コンタクトホールパターンやスペー
スパターンのような抜きパターンでは、ライン系パター
ンに比べ、コントラストが得にくく、解像力やフォーカ
スマージン等のリソグラフィ特性は、劣化してしまう。[0004] In particular, in a blank pattern such as a contact hole pattern or a space pattern, it is difficult to obtain contrast as compared with a line pattern, and lithography characteristics such as resolution and a focus margin deteriorate.
【０００５】そこで、コンタクトホールパターンやスー
ペスパターンなどの抜きパターンは、シュリンクプロセ
スが考えられている。この手法は、実際にデバイス適用
されている技術であり、その手法の概略を図２に示す。Therefore, a shrink process has been considered for a punching pattern such as a contact hole pattern or a superior pattern. This technique is a technique that is actually applied to a device, and an outline of the technique is shown in FIG.
【０００６】すなわち、この手法は、図２（ａ）におい
て、基板１上に酸化膜２を形成し、酸化膜２上に化学増
幅系レジスト３を塗布し、レジスト３の焼きしめとして
プリベークを行う。ついで、マスク４を通して波長２４
８ｎｍの露光光５を照射し、図２（ｂ）のように幅Ｗ１
のコンタクトホールＣを形成する。That is, in this method, in FIG. 2A, an oxide film 2 is formed on a substrate 1, a chemically amplified resist 3 is applied on the oxide film 2, and prebaking is performed as baking of the resist 3. . Then, a wavelength of 24
An exposure light 5 of 8 nm is irradiated, and the width W1 is increased as shown in FIG.
Is formed.
【０００７】そして、図２（ｃ）のように感光性の光と
して先と同じ波長２４８ｎｍの露光光６をレジスト３の
面に全面露光し、その後、ホットプレート７により、図
２（ｄ）のように、レジストの耐熱温度よりも高い温度
で熱処理することによってレジストをだらし、コンタク
トの寸法をＷ２（Ｗ１＞Ｗ２）に縮めるというものであ
る。Then, as shown in FIG. 2 (c), the entire surface of the resist 3 is exposed to exposure light 6 having the same wavelength of 248 nm as photosensitive light, and thereafter, a hot plate 7 is used as shown in FIG. As described above, the heat treatment is performed at a temperature higher than the heat-resistant temperature of the resist, thereby loosening the resist and reducing the dimension of the contact to W2 (W1> W2).
【０００８】[0008]
【発明が解決しようとする課題】しかしながら、上記の
ような手法によるパターン形成方法によるときには、レ
ジストプロファイルの劣化が著しく、また、レジストの
膜減りも大きいため、エッチング耐性に影響が現れると
いう問題がある。However, in the case of using the pattern forming method according to the above-mentioned method, there is a problem that the resist profile deteriorates remarkably and the film of the resist is greatly reduced, thereby affecting the etching resistance. .
【０００９】本発明の目的は、従来の手法に比較して、
パターン形状の劣化がなく、より低温でコンタクト径の
縮小が可能な化学増幅系レジストのパターン形成方法を
提供することにある。The object of the present invention is to
It is an object of the present invention to provide a method for forming a pattern of a chemically amplified resist that can reduce a contact diameter at a lower temperature without deteriorating a pattern shape.
【００１０】[0010]
【課題を解決するための手段】上記目的を解決するた
め、本発明による化学増幅系レジストのパターン形成方
法においては、全面露光処理およびベーク処理を施して
半導体基板上に塗布された化学増幅系レジストに形成し
たコンタクトパターンを縮小する化学増幅系レジストの
パターン形成方法であって、全面露光処理は、レジスト
表面のみを脱保護させることにより、表面と他部分との
耐熱性の温度差を持たせる処理であり、ベーク処理は、
レジストの表面の耐熱温度と、下部の耐熱温度との中間
の温度で半導体基板を熱処理するものである。In order to solve the above-mentioned problems, a method for forming a pattern of a chemically amplified resist according to the present invention comprises a chemically amplified resist applied to a semiconductor substrate by performing an overall exposure process and a baking process. A method of forming a chemically amplified resist pattern for reducing a contact pattern formed on a substrate, wherein the entire surface exposure process is a process of deprotecting only the resist surface so as to have a temperature difference in heat resistance between the surface and other portions. And the baking process is
The heat treatment is performed on the semiconductor substrate at an intermediate temperature between the upper surface temperature of the resist and the lower temperature limit.
【００１１】また、全面露光処理は、レジストに対し、
吸収の大きい波長の光源を用いてレジスト表面のみ脱保
護させ、レジスト表面の耐熱温度を他の部分より高くす
る処理である。[0011] Further, the whole surface exposure processing is performed on the resist.
This is a process in which only the resist surface is deprotected using a light source having a wavelength of large absorption so that the heat resistant temperature of the resist surface is higher than that of other portions.
【００１２】また、全面露光処理は、レジストに対して
吸収のある露光光をレジストの面に全面露光する処理で
ある。The whole-surface exposure process is a process for exposing the entire surface of the resist to exposure light that is absorbed by the resist.
【００１３】また、ベーク処理は、処理温度を制御して
縮小すべきコンタクトパターンの寸法を調整する処理を
含むものである。The baking process includes a process of controlling a processing temperature to adjust a dimension of a contact pattern to be reduced.
【００１４】本発明においては、レジスト表面のみを脱
保護させることにより、表面と他部分との耐熱性の温度
差を持たせることにより、従来の手法に比較してより低
温でコンタクト径の縮小が可能であり、パターンの形状
劣化がなく、エッチング耐性を向上できる。In the present invention, by deprotecting only the resist surface to provide a temperature difference in heat resistance between the surface and other parts, the contact diameter can be reduced at a lower temperature as compared with the conventional method. It is possible to improve the etching resistance without deterioration of the pattern shape.
【００１５】[0015]
【発明の実施の形態】以下に本発明の実施形態を図によ
って説明する。図１（ａ）において、半導体基板１上に
酸化膜２を形成し、酸化膜２上に化学増幅系レジスト３
を塗布し、さらにレジスト３の焼きしめとしてプリベー
クを行う。DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the drawings. In FIG. 1A, an oxide film 2 is formed on a semiconductor substrate 1 and a chemically amplified resist 3 is formed on the oxide film 2.
Is applied, and prebaking is performed as baking of the resist 3.
【００１６】ついで、マスク４を通して露光光５を照射
し、コンタクトパターンとして、図１（ｂ）のように幅
Ｗ１のコンタクトホールＣを形成する。そして、全面露
光処理として、図１（ｃ）のようにレジスト３に対して
吸収のある露光光６をレジスト３の面に全面露光する。Next, exposure light 5 is irradiated through the mask 4 to form a contact hole C having a width W1 as a contact pattern as shown in FIG. Then, as a whole-surface exposure process, as shown in FIG.
【００１７】この全面露光処理によって、残ったレジス
トの表面には、脱保護反応が起こり、レジストの表面
は、レジスト下部に比べ、耐熱性が向上する。その後、
図１（ｄ）において、ベーク処理として、ホットプレー
ト７により、レジスト表面の耐熱温度と、レジスト下部
の耐熱温度との中間の温度で熱処理を行う。このベーク
処理により、熱膨張し、コンタクトホールＣは、寸法Ｗ
２（Ｗ１＞Ｗ２）に収縮する。[0017] By this whole surface exposure treatment, a deprotection reaction occurs on the surface of the remaining resist, and the heat resistance of the resist surface is improved as compared with the lower part of the resist. afterwards,
In FIG. 1D, as a baking process, a heat treatment is performed by a hot plate 7 at a temperature intermediate between the heat resistant temperature of the resist surface and the heat resistant temperature of the lower part of the resist. The baking process causes thermal expansion, and the contact hole C has a dimension W
2 (W1> W2).
【００１８】縮小されるコンタクトパターンの寸法Ｗ２
は、ベーク処理の処理温度を制御することによって、自
在に調整できる。本発明によるパターン形成方法によれ
ば、コンタクトホールや孤立スペースパターンなどのレ
ジストを大部分残したパターンに適用できる。The dimension W2 of the contact pattern to be reduced
Can be freely adjusted by controlling the processing temperature of the baking processing. According to the pattern forming method of the present invention, the present invention can be applied to a pattern such as a contact hole or an isolated space pattern where most of the resist remains.
【００１９】本発明によれば、コンタクトホールパター
ンを形成した後、パターン形成部を本レジストに対して
吸収のある光源を用いて露光を行い、レジスト表面のみ
脱保護反応させる。すると、レジスト表面は脱保護させ
ているので耐熱性が高く、レジスト下部はレジスト表面
よりも低くなる。その中間の温度で熱処理を行うことに
よって、パターンを形状劣化が無く縮小することが出来
る。According to the present invention, after the contact hole pattern is formed, the pattern forming portion is exposed to the present resist using a light source having absorption, and a deprotection reaction is performed only on the resist surface. Then, since the resist surface is deprotected, the heat resistance is high, and the lower part of the resist is lower than the resist surface. By performing the heat treatment at an intermediate temperature, the pattern can be reduced without shape deterioration.
【００２０】[0020]
【実施例】以下に本発明の実施例を示す。 （実施例１）下地基板に絶縁膜のＢＰＳＧを用い、酸化
膜上に化学増幅系レジストとして、東京応化工業社製レ
ジストＴＤＵＲ−Ｐ００９を０．７μｍの厚さに塗布し
た。Examples of the present invention will be described below. (Example 1) A resist TDUR-P009 manufactured by Tokyo Ohka Kogyo Co., Ltd. was applied as a chemically amplified resist to a thickness of 0.7 μm on an oxide film using BPSG as an insulating film as a base substrate.
【００２１】次に、レジスト３の焼きしめとして、９０
℃、９０ｓｅｃのプリベークを行い、露光光源には、露
光波長２４８ｎｍのＫｒＦエキシマレーザーを用いて露
光し、０．２５μｍサイズのコンタクトホールＣを形成
した。そして、本レジストに対し、吸収のある露光波長
１９３ｎｍもＡｒＦエキシマレーザー６を用い、レジス
ト３の面に全面露光した。Next, as baking of the resist 3, 90
Pre-baking was performed at 90 ° C. for 90 seconds, and exposure was performed using a KrF excimer laser having an exposure wavelength of 248 nm as an exposure light source to form a contact hole C having a size of 0.25 μm. Then, the entire surface of the resist 3 was exposed to light using an ArF excimer laser 6 at an exposure wavelength of 193 nm having absorption.
【００２２】さらに、ホットプレートにより、１７０
℃、１２０ｓｅｃベーク処理を行った。この結果、レジ
ストの下部だけが熱膨張してコンタクトパターンが縮小
しレジスト形状の劣化が無く、コンタクトホールは、幅
０．１５μｍサイズに縮小された。Further, 170
A baking treatment was performed at 120 ° C. for 120 seconds. As a result, only the lower part of the resist thermally expanded, the contact pattern was reduced, and there was no deterioration of the resist shape. The contact hole was reduced to a size of 0.15 μm in width.
【００２３】（実施例２）下地基板に絶縁膜のＷＪＳｉ
Ｏ２を用い、基板上に酸化膜を形成し、次いでレジスト
として、住友化学工業社製レジストＰＦＩ−５２を１．
０μｍの厚さに塗布を形成した。(Embodiment 2) An insulating film WJSi was formed on a base substrate.
An oxide film is formed on a substrate using O 2 , and then a resist PFI-52 manufactured by Sumitomo Chemical Co., Ltd. is used as a resist.
The coating was formed to a thickness of 0 μm.
【００２４】さらに、レジストの焼きしめとして９０
℃、９０ｓｅｃのプリベークを行った。続いて、露光波
長３６５ｎｍのｉ線によって０．４０μｍサイズのコン
タクトホールを形成した。Further, 90% of the resist is baked.
Prebaking was performed at 90 ° C. for 90 seconds. Subsequently, a 0.40 μm-sized contact hole was formed with an i-line having an exposure wavelength of 365 nm.
【００２５】そして、本レジストに対して、吸収のある
露光波長２４８ｎｍのＫｒＦエキシマレーザーを用い
て、レジスト部を全面露光処理し、続いて、２００℃、
２４０ｓｅｃのベーク処理を行った。この結果、レジス
ト形状の劣化が無く、コンタクトホールパターンの寸法
は、０．２５μｍサイズに縮小された。Then, the entire resist is exposed to the resist using an absorbing KrF excimer laser having an exposure wavelength of 248 nm.
A baking process was performed for 240 seconds. As a result, the size of the contact hole pattern was reduced to a size of 0.25 μm without deterioration of the resist shape.
【００２６】（実施例３）下地基板に絶縁膜のＢＰＳＧ
を用い、酸化膜上に日本合成ゴム社製レジストＭＥＳＥ
Ｐ−１ＥＧを０．７μｍの厚さに塗布し、レジストの焼
きしめとして１００℃、６０ｓｅｃのプリベークを行っ
た。(Embodiment 3) BPSG of insulating film on base substrate
Using a synthetic MES resist MSE on the oxide film
P-1EG was applied to a thickness of 0.7 μm, and prebaked at 100 ° C. for 60 seconds as a resist bake.
【００２７】続いて、エレクトロンビームによって０．
１２μｍサイズのコンタクトホールを形成した。そし
て、本レジストに対して、吸収のあるＡｒＦエキシマレ
ーザーを用い、レジスト部に全面露光処理した。Subsequently, the electron beam is used for 0.1.
A contact hole having a size of 12 μm was formed. Then, the resist was entirely exposed to light using an absorbing ArF excimer laser.
【００２８】続いて、１５０℃、３００ｓｅｃのベーク
処理を行った。この結果、レジスト形状の劣化が無く、
コンタクトホールパターンの寸法は０．０８μｍサイズ
に縮小された。Subsequently, a baking treatment was performed at 150 ° C. for 300 seconds. As a result, there is no deterioration of the resist shape,
The dimension of the contact hole pattern was reduced to a size of 0.08 μm.
【００２９】[0029]
【発明の効果】以上のように本発明によるときには、レ
ジストに対し、吸収の大きい波長の光源を用いることに
よって、レジスト表面のみ脱保護させ、レジスト表面の
耐熱性を他部分よりも高い温度にすることでレジストの
だれを無くし、縮小された高精度のパターンを形成で
き、レジスト形状の劣化やレジストの膜減りがなく、優
れたエッチング耐性を得ることができる。As described above, according to the present invention, the resist is deprotected only by using a light source having a wavelength having a large absorption, so that the heat resistance of the resist surface is made higher than that of other parts. As a result, dripping of the resist can be eliminated, and a reduced and highly accurate pattern can be formed, and excellent etching resistance can be obtained without deterioration of the resist shape or loss of the resist film.
【図１】本発明の一実施形態を工程順に示す図である。FIG. 1 is a diagram showing an embodiment of the present invention in the order of steps.
【図２】従来の化学増幅レジストパターンの形成工程を
工程順に示す図である。FIG. 2 is a view showing a conventional step of forming a chemically amplified resist pattern in the order of steps.
１ 半導体基板 ２ 酸化膜 ３ レジスト ４ マスク ５ 露光光 ６ 露光光 ７ ホットプレート Reference Signs List 1 semiconductor substrate 2 oxide film 3 resist 4 mask 5 exposure light 6 exposure light 7 hot plate
Claims (4)
半導体基板上に塗布された化学増幅系レジストに形成し
たコンタクトパターンを縮小する化学増幅系レジストの
パターン形成方法であって、 全面露光処理は、レジスト表面のみを脱保護させること
により、表面と他部分との耐熱性の温度差を持たせる処
理であり、ベーク処理は、レジストの表面の耐熱温度
と、下部の耐熱温度との中間の温度で半導体基板を熱処
理するものであることを特徴とする化学増幅系レジスト
のパターン形成方法。1. A method of forming a chemically amplified resist pattern for reducing a contact pattern formed on a chemically amplified resist applied on a semiconductor substrate by performing an overall exposure process and a baking process, wherein the overall exposure process includes: The bake treatment is performed at a temperature intermediate between the heat resistance temperature of the resist surface and the heat resistance temperature of the lower part by deprotecting only the resist surface to give a heat resistance temperature difference between the surface and other parts. A method for forming a pattern of a chemically amplified resist, which comprises heat-treating a semiconductor substrate.
の大きい波長の光源を用いてレジスト表面のみ脱保護さ
せ、レジスト表面の耐熱温度を他の部分より高くする処
理であることを特徴とする請求項１に記載の化学増幅系
レジストのパターン形成方法。2. The whole-surface exposure process is a process in which a resist is deprotected only by using a light source having a wavelength of large absorption to make the resist surface heat resistant temperature higher than other portions. A method for forming a chemically amplified resist pattern according to claim 1.
のある露光光をレジストの面に全面露光する処理である
ことを特徴とする請求項１に記載の化学増幅系レジスト
のパターン形成方法。3. The pattern forming method for a chemically amplified resist according to claim 1, wherein the overall exposure process is a process of exposing the entire surface of the resist to exposure light that absorbs the resist.
すべきコンタクトパターンの寸法を調整する処理を含む
ものであることを特徴とする請求項１に記載の化学増幅
系レジストのパターン形成方法。4. The pattern forming method for a chemically amplified resist according to claim 1, wherein the baking process includes a process of controlling a processing temperature to adjust a dimension of a contact pattern to be reduced.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1027399A JP2000208408A (en) | 1999-01-19 | 1999-01-19 | Chemical amplification resist pattern forming method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1027399A JP2000208408A (en) | 1999-01-19 | 1999-01-19 | Chemical amplification resist pattern forming method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2000208408A true JP2000208408A (en) | 2000-07-28 |
Family
ID=11745720
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1027399A Pending JP2000208408A (en) | 1999-01-19 | 1999-01-19 | Chemical amplification resist pattern forming method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2000208408A (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US7350181B2 (en) | 2003-03-26 | 2008-03-25 | Kabushiki Kaisha Toshiba | Set of masks, method of generating mask data and method for forming a pattern |
| US8091046B2 (en) | 2003-03-26 | 2012-01-03 | Kabushiki Kaisha Toshiba | Set of masks, method of generating mask data and method for forming a pattern |
| US8312396B2 (en) | 2003-03-26 | 2012-11-13 | Kabushiki Kaisha Toshiba | Set of masks, method of generating mask data and method for forming a pattern |
| JP2007201446A (en) * | 2006-01-13 | 2007-08-09 | Hynix Semiconductor Inc | Method for forming fine pattern of semiconductor element |
| US10534266B2 (en) * | 2014-02-24 | 2020-01-14 | Tokyo Electron Limited | Methods and techniques to use with photosensitized chemically amplified resist chemicals and processes |
| KR20160124807A (en) * | 2014-02-24 | 2016-10-28 | 도쿄엘렉트론가부시키가이샤 | Methods and techniques to use with photosensitized chemically amplified resist chemicals and processes |
| KR102402923B1 (en) | 2014-02-24 | 2022-05-27 | 도쿄엘렉트론가부시키가이샤 | Methods and techniques to use with photosensitized chemically amplified resist chemicals and processes |
| US10048594B2 (en) | 2016-02-19 | 2018-08-14 | Tokyo Electron Limited | Photo-sensitized chemically amplified resist (PS-CAR) model calibration |
| US10429745B2 (en) | 2016-02-19 | 2019-10-01 | Osaka University | Photo-sensitized chemically amplified resist (PS-CAR) simulation |
| US10096528B2 (en) | 2016-05-13 | 2018-10-09 | Tokyo Electron Limited | Critical dimension control by use of a photo agent |
| US10522428B2 (en) | 2016-05-13 | 2019-12-31 | Tokyo Electron Limited | Critical dimension control by use of a photo agent |
| US10551743B2 (en) | 2016-05-13 | 2020-02-04 | Tokyo Electron Limited | Critical dimension control by use of photo-sensitized chemicals or photo-sensitized chemically amplified resist |
| US11163236B2 (en) | 2019-08-16 | 2021-11-02 | Tokyo Electron Limited | Method and process for stochastic driven detectivity healing |
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