KR100819647B1 - Method of Manufacturing Semiconductor Device - Google Patents

Abstract

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, forming a lower anti-reflection film including silicon on an etched layer formed on a semiconductor substrate; Forming a photoresist film on the lower anti-reflection film and exposing the light source to an exposure source; Developing the exposed photoresist to form a photoresist pattern; Etching the lower anti-reflection film using the photoresist pattern as a mask to form an anti-reflection film pattern; And etching the etched layer using the anti-reflection film pattern as a mask. In the method of the present invention, by using a lower anti-reflective film containing silicon instead of a conventional organic lower anti-reflective film, it is possible to reduce the size of the pattern in a simple manner without an additional process, and also to reduce the process steps to reduce the overall cost. You can get the effect.

Silicon, Anti-Reflection, Recess Gate

Description

Method of manufacturing semiconductor device {Method of Manufacturing Semiconductor Device}

FIG. 1 is a photograph showing that the outermost dummy pattern becomes poor when a pattern is formed by a conventional semiconductor device manufacturing method, and the defective pattern is displayed in red.

2A through 2E are cross-sectional views illustrating a process of manufacturing a semiconductor device by the method of the present invention.

3A to 3C are pattern photographs illustrating a process of fabricating a semiconductor device by the method of the present invention. FIG. 3A shows a photoresist pattern, FIG. 3B shows a lower anti-reflection film pattern, and FIG. 3C shows a final etched layer pattern.

<Description of the symbols for the main parts of the drawings>

11; Semiconductor substrates 12; Etching Layer,

13; A hard mask layer 14; Antireflection film comprising silicon,

15; Photoresist, 15 '; Photoresist pattern,

14 '; Antireflection film pattern, 13 '; Hard mask pattern,

12 '; Etch layer pattern

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to form a pattern using an anti-reflection film containing silicon instead of a conventional organic anti-reflection film to realize a fine pattern by line width control through slope etching. The present invention relates to a method for manufacturing a semiconductor device.

The recess gate pattern forming process of the DRAM device manufacturing process is a process in which line width is the most important and should implement a minimum pattern size. Currently, devices with a size of less than 60 nm require ultra-fine line widths of about 37 nm, which are addressed by exposure conditions that maximize resolution and the use of suitable photosensitizers. However, improvement is urgent due to insufficient process margin and roughness of the pattern compared to other pattern forming processes. To this end, developing a high resolution photosensitizer is a realistic alternative, but it is difficult to significantly improve the performance of the photosensitizer even if a lot of time and money are invested. Particularly, in case of 54 nm or less devices, the line width required for the recess gate mask is about 29 nm or less. As a result of the simulation possibility of applying ArF photosensitizer, the process margin is insufficient for ArF process and ArF immersion lithography should be used. Patterning is possible (see Table 1 and Table 2).

ArF ASML Scanner Mock Review Results Numerical aperture Exposure condition Primary light efficiency (%) EL (%) Depth of Focus (㎛) MEF Icut 0.93 D8797O90 9.73 One 0.45 ? 0.2232 D8797O60 14.59 1.6 0.46 36 0.2398 D8797O35 25.02 2.3 0.47 18.4 0.2665 D8297O35 17.15 1.8 0.54 26.7 0.2484 D8998O35 36.31 2.8 0.55 14.4 0.2822 D8998O20 55.86 3.9 0.52 8.3 0.339 D8998O15 60.4 4.1 0.45 7.5 0.3533 0.95 D8297O35 42.48 3.2 0.36 11.5 0.3032 D8797O35 61.99 4.1 0.32 7.3 0.3605 D8998O35 77.24 4.4 0.35 6.5 0.375

Simulation Results Using Immersion Lithography Numerical aperture Exposure condition Primary light efficiency (%) EL (%) Depth of Focus (㎛) MEF Icut 1.15 D8095O35 100 5.6 0.19 7.3 0.3053

In the above, the parts shown in italics are the results of the optimum conditions of the ASML 1400 Dry equipment used in the simulation, and the parts shown in bold indicate the conditions that can be processed by the ASML 1400 Dry equipment. In addition, EL and MEF represent Energy Latitude and Mask Error Factor, respectively, and Icut represents threshold value of PAC concentration.

In addition, when the photoresist thermal flow process that is widely applied has a problem that it is difficult to apply a shrink process because the outermost dummy pattern is poor (see FIG. 1). In addition, although the RELACS or SAFIER process can be applied as another pattern shrinkage technology, the technology is complicated and the efficiency is lowered, and the manufacturing cost is increased by using expensive materials, as well as the occurrence of defects. Various problems (defect issue, lack of shrink volume, etc.) are scattered and it is impossible to apply the process immediately.

The present invention has been made to solve the above-mentioned problems in the manufacturing method of a semiconductor device, by forming a pattern using an organic anti-reflection film containing silicon instead of a conventional organic anti-reflection film, the etching resistance is the same in the same process margin It is an object of the present invention to provide a method for manufacturing a semiconductor device which is excellent and can easily adjust the inclination of a pattern.

The manufacturing method of the semiconductor element of this invention is

Forming a lower anti-reflection film including silicon on the etched layer formed on the semiconductor substrate;

Forming a photoresist film on the lower anti-reflection film and exposing the light source to an exposure source;

Developing the exposed photoresist to form a photoresist pattern;

Etching the lower anti-reflection film using the photoresist pattern as a mask to form an anti-reflection film pattern; And

Etching the etched layer using the anti-reflection film pattern as a mask.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

2A through 2E are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention.

Referring to FIG. 2A, a hard mask layer 13, a lower anti-reflection film 14 including silicon, and a photosensitive film 15 are formed on the etched layer 12 formed on the semiconductor substrate 11. At this time, the lower anti-reflection film 14 is preferably formed of a material containing 30 to 40 wt% of silicon.

Referring to FIG. 2B, the photosensitive film 15 is exposed to an exposure source and then developed to form a photosensitive film pattern 15 ′. In this case, the method may further include performing a soft bake process and / or a post bake process after exposure, and in this case, the bake process is preferably performed at 70 to 200 ° C., respectively. In addition, as the exposure source, all light sources having a wavelength of 400 nm or less, specifically ArF (193 nm), KrF (248 nm), EUV (Extreme Ultra Violet), VUV (Vacuum Ultra Violet, 157 nm), E A light source selected from the group consisting of a beam, an X-ray, and an ion beam can be used without limitation, and the exposure process depends on the type of photosensitive agent used, but is usually 15 to 70 mJ / cm 2, preferably 40 mJ / cm 2. It is preferably carried out with exposure energy. Among them, it is preferable to use ArF, KrF or VUV as the exposure source, and more preferably ArF. In addition, the development is preferably carried out using an alkaline developer, wherein the alkaline developer is preferably used in an aqueous solution of tetramethylammonium hydroxide (TMAH) of 0.01 to 5% by weight.

At the time of pattern formation, patterning is preferably performed at an interval of about 40 nm using ArF dry scanner equipment. Subsequently, the pattern size may be adjusted in consideration of a stable process margin during bias and patterning during the etching process.

Referring to FIG. 2C, the anti-reflection film 14 is etched using the photoresist pattern 15 ′ as a mask to form the anti-reflection film pattern 14 ′. In this case, it is preferable to form an anti-reflection film pattern transformed into SiO ₂ by performing a 0 ₂ plasma treatment process to oxidize silicon in the anti-reflection film pattern. The lower anti-reflective film containing silicon has an excellent etching selectivity compared to the photosensitive film, and the inclination of the pattern can be appropriately adjusted by adjusting the etching process. In addition, the anti-reflective film containing silicon has an advantage of superior etching resistance than a conventional organic anti-reflective film, so that the inclination of the pattern can be easily adjusted even when a photosensitive film having the same thickness is used as a barrier. It can be used to overcome the limit resolution at the time of pattern formation using the conventional method. In other words, the desired pattern can be realized by stably realizing a patternable line width that secures a process margin larger than desired and reducing it again in an etching process. Referring to FIGS. 3A and 3B, the inclination of the pattern may be adjusted by etching the anti-reflection film including silicon in the initial photosensitive film pattern.

Meanwhile, preferably, a chemical shrinkage material such as a RELACS material or a SAFIER material may be applied onto the lower anti-reflection film pattern, and when the material is applied, it is baked at a temperature of about 140 to 160 ° C. and then deionized. wash with water). At this time, the shrinkage material on the anti-reflection film pattern 14 'causes a crosslinking reaction to remain around the etched anti-reflection film pattern. Through this process, the line width of the etched pattern is increased, and thus, the pattern space. Will be reduced. Therefore, it is possible to more effectively reduce the line width in the recess gate layer through this method. In the above, RELACS material is a material that reacts with the photosensitive agent to increase the area of the photoresist to form a fine contact hole when the temperature is added, SAFIER material does not react with the photosensitive agent when the temperature is added to physically pull the photosensitive agent It is a material to form a fine contact hole.

Referring to FIG. 2D, the hard mask layer 13 is etched using the lower anti-reflection film pattern 14 ′ as a mask to form a hard mask pattern 13 ′. At this time, the hard mask layer 13 is preferably composed of a double layer of an amorphous carbon layer and an inorganic hard mask layer.

Referring to FIG. 2E, the lower etching layer 13 is etched using the hard mask pattern 13 ′ as a mask to form a desired etching layer pattern 12 ′. 3C shows the final etch layer pattern.

In addition, the present invention provides a semiconductor device manufactured using the manufacturing method.

As described above, in the method of the present invention, by using a lower anti-reflective film containing silicon instead of a conventional organic lower anti-reflective film, the size of the pattern can be reduced in a simple manner without an additional process, and no additional cost is incurred. As a result, the cost can be reduced. In other words, at the current process level, the ArF immersion layer can be patterned using the conventional ArF dry exposure equipment, which reduces one layer of ArF immersion, resulting in substantial investment savings of more than 150 billion on a volume basis. It is expected to be obtained.

Claims (8)

Forming a lower anti-reflection film containing 30 to 40 wt% silicon on the etched layer formed on the semiconductor substrate; Forming a photoresist pattern on the lower anti-reflection film; Etching the lower anti-reflection film using the photoresist pattern as a mask to form an anti-reflection film pattern; And And etching the etched layer using the anti-reflection film pattern as a mask and removing the photosensitive film pattern. delete The method of claim 1, A post bake step is further performed after the soft bake step and the exposure step of the photosensitive film pattern forming step, or a post bake step is further performed after the soft bake step or the exposure step. The method of claim 1, And processing 0 ₂ plasma to the antireflection film pattern to oxidize silicon in the antireflection film pattern to SiO ₂ . The method of claim 1, A method of manufacturing a semiconductor device, characterized in that for further coating the chemical shrinkage material on the antireflection film pattern pattern. The method of claim 5, The chemical shrink material is a semiconductor device manufacturing method characterized in that the RELACS material or SAFIER material. The method of claim 1, And a hard mask layer on the etched layer, wherein the hard mask layer is composed of a double layer of an amorphous carbon layer and an inorganic hard mask layer. A semiconductor device manufactured using the manufacturing method of claim 1.

Images