JP2000207245A - In-circuit emulator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an in-circuit emulator capable of accelerating data transfer speed and executing tracing operation continuously, without any break even at the data transfer time by compressing and storing trace data in a memory. SOLUTION: This emulator is provided with a trace memory 103 and a data compressing circuit 102, and the trace data are compressed and stored in the trace memory 103. The data compression circuit 102 compresses the trace data outputted by a trace control circuit 101 in the tracing operation for decreasing data traffic intensity. Consequently, the trace data can be transferred quickly to a host computer. Consequently, the response of the host computer 2 to the in-circuit emulator 1 can be improved, and the time for which the tracing operation is stopped for transferring the trace data can be shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an in-circuit emulator using a compression technique.

[0002]

2. Description of the Related Art In recent years, in-circuit emulators have been used as devices for debugging programs. In particular, the trace function of the in-circuit emulator is a useful function for debugging because it can leave the execution history of the microcomputer.

Hereinafter, a conventional in-circuit emulator will be described with reference to FIGS.

FIG. 4 is a block diagram showing an example of the configuration of a conventional in-circuit emulator. 2 is a host computer, 3 is a microcomputer, 9 is an in-circuit emulator, 10 is a trace unit, 103 is a memory, and 101 is a trace control. Circuit, 201 is a trace start flag, 202 is a trace data transfer request flag, 501 is an address bus, 502 is a data bus, 503 is a memory address bus, 506 is a memory data output bus, 507 is a host address bus, and 508 is a host data bus , 521 are trace memory data input buses.

Referring to FIG. 4, the conventional in-circuit emulator 9 includes an execution address which is an address when an instruction is executed, a data bus value when the instruction is executed, and signal data required for debugging. Trace data composed of data is transferred to the address bus 501 and the data bus 5
The microcomputer 3 includes a microcomputer 3 having a function of outputting the data via an external device 02 and a tracing unit 10.

The tracing unit 10 has a function of taking in trace data of the microcomputer 3 via the address bus 501 and the data bus 502, a function of decoding the host address bus 507, a trace start flag 201 according to the host data bus 508, and a function of transferring trace data. A function for setting the request flag 202;
A function of outputting trace data including an execution address and execution data from the microcomputer 3 to the trace memory data input bus 521, and an address for reading and writing the trace data to and from the memory 103 are stored in a memory address bus 503.
Memory 103, a function to read trace data via the memory data output bus 506, a function to transfer trace data to the host computer 2, and a function to manage addresses to be output to the memory address bus 503 to fill the memory 103. The trace control circuit 101 has a function of setting the trace start flag 201 to a trace stop state when it is detected that the state has been changed, and further transmitted to the address indicated by the memory address bus 503 via the trace memory data input bus 521. The memory 103 has a function of writing trace data and a function of outputting trace data from the address indicated by the memory address bus 503 to the memory data output bus 506.

The trace control circuit 101 has a trace start flag 20 which is a 1-bit register indicating two states of a trace start state (Low) and a trace stop state (High).
1 and a trace data transfer request flag 202 which is a 1-bit register indicating two states of a trace data transfer state (Low) and a trace data transfer stop state (High).

The host computer 2 outputs an address for setting the trace start flag 201 and the trace data transfer request flag 202 of the trace control circuit 101 to the host address bus 507, and outputs data to the host data bus 508. And a function of reading trace data via the host data bus 508, and is connected to the trace control circuit 101.

The operation of the in-circuit emulator configured as described above will be described below by dividing the operation into 1) a trace operation and 2) a trace data transfer operation.

1) At the time of tracing First, a trace start flag 20 is sent from the host computer 2.
An address for setting 1 to a trace start state is output to the host address bus 507, and data is output to the host data bus 508.

The trace control circuit 101 receives an instruction for setting the trace start flag 201 to a trace start state via the host address bus 507 and the host data bus 508, and at that time, sets the trace data transfer request flag 202 to stop the trace data transfer. If so, the trace start flag 201 is set to the trace start state, and the trace operation is started. However, when the trace data transfer request flag 202 is in the trace data transfer state, the trace operation is not started without setting the trace start flag 201 to the trace start state.

When the tracing operation is started, the trace control circuit 101 takes in the trace data including the execution address and the execution data of the microcomputer 3 via the address bus 501 and the data bus 502, and stores the address for recording in the memory 103. The trace data is output via the memory address bus 503, the trace data is output via the memory data output bus 506, and the trace data is recorded in the memory 103.

When the host computer 2 outputs an address for setting the trace start flag 201 to a trace stop state to the host address bus 507 and outputs data to the host data bus 508, and when the memory address bus 5
When it is detected that the trace data to be recorded in the memory 103 through the memory 03 is full, the trace control circuit 10
1 sets the trace start flag 201 to the trace stop state,
Stop the trace operation.

2) When transferring trace data First, the trace control circuit 101 is sent from the host computer 2.
In order to set the trace data transfer request flag 202 to the trace data transfer state, an address is output via the host address bus 507, and data is output via the host data bus 508. The trace control circuit 101 decodes the host address bus 507 and the host data bus 508,
When an instruction for setting the trace data transfer request flag 202 to the trace data transfer state is received and the trace start flag 201 is in the trace stop state at that time, the trace data transfer request flag 202 is set and the trace data transfer is started. When the trace data is transferred,
The trace control circuit 101 outputs an address for reading trace data from the memory 103 to the memory 103 via the memory address bus 503, reads the trace data from the memory 103 via the memory data output bus 506, and outputs the host data bus 508 To the host computer 2 via.

When the trace control circuit 101 receives an instruction from the host computer 2 via the host address bus 507 and the host data bus 508 to set the trace data transfer request flag 202 to the trace data transfer stop state,
When it is detected that the trace data recorded in the memory 103 has run out via the memory address bus 503, the trace data transfer request flag 202 is set to a trace data transfer stop state, and the trace data transfer operation is stopped.

When the trace control circuit 101 receives an instruction from the host computer 2 for setting the trace data transfer request flag 202 to the trace data transfer state, and the trace start flag 201 is in the trace start state, Then, the trace operation is suspended, the trace data transfer request flag 202 is set to the trace data transfer state, and the trace data transfer is started. When receiving an instruction from the host computer 2 to set the trace data transfer request flag 202 to the trace data transfer stop state,
Alternatively, when the trace data recorded in the memory 103 runs out, the trace data transfer request flag 202
Is set to a trace data transfer stop state, the trace data transfer operation is stopped, and the trace operation is restarted.

FIG. 5 is a block diagram showing the configuration of another example of a conventional in-circuit emulator, wherein 2 is a host computer, 3 is a microcomputer, 11 is an in-circuit emulator, 12 is a trace section, 106 is a trace control circuit, 107 Is a memory, 108 is a memory, 109 is a read selector, 110
Is a NOT circuit, 201 is a trace start flag, 202 is a trace data transfer request flag, 204 is a read / write selection flag, 501 is an address bus, 502 is a data bus, 507 is a host address bus, 508 is a host data bus, and 513 is a memory. Address bus, 514 is a memory address bus, 515 is a read / write select signal line, 516 is a memory data output bus, 517 is a memory data output bus, 519 is a selected memory data output bus, 520 is a read / write select inversion signal line, 522 is This is a memory data branch input bus.

The conventional in-circuit emulator shown in FIG. 5 includes an execution address which is an address at the time of executing an instruction, a data bus value when the instruction is executed, and execution data including signal data required for debugging. The microcomputer 3 has a function of outputting trace data via an address bus 501 and a data bus 502, and the trace unit 12.

The tracing unit 12 has a function of taking in trace data composed of an execution address and execution data of the microcomputer 3 via the address bus 501 and the data bus 502, decodes the host address bus 507, and starts tracing according to the host data bus 508. A function of setting a flag 201, a trace data transfer request flag 202, and a read / write selection flag 204, and a memory data branch input bus 522 for transferring trace data including an execution address and execution data from the microcomputer 3;
Function to output the trace data to one memory 107
A function to output an address for reading / writing to / from the memory address bus 513, a function to output an address to read / write the trace data to / from the other memory 108 to the memory address bus 514, and a function to read / write Is set to the read state (Low), the read signal (Low) is output to the read / write select signal line 515, and the read / write select flag 204 is set to the write state (High).
, The read / write selection signal line 51
5, a function of outputting a write signal (High) to the memory, a function of reading trace data via the selected memory data output bus 519, a function of transferring trace data to the host computer 2, a memory address bus 513, and a switching memory address bus. The address to be output to 514 is managed, and when it is detected that one memory is full at the time of writing the trace data, the trace start flag 201 is set to the trace stop state, and when the transfer of the trace data of the other memory is completed, the read / write is performed. A function that switches the selection flag 204 to the write state if in the read state and switches to the read state if the write state, outputs a signal corresponding to the read / write selection flag 204 to the read / write selection signal line 515, and sets the trace start flag 201 to the trace state. And a trace control circuit 106 having When the signal output via the select signal line 515 is a write signal, the trace data output via the memory data branch input bus 522 is recorded at the address indicated by the memory address bus 513, and the read / write select signal line 515 Has a function of outputting trace data recorded at the address indicated by the memory address bus 513 to the memory data output bus 516 when the signal output through the memory 107 is a read signal.
When the signal output through the read / write selection inversion signal line 520 is a write signal, the memory address bus 51
The trace data output via the memory data branch input bus 522 is recorded at the address indicated by 4, and when the signal output via the read / write select inversion signal line 520 is in the read state, the signal indicated by the memory address bus 514 is indicated. The trace data recorded at the address is transferred to the memory data output bus.
When the memory 108 having a function of outputting to the memory 517 and the read / write selection signal line 515 are read signals, the signal of the memory data output bus 516 is output to the selected memory data output bus 519, and the read / write selection signal line 515 is written. For signals,
A read selector 109 having a function of outputting the signal of the memory data output bus 517 to the selected memory data output bus 519, and outputting a write signal to the read / write inversion signal line 520 when the read / write selection signal 515 is a read signal; A NOT circuit 110 having a function of outputting a read signal to the read / write inversion signal line 520 when the read / write selection signal 515 is a write signal.

The trace control circuit 106 has a trace start flag 20 which is a 1-bit register indicating two states of a trace start state (Low) and a trace stop state (High).
1; a trace data transfer request flag 202 which is a 1-bit register indicating two states of a trace data transfer state (Low) and a trace data transfer stop state (High); a read state (Low) and a write state (High) And a read / write select flag 204 which is a 1-bit register indicating the two states.

Further, the host computer 2 assigns addresses for setting the trace start flag 201, the trace data transfer request flag 202, and the read / write selection flag 204 of the trace control circuit 106 to the host address bus 507.
And has a function of outputting data to the host data bus 508 and a function of reading trace data from the host data bus 508, and is connected to the trace control circuit 106.

The operation of the in-circuit emulator configured as described above will be described below.

First, as an initial setting, a host address bus 507, a host data bus 5
The read / write selection flag 204 is set to a write state via 08. At this time, one memory 107 is in a write state and the other memory 108 is in a read state by a write signal output via the read / write selection signal line 515. The host computer 2 outputs an address and data for setting the trace start flag 201 to a trace start state via the host address bus 507 and the host data bus 508 to the trace control circuit 106.

The trace control circuit 106 is an instruction for decoding the host address bus 507 and the host data bus 508 and setting the trace start flag 201 to a trace start state.
If the trace data transfer request flag 202 is in the trace data transfer stop state at that time, the trace start flag 201 is set to the trace start state, the trace operation is started, and the address bus 501 and the data bus 5 of the microcomputer 3 are started.
02, the trace data including the execution address and the execution data is taken in, and an address for recording in the one memory 107 is stored in the one memory 107 via the memory address bus 513.
Output to the memory data branch input bus
The data is recorded in one memory 107 via 522.

At this time, the read selector 109 is connected to the memory data output bus 5 by the read / write selection signal line 515.
17 is selected, the trace control circuit 106 outputs an address for reading trace data from the other memory 108 to the other memory 108 via the memory address bus 514, and outputs the trace data to the memory data output bus 517,
Read selector 109, selected memory data output bus 519
And transferred to the host computer 2 via the host data bus 508.

When it is detected from one of the addresses to be recorded in one memory 107 that one memory 107 is full, the trace start flag 201 is set to a trace stop state, and the transfer of the trace data in the other memory 108 is stopped. Upon completion, the read / write selection flag 204 is set to a read state. As a result, the read / write selection signal line 51
The read signal output via 5 causes one memory 1
07 is in a read state, the other memory 108 is in a write state, an address to be recorded in the other memory 108 is output to the other memory 108 via a memory address bus 514, and the trace data is output to a memory data branch input bus 522. Through the other memory 108.

At this time, the read selector 109 is connected to the memory data output bus 5 by the read / write selection signal line 515.
16 is selected, the trace data is recorded in the other memory 108, and the trace control circuit 106 outputs an address to be read from the one memory 107 to the one memory 107 via the memory address bus 513, The trace data is read via the memory data output bus 516, the read selector 109, and the selected memory data output bus 519, and is transferred to the host computer 2 via the host data bus 508.

When it is detected from the address to be recorded in the other memory 108 that the other memory 108 is full, the trace start flag 201 is set to the trace stop state, and the trace data of the one memory 107 is When the transfer is completed, the read / write selection flag 204 is set to the write state, one memory 107 is set to the write state, and the other memory 108 is set to the read state. Thereafter, the above operation is repeated.

Even when the trace operation is stopped, the host address bus 507 of the host computer 2
When the trace data transfer request flag 202 is set to the trace data transfer state via the host data bus 508, data is read from either one of the memories in the read state, and the host computer 2 is read via the trace control circuit 106. Transfer the trace data to

When the trace control circuit 106 receives an instruction from the host computer 2 via the host address bus 507 and the host data bus 508 to set the trace start flag 201 to the trace stop state, the trace control circuit 106
201 is set to the trace stop state, and the trace operation is stopped.

[0031]

However, in the configuration of the conventional in-circuit emulator, since the trace data is transferred without compression, the amount of data traffic increases, and the transfer speed between the host computer and the trace control circuit increases. However, since it is slower than the transfer speed in the in-circuit emulator or the transfer speed in the host computer, it takes a lot of time to transfer data to the host computer, and the response from the host computer to the in-circuit emulator becomes poor. At the time of trace data transfer, it is necessary to stop the trace operation, so that there is a problem that the trace operation cannot be performed continuously.

The present invention solves the above-mentioned conventional problem. By providing means for reducing the amount of data traffic, the speed of data transfer between the host computer and the trace control circuit is increased. It is an object of the present invention to provide an in-circuit emulator capable of improving response and performing a trace operation continuously without stopping the trace operation even when transferring trace data.

[0033]

In order to achieve the above object, an in-circuit emulator according to the present invention is an in-circuit emulator capable of compressing trace data and storing the compressed data in a memory. And trace data including an execution address which is an address at the time of execution of the instruction, and a data bus value at the time of execution of the instruction and execution data including signal data necessary for debugging. An arithmetic processing unit, including a trace start flag for starting a trace operation and a trace data transfer request flag for starting trace data transfer, a function of capturing and outputting trace data from the arithmetic processing unit, and A function for outputting an address for reading and writing trace data to the A trace control circuit having a function to read trace data from, connected to said said trace control circuit memory is that a data compression circuit for compressing the trace data.

According to the above configuration, at the time of tracing, the trace data output from the trace control circuit is compressed by the data compression circuit to reduce the amount of data traffic. The transfer can be performed, the response from the host computer to the in-circuit emulator can be improved, and the trace operation stop time required to stop the trace operation for transferring the trace data can be reduced. .

An in-circuit emulator according to the present invention is capable of selecting whether to compress trace data and store it in a memory or to store trace data in a memory without compression. And a memory for recording trace data, an execution address which is an address at the time of instruction execution,
An arithmetic processing unit that outputs trace data consisting of a data bus value when the instruction is executed and execution data including signal data necessary for debugging, a trace start flag for starting a trace operation, and trace data transfer A trace data transfer request flag and a compression selection flag for initiating the trace data, and a function of capturing and outputting the trace data from the arithmetic processing unit and a function of outputting an address for reading and writing the trace data from and to the memory. A trace control circuit having a function of reading trace data from the memory, and a function of outputting a signal indicating whether or not to compress the trace data; a trace control circuit connected to the trace control circuit and the memory to compress the trace data; A data compression circuit for performing The data compression trace data or compressed by the circuit, or those with a selector for selecting whether trace data uncompressed.

According to the above configuration, when the trace data contains many redundant signals during the trace operation and the data traffic volume is reduced by the data compression, the trace data is compressed. When the traffic volume increases, the trace data can be uncompressed, and the data traffic volume transferred to the host computer at the time of the trace data transmission can be prevented from increasing by compressing the trace data.

Further, the in-circuit emulator according to the present invention has two memories, and is capable of compressing and writing trace data to one of the memories and reading the trace data from the other memory at the same time. An in-circuit emulator comprising two memories for recording trace data, an execution address which is an address at the time of execution of an instruction, a value of a data bus when the instruction is executed, and signal data necessary for debugging. An arithmetic processing unit for outputting trace data composed of execution data including the data, a trace start flag for starting a trace operation, a trace data transfer request flag for starting trace data transfer, and a read indicating the read / write state of the memory A write selection flag, and A function to read and write trace data from and to the memory; a function to read trace data from the memory; and a read / write to switch between a read state and a write state of the memory. A trace control circuit having a function of outputting a selection signal; a data compression circuit connected to the trace control circuit and the memory for compressing trace data; and a trace data read from two memories into the trace control circuit. And a selector for selection.

With the above configuration, during the trace operation, one of the memories is set to the read state and the other memory is set to the write state. All the recorded trace data can be read out from the memory and transferred to the host computer. When the memory on the recording side becomes full, the memory that was in the read state is changed to the write state and the memory in the write state is changed to the write state. The trace operation is stopped during the trace data transfer by repeating the operation of switching the read memory to the read state, recording the trace data in the write state memory, reading the trace data from the read state memory, and transferring it to the host computer The trace operation can be performed continuously without the need to Kill.

[0039]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A preferred embodiment of the present invention will be described below with reference to FIGS.

FIG. 1 is a block diagram showing a configuration of an in-circuit emulator according to a first embodiment of the present invention, wherein 1 is an in-circuit emulator, 2 is a host computer, 3 is a microcomputer as an arithmetic processing unit, and 4 is a trace unit. 101, a trace control circuit, 102, a data compression circuit, 103, a memory, 201, a trace start flag, 202, a trace data transfer request flag, 501, an address bus, 502
Is a data bus, 503 is a memory address bus, 504 is a trace data bus, 505 is a memory data input bus, 506 is a memory data output bus, 507 is a host address bus, and 508 is a host data bus.

The in-circuit emulator according to the first embodiment uses an execution address, which is an address when an instruction is executed, and execution data including a data bus value when the instruction is executed and signal data necessary for debugging. The microcomputer 3 has a function of outputting trace data through the address bus 501 and the data bus 502, and a trace unit 4.

The tracing unit 4 has a function of taking in trace data consisting of an execution address and execution data of the microcomputer 3 via the address bus 501 and the data bus 502, decodes the host address bus 507, and starts tracing according to the host data bus 508. A function of setting a flag 201 and a trace data transfer request flag 202; a function of outputting trace data including an execution address and execution data from the microcomputer 3 to a trace data bus 504; A function to output trace data to the memory address bus 503, a function to read trace data via the memory data output bus 506, a function to transfer trace data to the host computer 2, and an address to be output to the memory address bus 503. By managing the When it is detected that became equipped with a trace control circuit 101 having a function of a trace stopped trace start flag 201,
A data compression circuit 102 having a function of reading trace data via the trace data bus 504, compressing the trace data, and outputting the compressed data to the memory data input bus 505;
The memory 103 having a function of writing trace data transmitted via the memory data bus 505 to an address indicated by the memory address bus 503 and a function of outputting trace data from the address indicated by the memory address bus 503 to the memory data output bus 506 And

The trace control circuit 101 also includes a trace start flag 20 which is a 1-bit register indicating two states of a trace start state (Low) and a trace stop state (High).
1 and a trace data transfer request flag 202 which is a 1-bit register indicating two states of a trace data transfer state (Low) and a trace data transfer stop state (High).

The host computer 2 outputs an address for setting the trace start flag 201 and the trace data transfer request flag 202 of the trace control circuit 101 to the host address bus 507, and outputs data to the host data bus. , A function of reading trace data from the host data bus 508, and a function of decompressing the compressed trace data, and are connected to the trace control circuit 101.

The operation of the in-circuit emulator of the first embodiment configured as described above will now be described separately for 1) trace operation and 2) trace data transfer operation.

1) At the time of tracing First, the host computer 2 sends a trace start flag
An address for putting 201 in a trace start state is output to the host address bus 507, and the data is output to the host data bus 5
Output to 08. The trace control circuit 101 receives an instruction to set the trace start flag 201 to a trace start state via the host address bus 507 and the host data bus 508,
If the trace data transfer request flag 202 is in the trace data transfer stop state at that time, the trace operation is started with the trace start flag 201 set to the trace start state.

When the tracing operation is started, the trace control circuit 101 fetches the trace data including the execution address and the execution data of the microcomputer 3 via the address bus 501 and the data bus 502 and records the trace data in the memory 103. Is output via a memory address bus 503, and the trace data is output via a trace data bus 504. When the run length compression method is used, the data compression circuit 102 receives trace data, for example, AAABBBBBCC via the trace data bus 504, compresses the data into A3B5C2, and outputs the compressed data via the memory data bus 505. Other compression methods include the huffman method, arithmetic compression, and LZ method.

The memory 103 records the trace data output from the data compression circuit 102 via the memory data bus 505 at the address output via the memory address bus 503. Further, the host computer 2 outputs an address for setting the trace start flag 201 to the trace stop state to the host address bus 507, and outputs data to the host data bus 508 and to the memory 103 via the memory address bus 503. When it is detected that the trace data to be recorded is full, the trace control circuit
101 sets the trace start flag 201 to the trace stop state and stops the trace operation.

The trace control circuit 101 sends an address for setting the trace start flag 201 from the host computer 2 to the trace start state by the host address bus 507.
When the trace data transfer request flag 202 is in the trace data transfer state when the data is output to the host data bus 508 and the data is output to the host data bus 508, the trace operation is not started without setting the trace start flag 201 to the trace start state.

2) When transferring trace data First, the trace control circuit 101 is sent from the host computer 2.
Via the host address bus 507 and the host data bus 508 to output the address and data for setting the trace data transfer request flag 202 to the trace data transfer state. The trace control circuit 101 decodes the host address bus 507 and the host data bus 508, receives an instruction for setting the trace data transfer request flag 202 to the trace data transfer state, and then, at that time, starts the trace start flag 201
Is in the trace stopped state, the trace data transfer request flag 202 is set to the trace data transfer state, and the trace data transfer is started. In the trace data transfer state, the trace control circuit 101 outputs an address for reading trace data from the memory 103 to the memory 103 via the memory address bus 503, and outputs the trace data from the memory 103 via the memory data output bus 506. And transfers it to the host computer 2 via the host data bus 508.

The host computer 2 decompresses the compressed trace data by hardware or software as needed. Further, the trace control circuit 101 sends a host address bus 507 and a host data bus 508 from the host computer 2.
When an instruction to set the trace data transfer request flag 202 to the trace data transfer stop state via the memory address bus 503 is detected, and when it is detected that the trace data recorded in the memory 103 is exhausted via the memory address bus 503, the trace The trace data transfer operation is stopped by setting the data transfer request flag 202 to the trace data transfer stop state.

The trace control circuit 101 receives an instruction from the host computer 2 for setting the trace data transfer request flag 202 to the trace data transfer state. At this time, if the trace start flag 201 is in the trace start state, the trace operation is started. Is temporarily suspended, the trace data transfer request flag 202 is set to the trace data transfer state, the trace data transfer is started, and when an instruction to set the trace data transfer request flag 202 to the trace data transfer stop state is received from the host computer 2, Or memory 10
When the trace data recorded in 3 runs out,
The trace data transfer request flag 202 is set to the trace data transfer stop state, the trace data transfer operation is stopped, and the trace operation is restarted.

As described above, according to the first embodiment, at the time of tracing, the trace control circuit 1 is controlled by the data compression circuit 102.
By reducing the amount of data traffic by compressing the trace data output from 01, the trace data can be transferred to the host computer 2 at a high speed during the transfer of the trace data. The response can be improved, and the trace operation stop time in which the trace operation must be stopped to transfer the trace data can be reduced.

FIG. 2 is a block diagram showing the configuration of an in-circuit emulator according to a second embodiment of the present invention. Reference numeral 2 denotes a host computer, 3 denotes a microcomputer, 5 denotes an in-circuit emulator, 6 denotes a trace unit, and 102 denotes data compression. Circuit, 103 is memory, 104 is trace control circuit, 10
5 is a selector, 201 is a trace start flag, 202 is a trace data transfer request flag, 203 is a compression selection flag, 501 is an address bus, 502 is a data bus, 503 is a memory address bus, 504 is a trace data bus, and 506 is memory data. An output bus, 507 is a host address bus, 508 is a host data bus, 509 is a compressed trace data bus, 510 is an uncompressed trace data bus, 511 is a select signal line, and 512 is a selector memory data input bus.

The in-circuit emulator according to the second embodiment includes an execution address which is an address at the time of execution of an instruction, a value of a data bus when the instruction is executed, and execution data including signal data necessary for debugging. The microcomputer 3 has a function of outputting trace data to the address bus 501 and the data bus 502, and the trace unit 6.

The tracing unit 6 includes a trace data bus 504
And a data compression circuit 102 having a function of reading the trace data, compressing the trace data, and outputting the compressed trace data to the compressed trace data bus 509, and transmitting the data to the address indicated by the memory address bus 503 via the selector memory data input bus 512. And a memory 103 having a function of writing trace data to be written and a function of outputting trace data from the address indicated by the memory address bus 503 to the memory data output bus 506. And a function of taking in the data via the address bus 501 and the data bus 502, and decoding the host address bus 507 to obtain the host data bus 508.
A trace start flag 201, a trace data transfer request flag 202, and a compression selection flag 203, and a trace data bus 504 and a non-compressed trace data bus 510 from the microcomputer 3 including an execution address and execution data. A function of outputting trace data to the memory 103 via the memory data bus 506, a function of outputting an address for reading / writing trace data to / from the memory 103, a function of reading trace data via the memory data output bus 506, By managing the data transfer function and the address output to the memory address bus 503, when the memory 103 becomes full, the trace start flag 201 is set to the trace stop state, and the compression selection flag 203 is set to Compressed state (Lo
w) outputs a compressed signal (Low) to the select signal line 511 when set, and outputs a non-compressed signal (Low) when set to the uncompressed state (Low). The control circuit 104 is provided.

The trace section 6 further includes a select signal line 51
1 according to the compressed select signal transmitted via the data compression circuit 102 via the compressed trace data bus 509 or the trace control circuit 104
And a selector 105 having a function of selecting whether the data is trace data transmitted through a non-compressed trace data bus 510 and outputting it to a selector memory data input bus 512.

Further, the trace control circuit 104 includes a trace start flag 20 which is a 1-bit register indicating two states of a trace start state (Low) and a trace stop state (High).
1, a trace data transfer request flag 202 which is a 1-bit register indicating two states of a trace data transfer state (Low) and a trace data transfer stop state (High), a compressed state (Low) and an uncompressed state (High ) And a compression flag 203 which is a 1-bit register indicating the two states.

The host computer 2 outputs an address for setting the trace start flag 201, the trace data transfer request flag 202, and the compression selection flag 203 of the trace control circuit 104 to the host address bus 507.
It has a function of outputting data to the host data bus, a function of reading trace data from the host data bus 508, and a function of decompressing compressed trace data, and is connected to the trace control circuit 104.

The operation of the in-circuit emulator according to the second embodiment of the present invention configured as described above will now be described separately for 1) trace operation and 2) trace data transfer operation.

1) At the time of tracing First, an address for setting whether or not to compress the trace data is output from the host computer 2 to the compression selection flag 203 to the host address bus 507, and the data is output to the host data bus 508. Then, the compression selection flag 203 is set and the trace start flag is
An address for putting 201 in a trace start state is output to the host address bus 507, and the data is output to the host data bus 5
Output to 08.

The trace control circuit 104 receives an instruction for setting the trace start flag 201 to the trace start state via the host address bus 507 and the host data bus 508, and at this time, sets the trace data transfer request flag 202 to the trace data transfer stopped state. If so, the trace operation is started with the trace start flag 201 set to the trace start state. When the trace operation starts, the trace control circuit 10
4 fetches trace data including the execution address and execution data of the microcomputer 3 via the address bus 501 and the data bus 502, outputs an address to be recorded in the memory 103 to the memory address bus 503, and traces the trace data. Data bus 504 and uncompressed trace data bus 5
And output to 10. Further, the trace control circuit 104 outputs a compressed signal to the selector 105 when the compression selection flag 203 is in a compressed state for compressing the trace data, and is in a non-compressed state where the trace data is not compressed,
Outputs uncompressed signal.

When receiving the trace data via the trace data bus 504, the data compression circuit 102 compresses the trace data and outputs it to the compressed trace data bus 509. When the selector 105 obtains the compressed signal via the select signal line 511, the selector 105 selects the trace data obtained via the compressed trace data bus 509, and
When a non-compressed signal is obtained via 1, non-compressed trace data obtained via an uncompressed trace data bus 510 is selected and output to the memory 103 via a selector memory data input bus 512.

The memory 103 records the trace data output via the memory data bus 505 at the address output via the memory address bus 503. Also, an address for setting the trace start flag 201 to the trace stop state from the host computer 2 is transmitted to the host address bus.
507 and the data to the host data bus 508 and the memory 103 via the memory address bus 503.
When the trace control circuit 104 detects that the trace data to be recorded in the trace data is full, the trace control circuit 104 sets the trace start flag 201 to the trace stop state and stops the trace operation.

The trace control circuit 104 sends an address for setting the trace start flag 201 from the host computer 2 to the trace start state by the host address bus 507.
When the trace data transfer request flag 202 is in the trace data transfer state when the data is output to the host data bus 508, the trace start flag 20
Does not set 1 to the trace start state and does not start the trace operation.

2) When transferring trace data First, the trace control circuit 104
Via the host address bus 507 and the host data bus 508 to output the address and data for setting the trace data transfer request flag 202 to the trace data transfer state. The trace control circuit 104 decodes the host address bus 507 and the host data bus 508, receives the instruction for setting the trace data transfer request flag 202 to the trace data transfer state, and then, at that time, starts the trace start flag 201
Is set to the trace stopped state, the trace data transfer request flag 202 is set to the trace data transfer state, and the trace data transfer is started. In the trace data transfer state, the trace control circuit 104 outputs an address for reading trace data from the memory 103 to the memory 103 via the memory address bus 503, and
, Via the memory data output bus 506 and transferred to the host computer 2 via the host data bus 508. The host computer 2 decompresses the compressed trace data by hardware or software as needed.

When the trace control circuit 104 receives an instruction from the host computer 2 via the host address bus 507 and the host data bus 508 to set the trace data transfer request flag 202 to the trace data transfer stop state,
When it is detected that the trace data recorded in the memory 103 is exhausted via the memory address 503, the trace data transfer request flag 202 is set to the trace data transfer stop state, and the trace data transfer operation is stopped.

The trace control circuit 104 receives an instruction from the host computer 2 for setting the trace data transfer request flag 202 to the trace data transfer state, and if the trace start flag 201 is in the trace start state at that time, the trace operation is performed. Is temporarily suspended, the trace data transfer request flag 202 is set to the trace data transfer state, the trace data transfer is started, and when an instruction to set the trace data transfer request flag 202 to the trace data transfer stop state is received from the host computer 2, or When there is no more trace data recorded in the memory 103, the trace data transfer request flag 202 is set to the trace data transfer stop state, the trace data transfer operation is stopped, and the trace operation is restarted.

As described above, according to the second embodiment, when a large amount of redundant signals are included in the trace data during the trace operation and the data traffic volume decreases due to the data compression, the trace data is compressed. If the amount of data traffic increases due to compression due to a small number of redundant portions, the trace data can be uncompressed, and the host computer 2 can transfer the trace data when the trace data is transferred.
It is possible to prevent the amount of data traffic to be transferred from being increased by compressing the trace data.

FIG. 3 is a block diagram showing a configuration of an in-circuit emulator according to the third embodiment of the present invention. Reference numeral 2 denotes a host computer, 3 denotes a microcomputer, 7 denotes an in-circuit emulator, 8 denotes a trace unit, and 102 denotes data compression. Circuit, 106 is a trace control circuit, 107 and 108 are memories, 109 is a read selector, 110 is a NOT circuit, 201
Is a trace start flag, 202 is a trace data transfer request flag, 204 is a read / write selection flag, 501 is an address bus, 502 is a data bus, 504 is a trace data bus, 50
7 is the host address bus, 508 is the host data bus, 513
Is the memory address bus, 514 is the memory address bus, 515
Is a read / write selection signal line, 516 is a memory data output bus, 517 is a memory data output bus, 518 is a compressed memory data input bus, 519 is a selected memory data output bus, and 520 is a read / write selection inversion signal line.

The in-circuit emulator according to the third embodiment comprises an execution address which is an address at the time of execution of an instruction, an execution data including a data bus value when the instruction is executed, and signal data necessary for debugging. The microcomputer 3 includes a microcomputer 3 having a function of outputting trace data to an address bus 501 and a data bus 502, and a trace unit 8.

The trace section 8 has a trace data bus 504
A data compression circuit 102 having a function of reading trace data through the memory, compressing the trace data, and outputting the compressed data to a compressed memory data input bus 518;
And a function to capture trace data consisting of the execution address and execution data of the host through the address bus 501 and the data bus 502, decode the host address bus 507, and execute the trace start flag 201 and the trace data transfer request flag 202 according to the host data bus 508. And read / write select flag 2
04, a function of outputting trace data including an execution address and execution data from the microcomputer 3 to the trace data bus 504, and an address for reading / writing the trace data to / from one memory 107. A function to output to the address bus 513, a function to output an address for reading / writing trace data to / from the other memory 108 to the memory address bus 514, and a function to set the read / write selection flag 204 to the read state (Low). If the read / write select flag 204 is set to the write state (High), the read signal (Low) is output to the read / write select signal line 515, (High), a function of reading trace data through the selected memory data output bus 519, and a function of outputting trace data to the host computer 2. The data transfer function and the addresses output to the memory address bus 513 and the memory address bus 514, and when it is detected that the memory is full at the time of writing the trace data, the read / write selection flag 204 is set to the write state if the read state, In addition, a trace control circuit 106 having a function of switching to a read state in a write state and outputting a signal corresponding to the read / write selection flag 204 to a read / write selection signal line 515 is provided.

Further, when the signal output via the read / write selection signal line 515 is a write signal, the trace section 8 outputs the trace output via the compressed memory data input bus 518 to the address indicated by the memory address bus 513. A function of recording data and outputting the trace data recorded at the address indicated by the memory address bus 513 to the memory data output bus 516 when the signal output via the read / write selection signal line 515 is a read signal. One of the memories 107 and the trace data output via the compressed memory data input bus 518 to the address indicated by the memory address bus 514 when the signal output via the read / write selection inversion signal line 520 is a write signal Is recorded, and when the signal output through the read / write selection inversion signal line 520 is a read signal, Resubasu 51
The other memory 108 having the function of outputting the trace data recorded at the address indicated by 4 to the memory data output bus 517, and selecting the signal of the memory data output bus 516 when the read / write selection signal line 515 is a read signal. Output to memory data output bus 519 and read / write select signal line 5
A read selector 109 having a function of outputting a signal of the memory data output bus 517 to the selected memory data output bus 519 when 15 is a write signal, and a read / write inversion signal line when the read / write selection signal line 515 is a read signal. 520
And a NOT circuit 110 having a function of outputting a write signal to the read / write inversion signal line 520 when the read / write selection signal line 515 is a write signal.

The trace control circuit 106 has a trace start flag 20 which is a 1-bit register indicating two states of a trace start state (Low) and a trace stop state (High).
1; a trace data transfer request flag 202 which is a 1-bit register indicating two states of a trace data transfer state (Low) and a trace data transfer stop state (High); a read state (Low) and a write state (High) And a read / write select flag 204 which is a 1-bit register indicating the two states.

The host computer 2 outputs an address for setting the trace start flag 201, the trace data transfer request flag 202, and the read / write select flag 204 of the trace control circuit 106 to the host address bus 507. , A function of outputting data to the host data bus 508, a function of reading trace data from the host data bus 508, and a function of decompressing compressed trace data, and are connected to the trace control circuit 106.

The operation of the thus configured in-circuit emulator of the third embodiment will be described below.

First, as an initial setting, it is temporarily assumed that the host computer 2 sends the host address bus 507 and the host data bus 5
The read / write selection flag 204 is set to a write state via 08. At this time, one memory 107 is in a write state and the other memory 108 is in a read state by a write signal output via the read / write selection signal line 515. The host computer 2 outputs an address and data for setting the trace start flag 201 to a trace start state via the host address bus 507 and the host data bus 508 to the trace control circuit 106.

The trace control circuit 106 is an instruction for decoding the host address bus 507 and the host data bus 508 and setting the trace start flag 201 to a trace start state.
If the trace data transfer request flag 202 is in the trace data transfer start state at that time, the trace start flag 201 is set to the trace start state, the trace operation is started, and the address bus 501 and the data bus 5
02, the trace data including the execution address and the execution data is taken in, and an address to be recorded in one memory 107 is stored in one memory 1 via a memory address bus 513.
07 to the trace data bus 504
Output to the data compression circuit 102 via the
At 02, the trace data is compressed and recorded in the memory 107 via the compressed memory data input bus 518.

At this time, the read selector 109 is connected to the memory data output bus 5 by the read / write selection signal line 515.
17 is selected, and while the trace data is being recorded in one memory 107, an address for reading from the other memory 108 is output to the other memory 108 via the memory address bus 514, and this memory 108 All trace data recorded in the memory data output bus 517
Then, the data is read into the trace control circuit 106 via the read selector 109 and the selected memory data output bus 519, and is transferred to the host computer 2 via the host data bus 508.

Further, the trace control circuit 106 calculates the address of the one memory 107 from the address to be recorded in the one memory 107.
, The read / write selection flag 204 is set to a read state. As a result, the read signal output via the read / write select signal line 515 causes one memory 107 to be in a read state and the other memory 108 to be in a write state. Trace control circuit 106
Switches the address to be recorded in the other memory 108 via the memory address bus 514 to switch the other memory 108
Output the trace data to the compressed memory data input bus
The data is recorded in the memory 108 via the 518.

At this time, the read selector 109 is connected to the memory data output bus 516 by the read / write selection signal line 515.
Is selected, and the trace control circuit 106 outputs an address to be read from the one memory 107 to the one memory 107 via the memory address bus 513, and outputs trace data to the memory data output bus 516 and the memory data output bus 516. The data is read into the trace control circuit 106 via the selector 109 and the selected memory data output bus 519 and transferred to the host computer 2 via the host data bus 508. If it is detected from the address for recording in the other memory 108 that the memory 108 is full, the read / write selection flag 204 is set to the write state, and
In a write state and the other memory 108 in a read state, and thereafter, the above operation is repeated.

The trace control circuit 106 is an instruction for decoding the host address bus 507 and the host data bus 508 and setting the trace start flag 201 to a trace start state. At that time, the trace data transfer request flag 202
When the trace data transfer is stopped, the trace operation is started by setting the trace start flag 201 as the trace start state, and the trace data including the execution address and the execution data is transferred from the address bus 501 and the data bus 502 of the microcomputer 3. The data is captured and recorded in one memory 107. The trace control circuit 106 detects that one memory 107 is full from an address to be recorded in one memory 107, or traces the data from the host computer 2 via the host address bus 507 and the host data bus 508. When receiving an instruction to set the start flag 201 to the trace stop state, the trace operation is stopped with the trace start flag 201 set to the trace stop state.

Even when the trace operation is stopped, the host address bus 507 of the host computer 2
When the trace data transfer request flag 202 is set to the trace data transfer state via the host data bus 508, data is read from the memories 107 and 108 in the read state and traced to the host computer 2 via the trace control circuit 106. Transfer data.

When the trace control circuit 106 receives an instruction from the host computer 2 via the host address bus 507 and the host data bus 508 to set the trace start flag 201 to the trace stop state, the trace control circuit 106
The trace operation is stopped by setting 201 as the trace stop state.

As described above, according to the third embodiment, when one of the pair of memories 107 and 108 is in the read state and the other is in the write state during the trace operation, the traffic data amount is reduced. Therefore, while the trace data is being recorded in one memory, all the recorded trace data can be read from the other memory and transferred to the host computer 2, and the memory on the recording side can be read. When the memory becomes full, the other memory in the read state is switched to the write state, the memory in the write state is switched to the read state, trace data is recorded in the memory in the write state, and trace data is read from the memory in the read state. By repeating the operation of reading and transferring the data to the host computer 2, during the transfer of the trace data, Trace operation without the need to stop, it is possible to perform the tracing operation in succession.

In the third embodiment, the case where there are two memories 107 and 108 has been described as an example. However, the present invention can be similarly carried out when three or more memories are installed.

[0087]

As described above, according to the in-circuit emulator according to the present invention, at the time of tracing, the trace data output from the trace control circuit is compressed by the data compression circuit to reduce the data traffic amount. During the transfer, the trace data can be transferred to the host computer at high speed, the response from the host computer to the in-circuit emulator can be improved, and the trace operation must be stopped to transfer the trace data. Unnecessary trace operation stop time can be reduced.

In the trace operation, when the trace data contains many redundant signals and the data traffic volume is reduced by the data compression, the trace data is compressed. On the contrary, the trace data has a small redundant portion and the data is compressed. When the traffic volume increases, the trace data can be uncompressed, and the data traffic volume transferred to the host computer at the time of the trace data transmission can be prevented from increasing by compressing the trace data.

In the trace operation, one of the plurality of memories is set to the read state and the other memory is set to the write state, and the trace data is recorded in one of the memories because the amount of data traffic is reduced. In the meantime, all the recorded trace data can be read from the other memory and transferred to the host computer 2. When the memory on the recording side becomes full, the memory in the read state is changed to the write state. Switching the memory that was in the write state to the read state, recording trace data in the memory in the write state, reading the trace data from the memory in the read state, and transferring it to the host computer by repeating the operation of transferring trace data It is not necessary to stop the trace operation even during It can be carried out over the scan operation.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an in-circuit emulator according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of an in-circuit emulator according to a second embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of an in-circuit emulator according to a third embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of a conventional in-circuit emulator.

FIG. 5 is a block diagram showing a configuration of a conventional in-circuit emulator.

[Explanation of symbols]

 1, 5, 7 In-circuit emulator 2 Host computer 3 Microcomputer 4, 6, 8 Trace unit 101, 104, 106 Trace control circuit 102 Data compression circuit 103, 107, 108 Memory 105 Selector 109 Read selector 110 NOT circuit 201 Trace start Flag 202 Trace data transfer request flag 203 Compression selection flag 204 Read / write selection flag 501 Address bus 502 Data bus 503, 513, 514 Memory address bus 504 Trace data bus 505 Memory data input bus 506, 516, 517 Memory data output bus 507 Host Address bus 508 Host data bus 509 Compressed data bus 510 Uncompressed trace data bus 511 Select signal line 512 Selector memory data input bus 515 Read / write select signal line 518 Compressed memory data input bus 519 Selected memory data output bus 520 Read / write select inversion Issue

Continuation of the front page (72) Inventor Toru Morikawa 1006 Kazuma Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. F term (reference) 5B042 HH03 HH30 MA04 MA09 MA19 MA20 MC03 MC09

Claims (6)

[Claims] 1. An in-circuit emulator comprising a trace memory and compression means, wherein the trace data is compressed by the compression means and stored in the trace memory. 2. An in-circuit emulator capable of compressing trace data and storing the compressed data in a memory, comprising: a memory for recording trace data; an execution address which is an address at the time of instruction execution; An arithmetic processing unit that outputs trace data consisting of the data bus value when execution is performed and execution data including signal data necessary for debugging, a trace start flag for starting a trace operation, and start of trace data transfer A trace data transfer request flag, a function to capture and output trace data from the arithmetic processing unit, a function to output an address for reading and writing trace data to the memory, and a function to trace data from the memory. A trace control circuit having a function of reading the In-circuit emulator comprising: the data compression circuit for compressing the trace data is connected to said a road memory. 3. A trace memory, a compression means, and a selection for selecting whether to compress the trace data by the compression means and store it in the trace memory, or to store the trace data in the trace memory without compression. And an in-circuit emulator. 4. An in-circuit emulator that enables a user to select whether to store trace data in a memory by compressing the trace data or to store the trace data in a memory without compressing the trace data. Processing unit for outputting trace data including a memory for executing the instruction, an execution address which is an address at the time of execution of the instruction, and a data bus value at the time of execution of the instruction and execution data including signal data required for debugging. A trace start flag for starting a trace operation, a trace data transfer request flag for starting trace data transfer, and a compression selection flag, a function of capturing and outputting trace data from the arithmetic processing unit; A function of outputting an address for reading and writing the trace data to and from the A trace control circuit having a function of reading trace data from a memory and a function of outputting a signal indicating whether or not to compress the trace data; and a trace control circuit connected to the trace control circuit and the memory for compressing the trace data. A data compression circuit, and a selector for selecting, according to a signal from the trace control circuit, the trace data compressed by the data compression circuit or the uncompressed trace data;
An in-circuit emulator comprising: 5. At least two or more trace memories, and a compressing means, wherein the compressing means compresses and writes trace data to one of the trace memories, and at the same time, writes trace data from another trace memory. An in-circuit emulator characterized by a configuration for reading. 6. A memory comprising two memories, wherein trace data is compressed and written to one of the memories,
An in-circuit emulator capable of reading trace data from the other memory, comprising two memories for recording trace data, an execution address which is an address at the time of execution of an instruction, and a time when the instruction is executed An arithmetic processing unit that outputs trace data including the data bus value and execution data including signal data necessary for debugging, a trace start flag for starting a trace operation, and trace data for starting trace data transfer A transfer request flag and a read / write selection flag indicating a read / write state of the memory; a function of taking in and outputting trace data from the arithmetic processing unit; and outputting an address for reading / writing the trace data to / from the memory. Function and read trace data from the memory A trace control circuit having a function of outputting a read / write select signal for switching between a read state and a write state of the memory; and data connected to the trace control circuit and the memory for compressing trace data. An in-circuit emulator comprising: a compression circuit; and a selector for selecting trace data to be read from the two memories into the trace control circuit.