JP2000201161A - Arbitration control circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To arbitrate plural bus acquisition requests by flexibly setting up the bus using priority of plural devices connected to a bus in accordance with the bus using states of respective devices. SOLUTION: A priority decision part 103 receives a bus acquisition request signal 106 outputted from each of devices connected to a bus, extracts a counter value 110 indicating the bus acquisition expression frequency of respective devices from an arbitration counter part 101 and the priority data 111 of respective devices which are previously set up in a priority setting register part 102 and decides the priority of respective devices. The decision part 103 decides a device having the largest counter value as a target to which permission for using the bus is to be provided. Then the decision part 103 sends the arbitration ID of the decided device to a system bus 105 and outputs a counter reset signal 107 for resetting the counter value of the device acquiring the bus to the counter part 101.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an arbitration control circuit for controlling a bus acquisition request of a plurality of devices connected to a bus in information equipment such as a computer device and an information processing device.

[0002]

2. Description of the Related Art In information devices such as computer devices and information processing devices, when a plurality of devices connected to a bus simultaneously receive a bus acquisition request, an arbitration priority change for arbitrating based on the priority of each device. A method is used.

Conventionally, this type of arbitration priority changing method is disclosed in, for example, Japanese Patent Application Laid-Open No. 61-267160, in which a device having a high bus use priority in an arbitration bus uses the bus for a long time. In such a case, the waiting time is measured using a counter or a timer, and the right to use the bus is forcibly changed to another device with a lower priority in a certain time. This prevents the exclusive use of the bus of a high priority device.

FIG. 3 is a block diagram showing a configuration of an information device using a conventional arbitration priority changing method. In the information device shown in FIG. 3, a plurality of devices (device A30)
1, device B302) is connected to the bus 303. An arbitration unit 304 for controlling bus acquisition requests from a plurality of devices is connected to the bus 303. The arbitration unit 304 includes a counter unit 305 for counting the time during which the right to use the bus is acquired, and a bus use for a plurality of devices A301 and B302 connected to the bus 303 according to the count value of the counter unit 305. A priority determination unit 306 for controlling permission is provided.

The arbitration unit 304 shown in FIG. 3 operates as follows. Here, it is assumed that the device A301 has a higher priority than the device B302. When the device A301 makes a bus use request while the device B302 is using the bus, the priority determination unit 306 withdraws the bus use permission for the device B302 and gives the device A301 a bus use permission. At this time, the counter unit 305 starts counting at the same time when the right to use the bus is transferred to the device A301.

When the device A301 occupies the bus for a long time, when the count value of the counter unit 305 exceeds a preset time limit, the counter unit 305 activates the TC signal 307 to the priority determination unit 306. . Accordingly, the priority determination unit 306 withdraws the bus use permission for the device A301 and gives the device B302 a bus use permission. As a result, the lower priority device B30
2 can use the bus.

[0007]

In this conventional arbitration priority changing method, even when a device having a high arbitration priority occupies a bus for a long time,
When there is a bus use request from a device with a low priority, the bus use right can be forcibly transferred to a device with a low priority when the time limit counted by the counter unit 305 is reached. Arbitration processing that does not cause a bus hold state can be expected.

However, in the conventional arbitration priority changing method, it is difficult to apply to a system in which three or more devices are connected, and once arbitration is performed, the right to use the bus is forcibly taken up in the middle. In some cases, the efficiency may deteriorate, so that forcibly withdrawing the bus use permission of a high-priority device at the time when the time limit expires may reduce the processing efficiency of the system.

In view of the above, the present invention has been made in consideration of the above-mentioned points, and a bus acquisition request is flexibly set for a plurality of devices connected to a bus in accordance with the bus use status of each device. It is an object of the present invention to provide an arbitration control circuit capable of performing arbitration for the arbitration.

[0010]

In order to solve the above-mentioned problems, the arbitration control circuit of the present invention counts the number of bus acquisition requests from a plurality of devices connected to a bus for each device, Priorities can be arbitrarily set in advance for each of the devices. When a bus acquisition request is issued from a device connected to the bus, the device that has the largest counter value among the devices that output the bus acquisition request is granted a bus use right, and the device with the largest counter value is granted. When there are a plurality of devices, the right to use the bus is given to the device having the highest preset priority among the devices having the largest counter value.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of an arbitration control circuit according to the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing a configuration of an arbitration control circuit 100 according to an embodiment of the present invention. As shown in FIG. 1, the arbitration control circuit 100 includes an arbitration counter unit 101, a priority setting register 102, a priority determination unit 103, and a CPU 104. Arbitration control circuit 100
Performs arbitration in response to a bus acquisition request from a plurality of devices (not shown) connected to the system bus 105 by an arbitration priority change method.

The arbitration counter unit 101
A bus acquisition request signal 106 from a device connected to the bus 105 is input via the system bus 105, and the number of bus acquisition assertions of each device is counted based on the bus acquisition request signal 106. Arbitration counter 1
In 01, an n-bit counter is provided for each of the devices connected to the system bus 105. Therefore, if the total number of devices participating in arbitration connected to the system bus 105 is m, then n
Bit × m counters are provided.

The priority setting register 102 stores the arbitration priority of the devices connected to the system bus 105, and the arbitration priority for each device is set by the CPU 104. For example,
When the number of arbitration priority ranks is k, m
There are provided m bits × k storage units for storing arbitration priorities of the devices.

The priority judging section 103 receives the bus acquisition request signal 106 output from the device connected to the bus 105, and in response to the bus acquisition request signal 106, sets the arbitration priority set in the priority setting register 102 and the arbitration counter section. It has a function of determining the priority with reference to the n-bit arbitration frequency (bus acquisition assertion frequency) 101 and transmitting identification information (arbitration ID) indicating the bus acquisition device onto the bus 105. Bus 105
Can determine whether or not the device has been granted the right to use the bus, based on the arbitration ID sent to the bus 105.

The CPU 104 (rewriting means) operates based on a program stored in a memory (not shown) to rewrite the arbitration priority for each device stored in the priority setting register 102 for arbitrarily setting. Functions as a device.

Next, the operation of the arbitration control circuit shown in FIG. 1 will be described. Here, it is assumed that four devices (m = 4) are connected to the bus 105 and the device names are a, b, c, and d, respectively.

First, the CPU 104 is connected to the system bus 10
Arbitration priorities are set in advance in the priority setting register unit 102 for each of the m devices connected to 5. For example, the CPU 104 includes devices a, b, c,
It is assumed that higher priorities are set in the order of d.

The CPU 104 has a counter value C corresponding to each device of the arbitration counter unit 101.
a, Cb, Cc, and Cd are reset to “0”.

Assume that a bus acquisition request signal 106 is output from each device that wants to acquire a bus connected to the system bus 105 in a bus arbitration cycle for arbitrating a bus acquisition request.

When each of the bus acquisition request signals 106 becomes active, the n-bit counter corresponding to the bus acquisition request signal 106 provided in the arbitration counter unit 101 is counted up by one.

Upon receiving the bus acquisition request signal 106, the priority determining section 103
From 1, the counter value 110 of each device is extracted, and the data 111 of the priority set for each device is extracted from the arbitration priority setting register unit 102.

At this time, the arbitration counter 1
The counter value of 01 is Ca, Cc, Cd = 0, Cb = 1
And That is, it indicates that the bus acquisition request signal 106 has been output from the device b.

The priority judging unit 103 checks the device requesting the bus acquisition based on the count value of each device obtained from the arbitration counter unit 101. Here, the priority determination unit 103 determines that only the device b has issued the bus acquisition request, and determines the arbitration ID of the device b.
On the system bus 108.

At the same time, the arbitration counter unit 101 is notified by a counter reset signal 107 to reset the counter value of the device b to "0". The arbitration counter unit 101 sets the count value of the device b to “0” in response to the counter reset signal 107 from the priority determination unit 103.

The device b recognizes that the right to use the bus has been acquired by referring to the arbitration ID sent to the bus 105, and executes a bus cycle. When the bus cycle of the device b ends, the arbitration process end signal 109 is notified from the device b to the priority determination unit 103. This completes one bus use cycle.

Next, it is assumed that a bus arbitration cycle is performed again, and a bus acquisition request signal 106 is output from each device that wants to acquire a bus.

Upon receiving the bus acquisition request signal 106, the priority determination section 103
From 1, the counter value 110 of each device is extracted, and the data 111 of the priority set for each device is extracted from the arbitration priority setting register unit 102.

At this time, the arbitration counter 1
The values of 01 are Ca = 1, Cb = 0, Cc = 1, C
It is assumed that d = 1. That is, it indicates that the bus acquisition request signal 106 has been output from the devices a, c, and d.

In this case, the priority judging unit 103 determines the device having the highest priority set in the arbitration priority setting register unit 102 among the devices a, c, and d that output the bus acquisition request signal 106. Judge that
The arbitration ID of the device a
Send up. At the same time, the priority determination unit 103 notifies the arbitration counter unit 101 by a counter reset signal 107 so as to reset the counter value of the device a to “0”.

The device a recognizes that the right to use the bus has been acquired by referring to the arbitration ID sent to the bus 105, and executes a bus cycle. When the bus cycle of the device a ends, the priority determination unit 103 is notified of the arbitration process end signal 109 from the device a. This completes the second bus use cycle. At this time, the count values of the arbitration counter unit 101 for each device are Ca = 0, Cb, respectively.
= 0, Cc = 1, Cd = 1.

Next, it is assumed that the third bus arbitration cycle is performed and the bus acquisition request signal 106 is output from all of the devices a, b, c, and d. In this case, the counter value for each device of the arbitration counter unit 101 is counted up by one, and therefore a = 1, b = 1, c = 2, and d = 2.

Upon receiving the bus acquisition request signal 106, the priority determination section 103
From 1, the counter value 110 of each device is extracted, and the data 111 of the priority set for each device is extracted from the arbitration priority setting register unit 102.

The priority determining unit 103 determines the device to which the bus usage is given by giving priority to the counter value 110 of each device over the priority of each device.

At this time, the device having the highest priority set in the priority setting register 102 among the devices which have transmitted the bus acquisition request signal 106 is the device a. However, since there are devices c and d having a count value larger than the count value of the arbitration counter 101 for the device a, the device a is not given priority as in the previous arbitration cycle.

The priority judging section 103 sets the devices c and d having the largest count value of the arbitration counter 101.
Is determined based on the priority setting register 102. Here, since the priority of the device c is higher, the priority determination unit 103 sends the arbitration ID of the device c onto the system bus 108, and simultaneously transmits the counter value of the device c to the arbitration counter unit 101 as “ The counter reset signal 107 notifies the counter to reset to “0”.

The device c recognizes that the right to use the bus has been acquired by referring to the arbitration ID sent to the bus 105, and executes a bus cycle. Device c
Is completed, the arbitration process end signal 109 is notified from the device c to the priority determination unit 103. This completes the third bus cycle.

Hereinafter, bus arbitration is performed for the bus acquisition request signal 106 from each device connected to the bus 105 in the same manner.

As described above, the priority determination unit 103
The device that gives priority to the acquisition of the right to use the bus is determined according to not only the priority of each device preset in the priority setting register 102 but also the number of bus acquisition assertions from each device counted by the arbitration counter 101. I do. That is, although the bus use right is basically given based on the priority set in the priority setting register 102, the bus acquisition assertion counted by the arbitration counter 101 more than the priority set in the priority setting register 102 Since the bus use right is given with higher priority to the device having the largest number of times, appropriate arbitration according to the arbitration situation is realized instead of biased arbitration in accordance with a preset priority. This arbitration priority change method can be applied to any number of devices connected to the bus 105, and the right to use the bus is not forcibly taken up in the middle, thereby lowering the processing efficiency of the system. Not even.

Next, another embodiment will be described with reference to FIG.

Arbitration control circuit 2 shown in FIG.
00 denotes an arbitration counter unit 201, a priority setting register 202, a priority determination unit 203, a CPU 20
4 (priority setting means). The arbitration control circuit 200 shown in FIG. 2 performs arbitration based on the priority set in the priority setting register 202 and the count value counted by the arbitration counter unit 201, similarly to the arbitration control circuit 100 shown in FIG. They do what they do and have the same basic functions. The difference is that the arbitration control circuit 200 is configured to notify the CPU 204 of the counter value notified from the arbitration counter unit 101 to the priority determination unit 103 in FIG.

The CP of the arbitration control circuit 200
When the bus acquisition request 206 is input to the arbitration counter unit 201, the U 204 directly inputs the counter value (the number of bus acquisition assertions) of each device counted in the arbitration counter unit 201.

The CPU 204 determines a device to which the right to use the bus is granted based on the count value of each device input from the arbitration counter unit 201 according to a program stored in a memory (not shown). , The priority of the priority setting register 202 is changed. That is, the CPU 204 gives the highest priority to the device having the largest number of bus acquisition assertions.

When there are a plurality of devices having the largest number of bus acquisition assertions, the CPU 204 plots the priorities for these devices and the priorities for each device preset in the priority setting register 202. 1 may be determined in consideration of the same as the priority determination unit 103 described with reference to FIG.

On the other hand, upon receiving the bus acquisition request 206, the priority determining unit 203 extracts the data 211 of the priority set in the priority setting register 202, and in accordance with the priority set for each device, The arbitration ID of the device to be transmitted is sent to the bus 105.

The priority judging section 203 notifies the arbitration counter section 201 by a counter reset signal 207 to reset the counter value of the device corresponding to the transmitted arbitration ID to “0”.

In the above description, the CPU 204
Describes that the device to which the right to use the bus is granted is determined based on the counter value input from the arbitration counter unit 201. However, the same processing as the priority determination unit 103 shown in FIG. Degree setting register 20
The device to which the right to use the bus may be determined based on the priority set in advance for each device set to 2 and the counter value input from the arbitration counter unit 201. In this case, the CPU 204 notifies the priority determination unit 203 of the determined device, and the priority determination unit 20
3 to transmit the arbitration ID of the corresponding device.

As described above, the processing executed by the priority determination unit 103 in FIG. 1 can be executed by a program (software) operating on the CPU 204, so that the processing according to the usage status of the system bus can be performed. Thus, the software can appropriately replace the priority setting registers and perform flexible priority determination.

[0049]

As described above, according to the present invention, the bus granting device is determined based on the arbitration counter value indicating the number of bus acquisition assertions from each device connected to the bus. It is possible to flexibly set the bus use priority for a plurality of devices connected to the system and to improve the processing efficiency of the system.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an arbitration control circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of an arbitration control circuit according to another embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of a conventional arbitration unit.

[Description of Signs] 100, 200 Arbitration control circuit 101, 201 Arbitration counter unit 102, 202 Arbitration priority setting register unit 103, 203 Priority determination unit 104, 204 CPU 106, 206 Bus acquisition request signal 107, 207 Counter reset signal 109,209 Arbitration processing end signal 110,210 Arbitration counter value

Claims (4)

[Claims] An arbitration control circuit for arbitrating a bus acquisition request from a plurality of devices connected to a bus, wherein the arbitration counter circuit counts the number of bus acquisition requests output from each of the plurality of devices. Priority setting register means for setting priorities for each of the plurality of devices in advance; and a counter counted by the arbitration counter means when a bus acquisition request is received from a device connected to a bus. An arbitration control circuit comprising: priority determining means for determining a device to which a bus use right is granted based on a value and a priority set in the priority setting register means. 2. An arbitration control circuit for arbitrating bus acquisition requests from a plurality of devices connected to a bus, wherein the arbitration counter means counts the number of bus acquisition requests from the plurality of devices for each device. Priority setting register means for storing priorities preset for each of the plurality of devices; and rewriting means for arbitrarily setting priorities for each of the plurality of devices in the priority setting register means. When there is a bus acquisition request from a device connected to the bus, a bus use right is given to a device having the largest counter value counted by the arbitration counter means among the devices that output the bus acquisition request, and When there are a plurality of devices having the largest value, the priority is given among the devices having the largest counter values. An arbitration control circuit comprising priority determining means for giving a bus use right to a device having the highest priority set in the degree setting register. 3. An arbitration control circuit for arbitrating a bus acquisition request from a plurality of devices connected to a bus, wherein the arbitration counter means counts the number of bus acquisition requests output from each of the plurality of devices. Priority setting register means for setting a priority for each of the plurality of devices; and a counter value counted by the arbitration counter means when a bus acquisition request is received from a device connected to a bus. Priority setting means for setting the priority for the device in the priority setting register means, based on the priority, the bus use right based on the priority set in the priority setting register means by the priority setting means Priority determination means for determining a device to be given. Torsion control circuit. 4. An arbitration control circuit for arbitrating bus acquisition requests from a plurality of devices connected to a bus, wherein the arbitration counter means counts the number of bus acquisition requests from the plurality of devices for each device. Priority setting register means for storing priorities set in advance for each of the plurality of devices; and a device for outputting a bus acquisition request when a bus acquisition request is issued from a device connected to the bus. Priority for arbitrarily setting the priority for each of the plurality of devices in the priority setting register so that the device having the largest counter value counted by the arbitration counter in the device is given the right to use the bus. Setting means, and the priority set in the priority setting register means by the priority setting means Arbitration control circuit, comprising: priority determination means for determining a device to which a bus use right is granted based on the priority.