JP2000198240A - Printer and control method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To process a large volume of print data of color laser printer, or the like, at high speed. SOLUTION: A printer comprises a first CPU 11 controlling a process for receiving print data and a process for converting the print data into an intermediate code and outputting the intermediate code, and a second CPU 31 controlling a process for generating a writing data from the intermediate code, a color conversion process and a binarization process. Since data processing progresses stepwise in the printer, parallel processing can be carried out with two CPUs by taking over the processing of data at any one stage, e.g. the intermediate code, among a plurality of CPUs without requiring any communication function among the CPUs or development of an OS for coordination control resulting in the enhancement of processing speed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a printing apparatus capable of printing a color image and a control method thereof.

[0002]

2. Description of the Related Art In recent years, most documents have been processed by information processing apparatuses such as personal computers and output using printers. Therefore, it is always required to improve the printing speed of a printer in order to print a large number of documents at high speed. In addition, the processing of a color image is easily performed in a personal computer, and the amount of documents including color display is increasing.

[0003]

For this reason, various types of printers capable of performing color printing have been developed and generally used. And there is always a demand for a color printer to improve the printing speed. On the other hand, there is always a demand to be able to supply high-speed color printers at low cost.

A color laser printer capable of printing pages is known as a color printer having a high printing speed. In recent years, the speed of a printing engine (printing mechanism) has been greatly improved. However, the resolution of a color image processed by a personal computer has been greatly improved, and the data amount of a color image transmitted for printing from the personal computer has become enormous.
Further, languages transmitted from the personal computer to the printer are various, and the printer needs to process a huge amount of data according to each language. Further, the quality of the color print output from the printer is always required to be high, and a process specific to color printing such as error distribution is required.

Therefore, the process of receiving print data from a personal computer and converting it into binarized data that can be printed by a printing mechanism is complicated, and this process is more shortened than before. This is an important issue for speeding up color printers.

[0006]

Therefore, in the present invention, at least two CPUs perform processing from receiving print data to outputting binarized data from a printing mechanism in parallel. The speed of color printers has been further increased.

In order to improve the processing speed of digital data, it is common to change the CPU at a higher speed, or to develop and adopt hardware specialized in processing such as color conversion. If a high-speed CPU is employed, the processing time of the CPU can be reduced, but the time for data transfer, which will be a critical path, cannot be reduced. Therefore, even if an expensive CPU is employed, the time required for image processing cannot be reduced so much. If hardware fully customized for color conversion processing is employed, the speed of the processing itself can be improved, and if all processing is performed by customized hardware, the processing speed can be further improved.
However, since a critical path such as data transfer still occurs, it is difficult to shorten itself. In addition, it takes cost and time to develop dedicated hardware. Furthermore, since the versatility is lost by adopting the dedicated hardware, it is not possible to deal with future version upgrades or changes / additions of processing contents.

[0008] Parallel processing using a multiprocessor is also known as a general method for improving the processing speed of digital data. However, it takes time and cost to develop software and hardware, such as providing a communication function between processors for cooperative control and developing an OS for multiprocessors. Not adopted.

On the other hand, the inventors of the present application have described that the processing of print data in a printer includes a process of converting an intermediate code into an intermediate code, a process of converting an intermediate code into drawing data of each of RGB (red, green, and blue), and a drawing process. The process proceeds in steps of converting the data into color data for printing in CMYK (cyan, magenta, yellow and black) and binarizing the color-converted data for transmission to a printing mechanism. At each stage, attention has been paid to the fact that the conversion data is written to the buffer. Then, a different CPU takes over the subsequent processing with the data at any stage, so that the processing of the print data can be performed in parallel by a plurality of CPUs.

That is, a printing apparatus according to a first aspect of the present invention controls a process of receiving print data, a process of creating intermediate stage data from the print data, and a process of outputting the intermediate stage data. A first control section provided with a first CPU for performing the conversion, and a second control section provided with a second CPU for controlling a process of converting intermediate-stage data into binary data that can be output to a printing mechanism. Having.

[0011] A control method for a printing apparatus according to a second aspect of the present invention includes a process of receiving print data, a process of creating intermediate stage data from the print data, and a process of outputting the intermediate stage data. And a second control step of controlling the process of converting the intermediate stage data into binary data that can be output to the printing mechanism by the second CPU. .

In the printing apparatus and the control method thereof according to the present invention, the first CPU controls, for example, processing until the intermediate code is converted, and converts the intermediate-stage data converted into the intermediate code into one page or the like. Output in work units. When the intermediate stage data for one page is output, the second CPU controls processing from the subsequent processing to conversion into binary data and transmission to the printing mechanism. Therefore,
It is possible to cooperatively control the two CPUs only by passing data at the intermediate stage. Therefore, it is possible to provide a printing apparatus that performs parallel processing using a plurality of CPUs and has a high processing speed without developing a communication function between CPUs or an OS for cooperatively controlling a multiprocessor. Further, by adopting a plurality of CPUs to increase the speed, it is not necessary to increase the speed of the CPU alone. Therefore, a low-cost and high-speed printing apparatus can be realized. Further, since the CPU method can be adopted, the versatility is higher than that of dedicated hardware, and it can easily cope with future version upgrades.

Further, the speed is increased by the parallel processing by the first and second CPUs. At the same time, the first and second control sections are constituted by almost independent architectures, so that the critical path can be shortened or the critical path can be shortened. The occurrence of a path can be suppressed. That is, the first and second control sections are provided with first and second RAMs and the first and second ROMs, and the first control section is provided with a first CPU, a first RAM, A first ROM is connected by a first bus or a first ASIC, and a second control section includes a second CPU, a second RAM, and a second R
Preferably, the OM is connected by a second bus or a second ASIC. This prevents the bus or ASIC from being occupied by the CPU of another control section or the processing of another control section, so that a critical path does not occur in each control section, or the critical path is minimized. Optimal programming can be performed as follows. Further, by connecting the first control section and the second control section by a data exchange bus, it is possible to exchange data at an intermediate stage.

Of course, it is also possible to provide a third or fourth CPU for controlling each conversion process of drawing data, color conversion data and the like. However, since the hardware associated with the CPU also increases, employing three or more CPUs currently makes the printing apparatus large and very expensive. Furthermore, in the printing apparatus or the control method of the present invention, if data converted into an intermediate code is adopted as the intermediate stage data, the first control section can be designed as a monochrome or color common control section. The second control section can be designed as a color-only control section. Therefore, the first control section can be shared by the monochrome laser. The second control section is a sleek printer (dumb printer) for printing image data transmitted as a bit image.
Can also be shared.

By using the intermediate code as the data at the intermediate stage, the processing range of the first and second control sections becomes clear as described above, so that a highly versatile system is obtained.
Further, since the intermediate code and subsequent ones are continuously processed by the second control section in units of work such as one page and output from the printing mechanism, the use efficiency of hardware such as a memory is high and high-speed output is possible. However, since the process of converting the data of a work unit (one page) into drawing data, color conversion data, and binary data is performed in series in the second control section, if the processing speed of the printing mechanism is high, the printing speed The processing speed cannot keep up, and the control may become a critical path by the second CPU, causing an overrun.

Therefore, in such a case, the data in the intermediate stage is drawn data in which the intermediate code is further converted into RGB colors, or the drawn data is further converted to CMYK.
It is desirable to use data after color conversion into each color. Such a change in the data type at the intermediate stage can be dealt with by changing the conversion hardware included in the first and second control sections, or without changing the hardware, The range controlled by the first or second CPU may be changed by software.

A printing apparatus according to a third aspect of the present invention includes a printing mechanism and first and second control sections each having a CPU and capable of exchanging data with each other. The two control sections execute the control process for printing composed of a series of multiple steps starting from receiving the print data and ending by sending the binarized data to the printing mechanism. .

A control method for a printing apparatus according to a fourth aspect of the present invention is a control method for printing comprising a series of multiple steps starting from receiving print data and ending by sending binarized data to the printing mechanism. A control step in which some predetermined steps of the processing are executed by a first control section having a first CPU, and a control step in which the remaining predetermined steps are executed by a second control section having a second CPU. And a process.

In one preferred embodiment, a control program for both the first and second CPUs is stored in a ROM provided in the first control section, and the ROM is turned on when the power is turned on. From the RAM in the second control section to the second
The control program for the second CPU is loaded and the second CP
U to operate according to the control program loaded into its RAM. With this, the program ROM
And the size of the substrate in the control section can be reduced.

In a preferred embodiment, the first control section includes, in addition to the first CPU, a first RAM and a first ASIC.
Is mounted in the second control section, in addition to the second CPU, the second RAM and the second ASIC are mounted. Then, each of the first and second CPUs can access the first RAM, the first ASIC, the second RAM, and the second ASIC. For this reason, the first control section and the second control section are assigned to each stage of processing, and the control is performed by any CP.
A large degree of freedom is obtained with regard to work assignment such as whether the task is performed by U, and as a result, an optimum job assignment can be set according to the specifications of the printing apparatus and the nature of the print job.

A typical example of the work assignment is that the first control section shares the step of receiving print data and the step of creating intermediate data from the print data, and the second control section defines the intermediate step. And the step of generating the binarized data from the data of the print engine and the step of sending the binarized data to the print engine.

In a preferred embodiment, in the first control section, the first ASIC receives print data, and the first CPU interprets the received print data in language to create an intermediate code. In the second control section, the second CPU
From the intermediate code to the same color system as the intermediate code (for example, RG
B) draws drawing data as bitmap data, and the second ASIC performs color conversion on the drawing data to create color conversion data as bitmap data of the same color system (for example, YMCK) as the printing mechanism. The color conversion data is binarized to generate binarized data. In this series of control processing, the print data, intermediate code, and drawing data are temporarily stored in the first RAM or the second RAM, respectively.
The operation of writing to and reading from M is the first ASI
C performs by DMA, and the operation of writing and reading those data to and from the second RAM is performed by the second A
The SIC performs by DMA, thereby reducing the load on the CPU.

[0023]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a schematic configuration of a printer 1 according to the present invention using a block diagram. The printer 1 of the present embodiment is a color laser printer, and includes a printing mechanism 2 for performing multi-color printing, and a control unit 3 for supplying binarized data to the printing mechanism 2. The control unit 3 receives print data φ from a personal computer or the like.
p, and print data φp of the binarized data φo which can be printed by the printing mechanism 2 through several steps.
And output.

The printing section 3 of this embodiment is divided into two control sections 5 and 6. The first control section 5 stores the print data φ
A process of receiving p and a process of further converting it to an intermediate code φm and outputting it are performed. The second control section 6 converts the intermediate code φm into drawing data φc,
a process of color-converting c into converted data φt;
A process of binarizing the converted data φt and outputting the binarized data φo can be performed.

The first control section 5 is mainly composed of a first ASIC 10 having a function as a DMA controller.
, The first CPU 11 is connected. The first AS
The IC 10 is further connected to the SDRAM by the RAM bus 13.
14 are connected, and a ROM 17 is connected by a ROM bus 16. The RAM bus 13 is provided with a slot 15 for connecting an additional RAM.
The bus 16 is provided with a slot 19 for connecting an additional program card via a buffer 18. First
The ASIC 10 also has an input / output module 21 and an I / O module for high-speed serial interface via an external bus 20.
An IEEE 1394 module 22 and an Ethernet module 23 of a network interface are connected.

The input / output module 21 further includes a bus TYPEB for an option card, a parallel interface PIF such as Centronics, a serial interface SIF such as RS-232C, an engine interface EIF, a panel interface PANEL, and an interface for USB and IDE. , A non-volatile ROM interface EEPROM, and the like. Further, the first ASIC 10 is connected to a second control section 6 described later.
The ASIC 30 is connected via a data exchange bus 25.

Therefore, the first control section 5 can receive print data from a personal computer or the like via these external interfaces and store it in a working memory such as the SDRAM 14. Furthermore, the first
Since the ASIC 10 also has a compression function (CMP) and a decompression function (DCMP), it is also possible to decompress print data received in a compressed state and expand it on the SDRAM 14. Each module 21,
The print data φp received at 22 or 23 is
The data is transferred to the SDRAM 14 by the DMA function of C10,
Further, if compressed, it is expanded at the same time as the DMA or at another timing. The first CPU 11 controls the reception and decompression processing of these print data φp.

The CPU 11 further determines the description language of the print data φp loaded on the SDRAM 14, and
The print data φp is interpreted according to the language processing program stored in M17, and an intermediate code φm that can be processed by the printer 1 is generated. And the generated intermediate code φ
m via the data exchange bus 25 to the second control section 6
And writes the data in the DRAM 32 of the second control section 6. When the data amount of the intermediate code φm is large, ASIC
The compressed data is supplied to the second control section by using 10 compression functions CMP.

The second control section 6 is a control section for mainly performing color processing, and is an IMA which is hardware for drawing.
The second ASIC 30 including the ASIC 35 is mainly configured. The second ASIC 30 further includes a hardware function DCMP 36 designed for compression and decompression, a hardware function CCNV 37 designed for color conversion,
And hardware function CP designed for binarization
GIX 38 is provided. Further, a second CPU 31 for controlling these hardware functions is connected to the second ASIC 30 via a CPU bus 41. Further, a ROM 33 storing a program of the CPU 31 is connected to the second ASIC 30 via a ROM bus 43, and a DRAM 32 serving as a work area is connected via a RAM bus 42. Further, a bus 25 for exchanging data with the first ASIC 10 is connected to the second ASIC 30, and the binarized data φo is transmitted to the printing mechanism 2.
A bus 7 for outputting the data to the computer is also connected.

When the first control section 5 writes one page of intermediate code φm into the DRAM 32 by the first control section 5, the second control section 6 prints one page of data described by the intermediate code φm. The processing until the data is converted into binarized data φo that can be printed and output is continuously performed. First, the intermediate code φm written in the DRAM 32
CPU3 while decompressing by the decompression function DCMP36
1 and the function of the IMA 35 are converted into 8-bit drawing data φc for each color of RGB. The drawing data φc is written to the DRAM 32 in a compressed state again.

The drawing data φc is then reloaded and decompressed, and then subjected to a hardware function CCN for color conversion.
Is supplied to the V37, and from the 8-bit data of each color of RGB,
CMYK is converted into 8-bit color conversion data φt for each color. The color conversion data φt is further supplied to a hardware function CPGIX 38 for binarization, converted into binarization data φo, and output to the printing mechanism 2. The printing mechanism 2 outputs a color image for each page.

FIG. 2 is a flowchart showing the above process. First, the first control section 5 receives the print data φp in step 51 and stores it in the SDRAM 14. After receiving one job or at an appropriate timing during reception, in step 52, the print data φp is loaded from the SDRAM 14, decompressed, converted into an intermediate code φm, further compressed, and stored in the SDRAM 14. When an appropriate work unit, for example, an intermediate code φm for one page is generated, the ASIC 10
Of the ASIC 30 of the second control section 6 via the data exchange bus 25 using the DMA function of
0 is stored in the DRAM 32. These steps 51, 52 and 53 are performed under the control of the first CPU 11, and when the processing of step 53 is completed, the processing of the print data φp for the next one page is started.

In the second control section 6, when the intermediate code φm of the appropriate work unit is output to the DRAM 32, processing for color printing is performed. In this example, since the printer is a page printer, one page is usually a unit, and the process is started when the intermediate code φm of the unit is accumulated. First, in step 54, the intermediate code φm stored in the DRAM 32 is loaded and decompressed, and then converted into drawing data φc of each color of RGB. Then, in step 55, D
The compressed data is output to the RAM 32 again. The drawing data φc is loaded and decompressed again in step 56,
The color is converted into data φt of each color of CMYK. And
In step 57, the hardware function CPGIX for binarization
38, and a binarization process is performed in step 58. The binarized data φo is output to the printing mechanism 2 in step 59, and color printing is performed. These steps 54 to 59 are performed under the control of the second CPU 31.

As described above, in the printer 1 of the present embodiment, the processing (steps 51 to 53) from receiving the print data φp to outputting it as the intermediate code φm is controlled by the first CPU 11 in the first control section 5. Is repeated under Further, the processing from the conversion of the intermediate code φm to the binarized data φo to the output (Steps 54 to 59) is repeated in the second control section 6 under the control of the second CPU 31. Therefore, the processing of steps 51 to 53 and the processing of steps 54 to 59 are performed in parallel, so that the throughput of the control unit 3 can be greatly improved.
For this reason, the printer 1 with a high printing speed can be provided.

Further, by employing the control system of the present embodiment, it is possible to exclude the processing in the first control section 5 from the processing time of the second control section 6 which is likely to be a critical path in processing print data. Becomes By shortening the processing time in the second control section 6, if the processing time is substantially equal to or shorter than the printing speed of the printing mechanism 2, the next page is printed when the printing mechanism 2 finishes printing one page. Printing can be started. Therefore, it is possible to provide a color page printer capable of continuously outputting color prints without stopping the printing mechanism 2 for each sheet.

Further, in the first control section 5, since the colorization processing is performed independently in the second control section 6, it is not necessary to interrupt the printing processing by performing a special processing such as an interruption. Communication processing with the personal computer can be performed at any time during printing. Color page printers are more expensive and have a larger installation area than monochrome printers, so they are often shared via a LAN or the like, and the time spent for communication processing increases. In the printer 1 of the present embodiment, the number of interrupt processes for the communication process is reduced, so that extra processing time such as saving registers for interrupt and recovery can be saved, the printing speed is high, and the response when communicating is performed. A printer with a high speed can be provided.

In the control unit 3 of the printer 1 of this embodiment,
By providing the data converted from the first control section 5 to the intermediate code φm to the second control section 6, the control of the first and second control sections is coordinated. Intermediate code φ
The process in which data is converted stepwise into m, drawing data φc, color conversion data φt, and binary data φo is unique to a printer, and data in each step is not referred to at the same time. Therefore, by shifting the control section with the data at any stage, close cooperative control of the control section is not required.

Therefore, unlike the conventional control system using a multiprocessor, the control section 3 of the printer does not need to provide a communication function between CPUs and to newly develop an OS for parallel processing. By taking over the intermediate code φm at an appropriate timing,
Parallel processing by the two CPUs 11 and 31 is realized. For this reason, parallel processing by a multiprocessor can be realized without spending much cost or time on development of hardware or software, and a printer capable of high-speed processing can be provided at low cost.

Further, the control unit 3 of the printer 1 of the present embodiment
Each of the first control section 5 and the second control section 6 has a substantially independent architecture centered on the first ASIC 10 or the second ASIC 30, respectively. Therefore, the timing at which each CPU 11 or 31 fetches an instruction, the timing at which the CPU accesses the RAM, the timing at which the bus is opened for DMA, and the timing at which the bus is opened for DMA are adjusted between the first and second control sections. There is almost no need for the process of adjusting with. The timing at which the intermediate code φm is transferred from the first control section 5 to the second control section 6 may simply be controlled by one of the control sections 5 or 6.

Therefore, the processing from the reception of the print data φp to the conversion to the intermediate code φm and the processing from the output of the intermediate code φm to the output of the binary data φo can be executed almost completely independently. it can. Therefore, each control procedure can be optimized, and each control section 5 and 6 can be optimized.
Processing time can be shortened. Therefore, the total processing time of the printing apparatus 1 can be further reduced.

As described above, the first and second control sections 5
And 6 have independent architectures,
The processing speed can be improved, and the versatility for other printers is also improved. For example, the first control section 5 of this example is:
The first ASIC 10 has a function of compressing and expanding print data for monochrome. Therefore, in a monochrome laser printer, the first control section 5 of this example is used.
By mounting a substrate on which is mounted, it is possible to receive monochrome print data from a personal computer, print it after language processing it. On the other hand, the second control section 6 performs drawing, color conversion, and
It has the functions required for color printing to perform value conversion.
Therefore, by mounting the board on which the second control section 6 is mounted, it is possible to provide a slick printer or a dumb printer that receives bit-mapped data that does not require language processing and performs color printing.

Further, by using such two CPUs 11 and 31, the speed is increased to several hundred MHz.
It is possible to increase the speed at a lower cost as compared with a printer employing a very high-speed and expensive CPU such as a printer. Also, as described above, a control system that is more flexible and more versatile than a printer whose hardware has been accelerated and whose speed has been increased can be realized. The printer 1 of this example can flexibly cope with a printer language version upgrade by changing or adding a ROM, and can flexibly process multi-gradation or high-resolution color images by adding a memory card. Can respond.

Further, the control unit 3 of the present embodiment comprises two CPUs 1
By changing programs 1 and 31, the first
It is also possible to change the range controlled by the CPU 11 and the second CPU 31. For example, in a printer in which the resolution of the print data φp to be processed is high, the data amount is large, and the printing speed of the printing mechanism 2 is high,
When the second CPU 31 controls the process of converting the intermediate code into the drawing data φc, color conversion, and further binarization, the processing time becomes longer than the printing time per page of the printing mechanism 2, A series of processes controlled by the CPU 31 may become a critical path. In such a case, the printing mechanism 2 stops every time one page is printed,
Alternatively, there is a possibility that printing in which data is missing in the middle of a page due to overrun is performed. Therefore, it is desirable to reduce the processing controlled by the second CPU 31 so that the critical path becomes the printing time of the printing mechanism 2.

FIG. 3 is a flowchart showing an example in which the processing range controlled by the first and second CPUs 11 and 31 is changed. As described above, in the printer, the processing proceeds with the intermediate code φm, the drawing data φc, and the color-converted data φt, so that the data of any stage is transferred from the first CPU 11 to the second CPU 31 so that the two CPUs Can be processed in parallel. For this reason, in the example shown in FIG. 3, the processing up to the conversion to the drawing data φc and output is controlled by the first CPU 11, and the drawing data φc for one page, which is a unit of work, is stored in the DRAM 3 of the second control section 6.
At the stage of output to 2, the second CPU 31 takes over the subsequent processing of the data, so that the processing time by the second CPU 31 is shortened.

The respective steps shown in FIG. 3 are the same as those shown in FIG. 2, except that the first control section 5 first receives the print data φp in step 51 and receives the SDRA
Store it in M14. In step 52, the print data φp is loaded from the SDRAM 14, expanded, and converted into an intermediate code φm. Step 53 to the intermediate code φm
And the SDRAM 14 or the DRAM 3 of the second control section
Store in 2. Further, at step 54, the drawing hardware IMA provided in the ASIC 30 of the second control section
35, the intermediate code φm is converted into drawing data φc and stored in the SDRAM 14. Then, when the drawing data φc for an appropriate work unit, for example, one page, is generated, the D in the second control section 6 is transferred via the data exchange bus 25 using the DMA function of the ASIC 10 in step 55.
The data is stored in the RAM 32. The first CPU 11 repeats these processes.

When the data processing is taken over by the second CPU 31, the drawing data φc is loaded again at step 56, decompressed, and color-converted to data φt of each color of CMYK.
This data φt is output to the binarization hardware function CPGIX 38 in step 57, and after binarization processing in step 58, the data φo is output to the printing mechanism 2 in step 59 to perform color printing. In this control method, what is repeatedly and continuously controlled by the second CPU 31 is the processing from step 56 to step 59.
31 can be reduced. Therefore, the second CPU 3
1 can be prevented from becoming a critical path, and the printing mechanism 2 allows continuous printing in page units.

Further, deterioration of print quality due to overrun can be prevented. Of course, the load on the second CPU 31 can be further reduced, and the first CPU 11 controls the processing up to the processing of outputting the data φt after color conversion (step 57). The processing after the value conversion may be controlled. Then, the range controlled by the first and second CPUs 11 and 31 can be changed only by changing the program of each CPU.

However, in the above example, the hardware function 35 for converting the drawing data into the drawing data φc or the hardware function 37 for performing the color conversion in the second control section 6 is used. For this reason, the data exchange bus 2
5 traffic increases. Therefore, there is a possibility that the use efficiency of a memory such as a DRAM or a hardware function is reduced. However, since the critical path for data processing can be shortened, there is a possibility that the total processing time can be shortened. Of course, the hardware function 35 for drawing or the hardware function 37 for color conversion
It is also possible to move to the first control section 5 or to provide the first control section 5. However, when the hardware is changed in this way, each control section 5
And 6 are less versatile, and are over-equipped, resulting in excessive cost and size. Therefore, as described above, it is desirable to cope with this by changing the software of each of the CPUs 11 and 31.

Further, the drawing, color conversion, or binarization processing currently performed by the hardware function can also be performed by software. In such a case, the software including the respective functions is optimized by software. Could be assigned to Even in such a case, cooperative control of the two CPUs 11 and 31 can be performed very easily by switching the CPUs with the intermediate stage data (intermediate code φm, drawing data φc or color conversion data φt) after the conversion in each stage. And the processing speed can be increased by performing parallel processing.

Further, in the above description, each control section is an ASIC 10 to which a RAM bus and a CPU bus can be connected.
Although description has been made of an example in which the configuration is centered on and, it is needless to say that a configuration in which a RAM and a ROM are connected to the CPU bus may be used. However, R
In a configuration in which AM and ROM are connected to the CPU bus, there is a possibility that the control procedure may be restricted, such as matching the timing at which the CPU releases the bus with the timing at which data is transferred, so the processing speed may be slightly reduced. Will be.

In the above description, the first and second two C
Although the control unit 3 in which the PUs are installed is described as an example, each control section may be configured by a multi-CPU, or the first and second control sections may be configured.
It is of course possible to adopt a configuration using more CPUs, such as receiving a plurality of control sections and performing parallel processing.

FIG. 4 is a block diagram showing a circuit configuration of a printer according to another embodiment of the present invention.

As shown in FIG. 4, the printer 101 has a first control section 103, a second control section 105, and a printing mechanism 107. First control section 103 and second control section 1
05 has a symmetrical configuration as shown in the figure.

That is, the first control section 103 includes the first C
PU 111, first ASIC 113, first DRAM 115
And a first ROM 117. First ASIC 113
Is an input / output ASIC 121 for inputting / outputting data to / from the host device 109 and a memory AS for accessing the memories 115 and 117 and controlling the bus of the CPU 111.
And an IC 123. In the first ROM 117,
A program for the first CPU 111 is stored.

The second control section 105 includes the second CPU 13
1, the second ASIC 133, the second DRAM 135 and the second
It has a ROM 137. The second ASIC 133 is obtained by the memory ASIC 141 that accesses the memories 135 and 137 and controls the bus of the CPU 121, and performs image processing such as color conversion, binarization, gradation correction, and edge smoothing. Image processing ASIC 14 that supplies final YMCK binary data to printing mechanism 107
3 The second ROM 137 has a second CPU
131 programs are stored.

The first CPU 111 of the first control section 103
Is a resource in the first control partition 103 (first ASIC)
113, the first DRAM 115) as well as the resources (second ASIC 123, second DR) in the second partition 105.
AM 135). Similarly,
The second CPU 131 of the second control section 105 controls the resources (the second ASIC 123, the second DR 123) in the second control section 105.
AM 135) as well as the resources (first ASIC 113, first DRAM 115) in the first control section 103 can be accessed.

When the first CPU 111 has a DRAM controller, instead of connecting the first DRAM 115 to the first memory ASIC 123 (or together with it), the first CPU 111 supplies the first DRA as shown by a dotted line.
M151 can also be connected. If the second CPU 131 has a DRAM controller, the second memory AS
Instead of (or with) the second DRAM 135 to the IC 133, the twelfth PU1
The second DRAM 153 can be connected to the terminal 31.

FIG. 5 is a block diagram of a printer having a configuration in which the printer shown in FIG. 4 is slightly modified.

In the printer 101 shown in FIG. 4, ROMs 117 and 137 storing control programs for the CPUs 111 and 131 are individually prepared in the control sections 103 and 105. However, the data amount of the control program is small for the capacity of the actual ROM chip.
There are quite a lot of unused storage areas in the ROMs 117 and 137 that are not used. In particular, two control sections 10
When a configuration is adopted in which the circuit boards 3 and 105 are separate circuit boards and both boards are connected by a connector or the like, the number of mountable devices may be further reduced due to the allowable board size.

Therefore, in the configuration shown in FIG. 5, the first C
Both the control program for the PU 211 and the control program for the second CPU 231 are collectively stored in the ROM 217 in the first control section 203. Therefore, there is no program ROM in the second control section 205, and the board size of the second control section 205 is reduced. The memory ASIC 241 in the second control section 205 has a built-in SRAM 271. When the power of the printer 201 is turned on, the RO
The control program for the second CPU 231 in M217 is S
Loaded into the RAM 271, and the second CPU 231
271 operates according to the control program in 271.

When the first CPU 211 has a DRAM controller, instead of connecting the first DRAM 215 to the first memory ASIC 223 (or together with it), the first CPU 211 has the first DRA as shown by a dotted line.
M251 can also be connected. If the second CPU 231 has a DRAM controller, the second memory AS
Instead of (or with) the second DRAM 235 connected to the IC 233, the second CPU 1
The second DRAM 253 can be connected to the terminal 31.

FIGS. 6 and 7 show operation start timings when the power supply of the printer shown in FIGS. 4 and 5 is turned on.

In the printer 101 shown in FIG. 4, when the power is turned on, the reset circuit 119 outputs the reset signal 161 to the first signal.
CPU 111, first ASIC 113, second CPU 131
In addition to the reset state, the reset signal 161 is released after a predetermined time. FIG.
As shown in the timing chart of FIG. 11, the first CPU 111, the first ASIC 113, the second C
The PU 131 and the second ASIC 133 are simultaneously activated, and the first control section 103 and the second control section 105 start operating simultaneously.

On the other hand, in the printer 201 shown in FIG. 5, when the power is turned on, the first reset circuit 219 sends the reset signal 261 to the first CPU 111, the first ASIC 113, and the second ASIC.
In addition to C133, a second reset circuit 263 built in the second ASIC 263 outputs a reset signal 265 to the second ASIC 263.
It is added to the CPU 231. Then, after a predetermined time, the first reset circuit 219 releases the reset signal 261. FIG.
As shown in the timing chart of FIG. 7, the first CPU 111 and the first ASIC 113 are enabled at the same time as the reset is released, and the first control section 203 starts operating, but the second control section 203 starts operating.
In the control section 205, the second ASIC 233 is valid,
Since the second CPU 231 is still in the reset state, the second control section 205 as a whole is still in the standby state. Then, in this standby state, the second CPU program in the ROM 217 is loaded into the SRAM 271 in the second memory ASIC. After the loading is completed, the reset signal 265 of the second reset circuit 263 is released by the signal 267 from the first CPU 211, whereby the second CPU 231 is enabled and the operation of the second control section 205 starts.

In the printer shown in FIG. 4 or FIG.
There are many variations in how the control process from receiving print data from the host device to sending binary data to the printing mechanism is assigned to the first and second control sections. Which allocation method is optimal also depends on the difference in performance between the first CPU 111 and the second CPU 211, the nature of the print job, and the like. FIG.
9 shows a representative example of the assignment of work to the first and second control sections. FIG. 8 shows a control operation from reception of print data to creation of RGB raster data, and FIG. 9 shows a process of performing color conversion and binarization on RGB raster data to create YMCK binary data and sending it to a printing mechanism. 3 shows the control operation.

As shown in FIG. 8, print data from the host device 301 is transferred to the input / output
The C303 receives the print data (401), and the first memory ASIC 307 writes the received print data to the first DRAM 309 by the DMA (403). At this time, the first CPU 3
05 performs DMA (40) performed by the first memory ASIC 307.
3) is controlled (407). The print data 405 stored in the first DRAM 405 is described in, for example, PDL (Page Description Language). Next, the first CPU 305
The PDL print data 405 is read from the first DRAM 309, interpreted (409), and intermediate-stage data (typically an intermediate code) is created.
11 is written to the first DRAM 309.

Next, the second memory A of the first control section 302
The SIC 313 performs the first DRA by the DMA (413).
The intermediate code 411 in M309 is copied (or transferred) to the second DRAM 315. DMA at this time (413)
Is controlled by the second CPU 311 (417). Next, the second CPU 311 reads the intermediate code 415 from the second DRAM 315k, draws complete bitmap image data based on this (417), and stores the bitmap image data (drawing data) 419 in the second DRAM 31.
Write 5 Next, the third memory ASIC 313 transfers the drawing data 419 in the second DRAM 315 to the DMA (4
21), the data is transferred to the first DRAM 309. This D
The AM (421) is controlled by the second CPU 311 (42).
5).

Subsequently, image processing such as color conversion and binarization is performed according to the procedure shown in FIG. Second memory ASIC 313
Sends the drawing data (usually RGB bitmap image data) 423 in the first DRAM 309 to the image processing ASIC 317 by the DMA (425). The image processing ASIC 317 performs processing (427) such as color conversion and gradation correction on the RGB drawing data, and performs YMCK
To the drawing data (color conversion data). That YMC
The second memory ASIC 313 transfers the K color conversion data to the DMA
By (429), data is written to the first DRAM 309. Next, the second memory ASIC 313 uses the DMA (433) to execute the YMCK color conversion data 43 in the first DRAM 309.
1 is sent to the image processing ASIC 317. Image processing ASIC
317 performs binarization processing (435) on the YMCK color conversion data (performs edge smoothing processing as necessary) to convert the YMCK color conversion data into YMCK binarization data, and converts the YMCK binarization data into a printing mechanism 319. Send to The DMA (42) performed by the second memory ASIC 313 in the above process
5, 429, and 433) are controlled by the first CPU 305.

The control procedure shown in FIGS. 8 and 9 is an example, and another procedure can be adopted. For example, in the procedure shown in FIG. 9, if the second CPU has sufficiently high performance, as shown by a dotted line 441, the second CPU 311 sends the DMA (425, 429,
433) may be controlled. Also, the second DRAM 315
Is sufficiently large, as indicated by the dotted line 439,
The YMCK color conversion data after the color conversion is stored in the second DRAM 315.
May be stored. Also, an image processing ASIC
At 317, the YMCK color conversion data obtained by the color conversion (427) is directly binarized as indicated by a dotted line 443 without temporarily storing it in the DRAM (435), and the resulting YMCK binarized data is obtained. May be sent to the printing mechanism 319.

The printer according to the present invention described above is
A plurality of CPUs are used to control processing until print data is converted into binary data. Then, the range controlled by each CPU is taken over by the intermediate-stage data that has undergone any conversion processing such as intermediate code, drawing data, or color conversion data.
Parallel processing by a plurality of CPUs is realized with a simple configuration without using an OS for data communication between U and cooperative control. Therefore, according to the present invention, it is possible to provide a low-cost, high-speed printing apparatus that is optimal for a printer that outputs a high-quality color printer such as a color laser printer.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a schematic configuration of a printer according to an embodiment of the present invention.

FIG. 2 is a flowchart showing a control process in the printer shown in FIG. 1;

FIG. 3 is a flowchart showing a control process different from that of FIG. 2;

FIG. 4 is a block diagram illustrating a circuit configuration of a printer according to another embodiment of the present invention.

FIG. 5 is a block diagram showing a configuration of a printer according to still another embodiment of the present invention.

6 is a timing chart showing a reset release operation when the power of the printer in FIG. 4 is turned on.

FIG. 7 is a timing chart showing a reset release operation when the power of the printer in FIG. 5 is turned on.

FIG. 8 is an explanatory diagram showing a control operation from reception of print data to creation of RGB raster data by the printer in FIG. 4 or FIG.

9 is an explanatory diagram illustrating a control operation when performing color conversion and binarization of the printer in FIG. 4 or FIG. 5;

[Explanation of symbols]

1, 101, 201 printer 2, 107, 207, 319 printing mechanism 3 control unit 5, 103, 203, 300 first control section 6, 105, 205, 302 second control section 10, 113, 213 first ASIC 11, 111, 211 First CPU 12 CPU bus 13 RAM bus 14 SDRAM 16 ROM bus 17 ROM 20 External bus 21 I / O unit 30, 133, 233 Second ASIC 31, 131, 231 Second CPU 41 CPU Bus 32 DRAM 42 RAM bus 33 ROM 43 ROM bus 35 Drawing hardware function 36 Compression / decompression hardware function 37 Color conversion hardware function 38 Binarization hardware 115, 151, 215, 251, 309 First DR
AM 135, 153, 235, 253, 315 Second DR
AM 117 First ROM 137 Second ROM 217 ROM 121, 221, 303 Input / output ASIC 123, 223, 307 First memory ASIC 141, 241, 313 Second memory ASIC 143, 243, 317 Image processing ASIC

────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] June 22, 1999 (1999.6.2
2)

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0007

[Correction method] Change

[Correction contents]

In order to increase the processing speed of digital data, it is common to change the CPU to a high-speed one, or to develop and adopt hardware specialized in processing such as color conversion. If a high-speed CPU is adopted, the CPU
Can be shortened, but the time for data transfer or the like which will become a critical path cannot be shortened. Therefore, even if an expensive CPU is employed, the time required for image processing cannot be reduced so much. If hardware fully customized for color conversion processing is employed, the speed of the processing itself can be improved, and if all processing is performed by customized hardware, the processing speed can be further improved.
However, since a critical path such as data transfer still occurs, it is difficult to shorten itself. Also, developing dedicated hardware is costly and time consuming. Furthermore, since the versatility is lost by adopting the dedicated hardware, it is not possible to deal with future version upgrades or changes / additions of processing contents.

Claims (16)

[Claims] A first method for controlling a process of receiving print data and a process of converting the print data into intermediate stage data
A first control section having a CPU, and a second control section having a second CPU for controlling a process of converting the intermediate stage data into binary data that can be output to a printing mechanism. Printing equipment. 2. The control section according to claim 1, wherein the first control section further includes a first RAM, a first ROM, and a first ASIC, and the second control section includes a second RAM, And a second ASIC, further comprising a data exchange bus for supplying the intermediate stage data from the first control section to the second control section. 3. The printing apparatus according to claim 1, wherein the data in the intermediate stage is data of an intermediate code created by language-interpreting the print data. 4. The printing apparatus according to claim 1, wherein the data at the intermediate stage is rendering data as RGB bitmap data rendered based on an intermediate code. 5. The CMY data according to claim 1, wherein the data at the intermediate stage is formed by performing color conversion on RGB drawing data.
A printing device that is color conversion data as K bitmap data. 6. A first method for controlling a process of receiving print data and a process of converting the print data into intermediate stage data.
And a second control step of controlling, by a second CPU, a process of converting the intermediate stage data into binary data that can be output to a printing mechanism. 7. The method according to claim 6, wherein the intermediate stage data is intermediate code data created by interpreting the print data in a language. 8. The method according to claim 6, wherein the data in the intermediate stage is rendering data, which is RGB bitmap data rendered based on an intermediate code. 9. The CMY data according to claim 6, wherein the data at the intermediate stage is a color conversion of RGB drawing data.
A method for controlling a printing apparatus, which is color conversion data as K bitmap data. 10. A printing mechanism, comprising a first control section and a second control section capable of exchanging data with each other, wherein the first control section has a first CPU and the second control section The partition has a second CPU, wherein the first and second control partitions are configured for a series of printing steps consisting of a series of steps beginning with receiving print data and ending with sending binarized data to the printing mechanism. Printing device that performs control processing for each stage in a shared manner. 11. The control section according to claim 10, wherein the first control section has a ROM in which control programs for the first and second CPUs are stored, and the second control section is provided from the ROM. Second CP
A printing apparatus, comprising: a RAM in which a control program for U is loaded, wherein the second CPU operates according to the control program loaded in the RAM. 12. The device according to claim 10, wherein the first control section includes a first RAM and a first ASIC.
Wherein the second control section comprises a second RAM and a second ASIC.
Wherein each of the first and second CPUs comprises the first CPU.
And a printing apparatus capable of accessing the first RAM, the first ASIC, the second RAM, and the second ASIC. 13. The second control section according to claim 10, wherein the first control section shares the step of receiving the print data and the step of creating intermediate data from the print data. Is a printing apparatus that shares the steps of creating the binarized data from the intermediate stage data and sending the binarized data to the print engine. 14. The first control section according to claim 13, wherein the first control section comprises a first RAM and a first ASIC.
And the second control section comprises a second RAM and a second ASIC.
Wherein the first ASIC has means for receiving the print data, and the first CPU has means for interpreting the received print data in language to create an intermediate code; The second CPU has means for drawing drawing data, which is bitmap data of the same color system as the intermediate code, from the intermediate code, and the second ASIC performs color conversion on the drawing data and A printing apparatus comprising: means for creating color conversion data as bitmap data of the same color system as a printing mechanism; and means for binarizing the color conversion data to create the binary data. 15. The second ASIC according to claim 14, wherein the first ASIC has a unit that performs DMA to the first RAM with respect to any of the print data, the intermediate code, and the drawing data. A printing apparatus comprising: means for performing DMA on the second RAM with respect to any of the print data, intermediate code, and drawing data. 16. A control for printing, comprising a series of steps, wherein a first control section having a first CPU starts with receiving print data and ends with sending binarized data to the printing mechanism. A control step of executing some predetermined steps of the processing; and a second control section having a second CPU, wherein the control processing for printing including the series of plural steps is performed. And a control step of executing the remaining predetermined steps.