JP2000173281A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To divide a whole memory array into a region in which binary data is recorded and a region in which multi-level data is recorded, and to enable externally dealing with it as the same storage unit. SOLUTION: A memory array 4 is divided into a storage region of binary and a storage region of multi-level, and corresponding to the above, a multi-level write-in/read-out control circuit 12 and a binary write-in/read-out control circuit 13 are provided. A mapping circuit 11 converting logic address from the outside to a physical address is provided, while a dividing position between a multi- region and a binary region is held in a division address register 15. A logic address and a physical address are exchanged by a mapping circuit 11, it is judged whether the physical address is in the multi-level storage region of a memory array or a binary storage region from an output of a comparator 16, and the multi-level write-in/read-out control circuit 12 and the binary write-in/read-out circuit 13 are switched.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device such as a flash memory.
The present invention relates to a nonvolatile semiconductor memory device provided with an area for storing binary data or more in a memory cell and an area for storing binary data.

[0002]

2. Description of the Related Art In a flash type nonvolatile semiconductor memory composed of a NAND string, a structure in which data having two values of "0" and "1" are recorded in one memory cell transistor is usually used. However, a nonvolatile semiconductor memory having a binary configuration has a limit in storage capacity per unit area. In particular, it is considered that such a semiconductor memory is used for recording video data and audio data, and a large-capacity semiconductor memory capable of recording video data and audio data for a long time is desired. For this reason, a multi-level nonvolatile semiconductor memory capable of recording multi-level data in one memory cell has been developed. However, in a multi-valued nonvolatile memory,
The reliability of data retention is lower than when binary data is stored.

As described above, the nonvolatile semiconductor memory having the binary configuration has high reliability, but it is difficult to increase the storage capacity. On the other hand, the nonvolatile semiconductor memory having the multi-level configuration has the following disadvantages. Although the storage capacity can be increased, there is a problem that reliability is reduced.

Therefore, the entire non-volatile semiconductor memory array is divided into an area for recording binary data and an area for recording multi-valued data, and the two areas are selectively used according to the nature of the data and the needs of the user. It has been proposed to do so.

That is, the data stored in the memory includes:
Reliability is required, but the data amount is not so large, and the data amount is large, but some errors can be tolerated. The former data includes data in a management area for managing a boot area, a FAT (File Allocation Table) area, a directory area, and the like. Examples of the latter data include image data and music data.

In accordance with the nature of such data, data to be stored in an area for recording binary data and data to be stored in an area for recording multi-valued data are sorted. That is, the data in the management area where reliability is required is written in the area where binary data is recorded. Image data and music data whose data amount becomes large are written in an area for storing multi-valued data.

As described above, the entire memory array of the nonvolatile semiconductor memory is divided into an area for recording binary data and an area for recording multi-valued data. If the two areas are properly used, the storage area for the binary data and the storage area for the multi-valued data in the nonvolatile memory can be effectively used.

[0008]

However, the addresses at which the data in the management area such as the boot area, FAT area, and directory area are arranged are usually determined according to the requirements of the system. Due to the demand of such a system, even if the entire nonvolatile semiconductor memory array is divided into an area for recording binary data and an area for recording multi-valued data, the binary area and the multi-valued area are externally divided. Specify and write the data of the management area to the area of the binary data,
Control such as writing image data and music data in a multi-value area cannot be easily performed.

Accordingly, it is an object of the present invention to use the entire memory array by dividing it into an area for recording binary data and an area for recording multi-valued data, and to externally store binary data. An object of the present invention is to provide a semiconductor memory device in which an area for recording and an area for recording multi-valued data can be treated as the same.

[0010]

SUMMARY OF THE INVENTION The present invention provides a memory array in which a storage area for multivalued data and a storage area for binary data can be set, and a method for writing / reading data to / from the memory array with multivalued data. Multi-level write / read control means for controlling, binary write / read control means for controlling writing / reading to / from the memory array with binary data, and external logical address to physical address of the memory array Address converting means for converting, and determining means for determining whether the physical address from the address converting means is in the multi-value storage area or in the binary storage area of the memory array, and based on the determination result of the determining means, A semiconductor memory device that switches between multi-level write / read control means and binary write / read control means.

Data requiring high reliability can be allocated to a binary area, and data requiring a large capacity can be allocated to a multilevel area. The multi-valued area and the binary area can be freely set by the mappin circuit 11, and the functions viewed from the outside are as follows.
The multi-value area and the binary area can be treated exactly the same.
In addition, the multi-value area and the binary area are configured by the same page latch circuit on the same memory array, and cost can be reduced.

[0012]

Embodiments of the present invention will be described below with reference to the drawings. In FIG. 1, reference numeral 1 denotes a flash-type nonvolatile semiconductor memory device, and reference numeral 2 denotes an external device. The nonvolatile semiconductor memory device 1 includes, for example, a NAND
It comprises a memory array 4 composed of cells and a memory control circuit 5. The memory cell array 4 and the memory control circuit 5 are connected via an internal signal line 6, and are housed in the same package. As the external device 2, for example, a personal computer, a digital video camera, a digital audio recording / reproducing device, or the like is used.

As shown in FIG. 2, the memory array 4 has a multi-level storage area MEM1 for storing multi-level (eg, 8-level) data in a memory cell and a binary storage area MEM2 for storing binary data in a memory cell. And is divided into: The memory control circuit 5 controls the multi-value area and the binary area so that they can be accessed identically from the outside. The external device 2 uses the binary area even when the multi-value area of the memory array 4 is used. In this case, exactly the same processing may be used. Further, the multi-value area M
The division position P between the EM1 and the binary area MEME2 can be freely set in block units.

In FIG. 1, an interface circuit 7 is provided in a memory control circuit 5. Data is exchanged between the external device 2 and the nonvolatile semiconductor memory device 1 by the external signal line 8 via the interface circuit 7.

The memory cell array 4 is a memory cell array of a NAND flash memory. Such N
The AND type memory cell array is configured as shown in FIG.

In FIG. 3, transistors MT0A to MT0M
T15A, MT0B to MT15B,... Are memory cell transistors having a floating gate. For example, 16 memory cell transistors MT0A to MT1
5A are connected in series, the select gate transistor SG1A is connected to the drain side of the series connection, and the select gate transistor SG2A is connected to the source side of the series connection to form the NAND string STA. Similarly, memory cell transistors MT0B to MT15B are connected in series, a select gate transistor SG1B is connected to the drain side of the series connection, and a select gate transistor SG2B is connected to the source side of the series connection to form NAND string STB. Be composed.

These NAND strings STA, ST
B are arranged side by side, and the gates of the corresponding select gate transistors and the gates of the memory cell transistors are commonly connected. In this example, the NAND string ST
The gates of the selection gates SG1A, SG1B,... Of A, STB,... Are connected to a common selection signal supply line DSG.
Memory cell transistors MT0A to MT15A, MT0
The gates of B to MT15B,... Are respectively connected to common word lines WL0, WL12,. NA
Select gate SG2 of ND strings STA, STB,...
, SG2B,... Are connected to a common selection signal supply line S.
Connected to SG.

Each of the NAND strings STA, STB,...
Transistors SG1A, S1 on the drain side select gate
G1B,... Are connected to bit lines BL0, BL1,. The transistors SG2A, SG2 of the selection gates on the source side of each of the NAND strings STA, STB,...
B are connected to the source line Vs, respectively.

These same selection signal supply lines DSG and S
SG, NAND connected to word lines WL0 to WL15
A block is composed of the strings STA, STB,. Data is erased in units of this block.

The pages PG0, PG1,... Are connected by the memory cells respectively connected to the same word lines WL0 to WL15.
The PG 15 is configured. Writing / reading of data is performed in units of the pages PG0, PG1,... PG15.

As shown in FIG. 4, the NAND string S
Blocks BLK0, BLK1, B from TA, STB, ...
LK2,... Are constituted, and these blocks BLK0, B
The memory cell array 4 is configured by arranging a plurality of LK1, BLK2,.

In the multi-value storage area MEM1, for example, if it is 8-value data, "111", "110", "10"
1 "," 100 "," 011 "," 010 "," 00
1 "," 000 ", the distribution level of the threshold value corresponding to each of the memory cell transistors MT0A to MT1 is set.
8A data are stored in 5A, MT0B to MT15B,. In the binary storage area MEM2, "1", "
The distribution level of the threshold value corresponding to "0" is set, and each of the memory cell transistors MT0A to MT15A, MT0B
ＭＴMT15B,... Store binary data.

FIG. 5 shows the configuration of the memory control circuit 5. The memory control circuit 5 includes a mapping circuit 11
Multi-level write / read control circuit 12 and binary write / read control circuit 13, multi-level write / read control circuit 12, and binary write / read control circuit 13
A switch circuit 14 for switching between the two, a block divided address register 15, an address comparator 16,
And a page address counter 17.

The mapping circuit 11 is a table for converting an address of a logical block and an address of a physical block. The logical block is an address of a block used when accessing from the external device 1. The physical block is a block number (BLK) of the memory array 4.
0, BLK1,...).

The mapping circuit 11 is a RAM or EEP
It is composed of a ROM. The mapping circuit 11 is supplied with the address of the logical block via the block address line 21 and is supplied with the address of the corresponding physical block via the data input / output line 22A, so that the memory cell is written. By doing
A conversion table between physical blocks and logical blocks is created.

FIG. 6 shows the configuration of the mapping circuit 11. As shown in FIG. 6A, the mapping circuit 11 includes logical blocks L1, L2,.
, And A1, B2,... And B1, B2,. As shown in FIG. 6B, physical blocks A1, A
.. Are multi-value areas, and physical blocks B1, B2,.
Is a binary region.

As shown in FIG. 6B, the logical block L1 is associated with the physical block B2, the logical block L2 is associated with the physical block A1, the logical block L3 is associated with the physical block A3, and the logical block L4 is associated with the physical block B1. In order to make the mapping correspond, a conversion table between a logical address and a physical address as shown in FIG. 6A is created in the mapping circuit 11.

When a logical address (represented by a signal line 21) corresponding to the logical block L1 is input by the mapping circuit 11, a physical address (represented by a signal line 24) corresponding to the physical block B2 in the binary area is output. When a logical address corresponding to the logical block L2 is input, a physical address corresponding to the physical block A1 in the multi-value area is output. When a logical address corresponding to the logical block L3 is input, the logical address in the multi-value area is input. When the physical address corresponding to the physical block A3 is output and the logical address corresponding to the logical block L4 is input, the physical block B1 in the binary area is output.
Is output.

The multilevel write / read control circuit 12 and the binary write / read control circuit 13 control writing / reading of the memory array 4. The memory array 4 includes, as shown in FIG.
1 and a binary storage area MEM2. When performing multi-level writing / reading on the memory array 4, a multi-level writing / reading control circuit 12 is used. When binary writing / reading is performed on the memory array 4, the binary writing / reading control circuit 1
3 is used. The multi-level write / read control circuit 12 and the binary write / read control circuit 13 are switched by a switch circuit 14.

The block number (B) for the memory array 4
LK0, BLK1,...) Are supplied from the mapping circuit 11 via a signal line 24. The page number (PG0, PG1,...) For the memory array 4 is stored in the address counter 17
Given by In the address counter 17, a page address is set as an initial value via the sector address line 23.

Data for the memory array 4 is input or output via a data input / output line 22. As described above, the reading / writing of data in the memory array 4 is performed in page units.
A paded data latch circuit 4A is provided.

As shown in FIG. 2, the memory array 4
In the block unit, the first half area is a multi-value storage area MEM1.
And a binary storage area MEM2 is allocated to the rest. When the memory array 4 is divided into the multi-value storage area MEM1 and the binary storage area MEM2, the division position P between the multi-value storage area MEM1 and the binary storage area MEM2 is sent to the division address register 15 and held. Is done. The output of the division address register 15 is supplied to one of the comparators 16.

A physical block address indicating the block numbers BLK0, BLK1, BLK2,... Of the memory array 4 is output from the mapping circuit 11 via a signal line 24.
This physical block address is supplied to the block row address of the memory array 4 and the comparator 1
6 to the other. The comparator 16 compares the address of the division position P between the multi-value area and the binary area held in the division address register 15 with the specified physical block address. The switch circuit 14 is switched by one bit of the comparison output of the comparator 16 and the page address counter 17 is controlled.

In the memory array 4, the first half of the area is assigned to the multi-value storage area MEM 1, and the rest is assigned to the binary storage area MEM 2. The divided address holding register 15 stores the multi-value storage area MEM 1 The division position P with the binary storage area MEM2 is held. Therefore, if the specified block address is smaller than the division position P, it is the multi-value storage area MEM1, and if the specified block address is larger than the division position P, it is the binary storage area MEM2. Therefore, the physical block address from the mapping circuit 11 is stored in the division address register 15 by the comparator 16 in the division position P.
If it is determined that the value is smaller than
The mode is switched to the 4A side, and the multi-level write / read control circuit 12 is selected. When it is determined that the physical block address from the mapping circuit 11 is larger than the division position P held in the division address register 15, the switch circuit 14 is switched to the terminal 14B side, and the binary write / read control circuit 13 is selected. Is done.

Further, the multi-value area MEM1 and the binary value area MEM
The size of the logical block is set so that 2 can be treated as the same block. That is, the multi-value area MEM1
In the binary area MEME2, one logical block corresponds to k physical blocks. Then, the page address counter 17 is set so that the multi-value area MEM1 and the binary area MEM2 can be treated as the same page. In the page reading / writing of the binary area, the page address counter 17 is activated by the comparator 16 to perform continuous access to k pages (k is an arbitrary integer) while increasing the page address.

When using the flash type nonvolatile semiconductor memory device 1, first, the area of the memory array 4 is divided into a multi-level area MEM1 and a binary area MEM2. Then, the block address of the division position between the multi-value area and the binary area is held in the division address register 15. In the mapping circuit 11, a conversion table between a logical address block and a physical address block is created.

When page writing is performed on the nonvolatile semiconductor memory device 1 by the external device 1, a block address is supplied from the external device 1 to the mapping circuit 11 via the block address line 21, and the sector address is supplied from the external device 1. Is supplied to the address counter 17 via the sector address line 23. The write data is supplied via the data input / output line 22 and is latched by the page data latch circuit 4A of the memory array 4.

The mapping circuit 11 converts the logical block address from the external device 1 into a physical block address. The block address of the memory array 4 is specified by the physical block address, and the comparator 16 compares the physical address with the address of the division position P between the multi-value area and the binary area.

If the physical address is smaller than the address of the division position P between the multi-value area and the binary area, the multi-value write / read control circuit 12 causes the page data latch circuit 4
The write data latched in A is written to the memory array 4 in a multi-valued manner. Physical address is multi-value area and 2
If the address is larger than the address of the division position P with the value area, the write data latched in the page data latch circuit 4A by the binary write / read control circuit 13 is:
The binary data is written to the memory array 4. When performing binary writing, the address counter 17 sequentially writes k pages.

When data is read from the nonvolatile semiconductor memory device 1, a block address is supplied from the external device 1 to the mapping circuit 11 via the block address line 21, and a sector address is supplied from the external device 1 to the sector address line 23. To the address counter 17 via

The mapping circuit 11 converts a logical block address from the external device 1 into a physical block address. The block address of the memory array 4 is specified by the physical block address, and the comparator 16 compares the physical address with the address of the division position P between the multi-value area and the binary area.

If the physical address is smaller than the address of the division position P between the multi-value area and the binary area, the data in the memory array 4 is read by the multi-value write / read control circuit 12 in multi-value, and the page data latch The signal is latched by the circuit 4A. If the physical address is larger than the address of the division position P between the multi-value area and the binary area, the binary write / read control circuit 13 causes the data in the memory array 4 to be 2
The value is read out and latched by the page data latch circuit 4A. When binary writing is performed, k pages are sequentially read by the address counter 17.

The read data latched by the page data latch circuit 4A is output to the outside via the data input / output line 22 and sent to the external device 1.

In the above-described example, the multi-value area has eight values, but the present invention is not limited to this. Further, in this example, the multi-value area is arranged in the first half of the memory array, and the binary area is arranged in the second half of the memory array. However, the arrangement of the areas is not limited to this. Further, the memory array area may be divided into a plurality of areas, and each area may be set as a binary area or a multi-value area.

[0045]

According to the present invention, data requiring high reliability can be allocated to a binary area, and data requiring a large capacity can be allocated to a multilevel area. The multi-value area and the binary area can be freely set by the mappin circuit 11, and the functions seen from the outside are as follows.
Both the page, which is the unit of writing / reading, and the block, which is the unit of erasing, can be handled exactly the same in the multi-value area and the binary area. Further, the multi-value area and the binary area are:
Since the same page latch circuit is formed on the same memory array, the cost can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram used for describing a nonvolatile semiconductor memory device to which the present invention is applied.

FIG. 2 is a schematic diagram used for describing division of a memory region in a nonvolatile semiconductor memory device to which the present invention is applied;

FIG. 3 is a connection diagram used to describe a memory cell in a nonvolatile semiconductor memory device to which the present invention is applied;

FIG. 4 is a block diagram used for describing a memory cell in a nonvolatile semiconductor memory device to which the present invention is applied;

FIG. 5 is a block diagram used for explaining a memory control circuit in the nonvolatile semiconductor memory device to which the present invention is applied;

FIG. 6 is a block diagram used for explaining a mapping circuit in a nonvolatile semiconductor memory device to which the present invention is applied;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Non-volatile semiconductor memory device, 2 ... External storage device, 4 ... Memory array, 11 ... Mapping circuit, 15 ... Split address register, 16 ... Comparator

Claims (2)

[Claims] 1. A memory array capable of setting a storage area for multi-valued data and a storage area for binary data, and a multi-valued write / read for controlling writing / reading to / from the memory array with multi-valued data. Control means; binary write / read control means for controlling writing / reading to / from the memory array with binary data; address conversion means for converting an external logical address to a physical address of the memory array Determining means for determining whether the physical address from the address conversion means is in the multi-value storage area or in the binary storage area of the memory array, and based on the determination result of the determination means, A semiconductor memory device that switches between value write / read control means and binary write / read control means. 2. The method according to claim 1, wherein the determining means includes: a division address holding means for holding an address of a division position between the multi-value data storage area and the binary data storage area; a physical address from the address conversion means; Comparing means for comparing the address of the divided position held in the divided address holding means with the physical address from the address conversion means and the address of the divided position held in the divided address holding means. 2. The semiconductor memory device according to claim 1, wherein whether the logical address is in a multi-value storage area or a binary storage area of the memory array is determined from the value.