JP2000172738A - Automatic layout method for lsi - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain an automatic layout method for an LSI which prevents delay violation path from occurring. SOLUTION: Necessary information is inputted (S101), all cells are automatically arranged (S102), the initial outline wiring for the entire net is carried out (S103), the delay time of each path is calculated in a delay analysis process 104, and a critical path violating the delay constraint value of each path. The results of this analysis are decided (S105), processing is returned to an arrangement processing process 102 when there is a critical path, and the processing is shifted to the next improvement outline wiring process 106 when no critical path exists. In the process 106, an initial outline wiring route and a wiring layer where wiring delay becomes minimum are allocated to a net having a strict delay constraint value, and a net outline wiring route and a wiring layer are allocated to nets other than the net so as to relieve the degree wiring congestion. In a detailed wiring process 107, a detailed wiring route is decided, based on the allocated outline wiring route.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an automatic layout method for a multilayer wiring LSI.

[0002]

2. Description of the Related Art Conventionally, an automatic layout method of an LSI is generally configured as an automatic layout method in consideration of timing constraints. In particular, in recent years, wiring has become finer due to the development of LSI manufacturing technology, and the number of wiring layers has been increased. In such a tendency, the wiring resistance is increased due to the miniaturization of the wiring, and the increase in the delay time due to the wiring is more dominant than the rate at which the gate circuit delay is reduced. For this reason, it is an important subject to design an LSI layout in consideration of timing constraints.

As a conventional layout method using wiring capacitance and wiring resistance per unit length of each wiring layer, for example, there is a method disclosed in the following publication.

[0004] Japanese Patent Application Laid-Open No. 3-335564 discloses a technique for performing delay analysis based on the delay value of a wiring layer having the largest delay value after placement and the virtual wiring length of each net. In Japanese Patent Application Laid-Open No. Hei 6-118900 of Conventional Example 2, a net delay value is detected after a conventional general wiring,
A technique for allocating a net to a wiring layer within a delay value range of the net is disclosed.

[0005]

However, in the above-described automatic layout method in consideration of the timing constraints, when calculating the wiring delay time of each net, the wiring capacitance per unit length and the wiring resistance are determined by the wiring of the net. The calculation is performed using one type of a typical type without using the layer according to the layer. For a net having a severe delay constraint, attention is paid only to shortening the wiring length.

For this reason, even if the wiring capacitance and wiring resistance per unit length used in the calculation are within the allowable values, the actual wiring capacitance and wiring resistance of the layer to which the wiring after detailed wiring is allocated is not affected. If there is a difference, a delay violation may occur. In particular, there is a problem that the wiring delay of the net differs greatly when the wiring length is long.

The virtual wiring length of the net disclosed in Japanese Patent Application Laid-Open No. 3-335564 in the prior art 1 may have a large difference from the actual wiring length of the net up to the detailed wiring.
Therefore, the net may be different from the net actually detected as a violation net. Further, the delay value of the wiring layer having the largest delay value is used for calculating the wiring delay time. For this reason, many nets are detected as violating nets, and are roughly wired preferentially, causing a problem in wiring accommodation.

Further, Japanese Patent Application Laid-Open No. 6-118900
In the publication, there is a problem that when a wiring length of a net becomes long at the time of general wiring, the delay constraint is not satisfied even if it is assigned to a wiring layer having a minimum delay value.

According to the present invention, L which does not cause a delay violation path is generated.
An object of the present invention is to provide an automatic layout method for SI.

[0010]

In order to achieve the above object, an automatic layout method for an LSI according to the present invention comprises an information input step of inputting information required for layout design, and an automatic arrangement of all cells. A placement processing step to be performed, an initial rough routing step for performing rough routing of all nets, a delay analysis step for calculating a delay time of each path and extracting a critical path that violates a delay constraint value of each path, and a delay analysis When there is a critical path in the process, the process returns to the placement processing step, and when there is no critical path, the process shifts to the next improved schematic routing process. Is assigned to the initial schematic routing path and the wiring layer that minimizes the wiring delay, and to the other nets, An improved global routing step of allocating a line layer, and characterized in that it is configured to have a detailed wiring determining a detailed wiring path on the basis of the rough wiring path, the.

The information required in the information input step is information including logical connection information, physical library information, delay library information, and path delay constraint information. It is desirable to have an improved placement function of cells related to nets on the critical path.

Further, the initial schematic wiring step is a step of obtaining a schematic wiring path of each net with the shortest path, and the delay analyzing step is a step of calculating the initial schematic wiring path of each net and a unit of a wiring layer having a minimum delay value. It may be a processing step of calculating a net wiring delay time and a path delay time using a wiring capacity per length and a wiring resistance value, and detecting a critical path violating the delay constraint value of the path.

In the delay analysis step, the product of the wiring capacitance and the wiring resistance per unit length is calculated for each wiring layer to which the horizontal wiring is allocated, and the wiring layer having the smallest value is determined by the wiring layer to which the horizontal wiring is allocated. Calculate the product of the wiring capacitance per unit length and the wiring resistance for each wiring layer to which the vertical wiring is assigned, and assign the vertical wiring to the wiring layer with the smallest value. It is good to use the wiring layer having the shortest delay time among the above.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of an automatic layout method for an LSI according to the present invention will be described in detail with reference to the accompanying drawings. FIG. 1 shows an embodiment of an automatic layout method for an LSI according to the present invention.

FIG. 1 is a flowchart showing an example of the automatic layout method according to the embodiment. This method is an automatic layout method applied to an LSI having a multilayer structure and different wiring capacities and wiring resistances per unit length of each wiring layer.

The automatic layout method according to this embodiment includes an information input step 101 for inputting information, an arrangement processing step 102 having an improved cell arrangement function, and an initial schematic wiring step 10.
3 and a delay analysis step 104 for detecting a critical path
A delay violation path determination step 105; and an improved schematic wiring step 10 for allocating a schematic wiring path and a wiring layer of a net.
6 and a detailed wiring step 107.

The information input step 101 is a step of inputting information necessary for designing a layout such as logical connection information, physical library information, delay library information, and path delay constraint information. The logical connection information is information on a logical connection relationship between logical elements (gates) forming a circuit. The physical library information is information necessary for laying out the LSI, such as the size of the LSI to be designed, the size of each gate type, the terminal position, and the width of the wiring.
The delay library information is information for calculating a delay value of a wiring between logic elements such as a capacitance per unit length of each wiring layer and a resistance value, and information such as an internal delay value of each gate.

The placement processing step 102 has an initial automatic placement of cells and an improved placement function of cells related to a net on a critical path.

The initial general wiring step 103 is a step of obtaining a general wiring path of each net with the shortest path.

The delay analysis step 104 calculates a net wiring delay time and a path delay time using the initial schematic wiring path of each net and the wiring capacitance and wiring resistance per unit length of the wiring layer having the minimum delay value. This is a processing step of detecting a critical path violating the path delay constraint value.

The determination step 105 returns to the placement processing step 102 when there is a critical path in the delay analysis step 104, and shifts the processing to the improved schematic routing step 106 when there is no critical path. This is the step of performing

The improved schematic routing step 106 assigns an initial schematic routing path to a net having a severe delay constraint value and a wiring layer having the smallest wiring delay, and assigns a net to other nets so as to reduce the degree of wiring congestion. This is a step of allocating a general wiring path and a wiring layer.

The detailed wiring step 107 is a step of determining a detailed wiring path based on a schematic wiring path.

(Description of Operation) An operation example of the embodiment of FIG. 1 will be described below. In an information input step 101, information necessary for layout design is input. As necessary information,
Input logical connection information, physical library information, delay library information, and path delay constraint information.

The capacitance and resistance per unit length of each wiring layer vary depending on the manufacturing parameters such as the wiring width, wiring height, and material of each layer. Generally, the wiring capacitance is proportional to the wiring width and the wiring height. However, the wiring resistance decreases in inverse proportion to the width and height. In the input of path delay constraint information, a path delay constraint value attached to each inter-flip-flop path is input.

Next, in step 102, all cells are automatically arranged. In step 103, general wiring of all nets is executed. At this time, the schematic wiring operates for the purpose of minimizing the wiring length of each net, and here, the wiring congestion degree is not considered,
Determine a schematic wiring path. At this point, the wiring length of each net is the shortest.

In step 104, the delay time of each path is calculated, and a critical path violating the delay constraint value of each path is extracted. The delay time of a path can be represented by the sum of the internal delay time of a gate through which a signal passes and the wiring delay time of each net. Here, the wiring delay time of the net is Elmore
Is calculated by the RC model of

FIG. 2 shows an example of calculation of the wiring delay time. In FIG. 2, the horizontal wiring segment S1 is allocated to the wiring layer 1, the vertical wiring segment S2 is allocated to the wiring layer 2, and the horizontal wiring segment S3 is allocated to the wiring layer 3. The wiring delay time TAB from the output terminal A to the input terminal B in FIG.
Generally, it is calculated by the following equation 1, and the output terminal A is connected to the input terminal C.
The wiring delay time TAC up to is calculated by the following equation 2.

TAB = RA (C1 · L1 + C2 · L2 + C3 · L3 + CB + CC) + r1 · L1 (C1 · L1 / 2 + C2 · L2 + C3 · L3 + CB + CC) + r3 · L3 (C3 · L3 / 2 + CB) (Equation 1)

TAC = RA (C1 · L1 + C2 · L2 + C3 · L3 + CB + CC) + r1 · L1 (C1 · L1 / 2 + C2 · L2 + C3 · L3 + CB + CC) + r2 · L2 (C2 · L2 / 2 + CC) (Equation 2)

The symbols in the above equations 1 and 2 are as follows. RA: Output resistance of output terminal CB: Terminal capacitance of input terminal B CC: Terminal capacitance of input terminal C L1 to L3: Line length of wiring segments S1 to S3 C1 to C3: Wiring capacitance per unit length of each wiring layer r1 To r3: wiring resistance per unit length of each wiring layer

As described above, the RC of each segment is extracted by using the wiring capacitance per unit length and the wiring resistance value of the wiring layer to which each wiring is allocated. In the wiring delay analysis step 104, the horizontal wiring segment is extracted. Is calculated using the wiring capacitance and the wiring resistance per unit length of the layer having the shortest wiring delay time among the wiring layers to which the wiring is mainly allocated in the horizontal direction. Similarly, when extracting the RC of the vertical wiring segment,
The calculation is performed using the wiring capacitance and the wiring resistance per unit length of the layer having the shortest wiring delay time among the wiring layers to which wiring is mainly allocated in the vertical direction.

Next, the layer in which the wiring delay time of the wiring is minimized will be described. The output terminal O to the input terminal i in FIG. 3 are connected by one wiring segment in the same wiring layer. At this time, the wiring delay time from the output terminal O to the input terminal i can be calculated by Expression 3.

[0034] T = Ro (C · L + Ci) + r · C · L 2/2 + r · L · Ci ... ( Equation 3)

The symbols in the above equation (3) are as follows. Ro: Output resistance of output terminal O Ci: Terminal capacitance of input terminal i L: Line length of wiring segment C: Wiring capacitance per unit length of arbitrary wiring layer r: Wiring resistance per unit length of arbitrary wiring layer

FIG. 4 is a graph showing the relationship between the wiring length A and the wiring delay time T when the wiring length L is changed under the conditions at this time. In FIG. 4, wiring layers A and B
Is the wiring capacitance per unit length of CA, CB, and the wiring resistance per unit length of wiring layers A and B is r.
Let A and rB satisfy the following conditions.

CA <CB, rA> rB

In general, when the wiring width and the wiring height of the wiring layer increase, the wiring capacitance per unit length of the wiring layer also increases, but the wiring resistance per unit length decreases. As is known from Equation 3 and FIG. 4, the wiring delay time increases in proportion to the wiring length. Also, from equation 3, when the wiring length becomes longer, r
It is largely controlled by C (product of wiring capacitance and wiring resistance per unit length). When the wiring length is short, the difference in wiring delay time between wiring layers to which wiring is allocated is small, and when the wiring length is long, the difference in wiring delay time between wiring layers becomes large. For this reason, in step 104 of the delay analysis, the product of the wiring capacitance per unit length and the wiring resistance is calculated for each wiring layer to which the horizontal wiring is allocated, and the wiring layer having the smallest value is the wiring layer to which the horizontal wiring is allocated. And the wiring layer having the shortest delay time. Similarly, the product of the wiring capacitance per unit length and the wiring resistance is calculated for each wiring layer to which the vertical wiring is allocated, and the wiring layer with the smallest value is the wiring layer with the shortest delay time among the wiring layers to which the vertical wiring is allocated. It is a wiring layer.

Therefore, in the delay analysis step 104, the delay time when the wiring length of each net is shortest and the wiring delay time is shortest in the current placement result is calculated. That is, since the path delay time also has the minimum value, the delay analysis is performed using the path delay time when the best result is obtained in the schematic wiring, and a critical path that violates the path delay is extracted.

In the step 105 for judging the presence or absence of a delay violation path, if a critical path exists in the step 104 of the delay analysis, it is clear that there is a critical path that cannot be corrected in the subsequent wiring processing. For this reason, the process returns to the arrangement processing of step 102 again,
The cell arrangement position is changed so that the wiring delay time of the net on the critical path is improved. The processes of steps 102 to 104 are repeated until the critical path disappears or the improvement cannot be further improved. If the critical path has disappeared, the process is shifted to the improved schematic routing in step 106.

FIG. 5 shows an example of the arrangement state before the arrangement improvement, and FIG. 6 shows an example of the arrangement state after the arrangement improvement. In FIG. 5, gates 302, 303,
305 are connected by nets 401, 402, 403, and 406. From the output terminal P2 of the gate 301 to the gate 3
02, input terminal P3, output terminal P4, input terminal P5 of gate 303, output terminal P6, input terminal P of gate 305.
9. Pass through the output terminal P10, flip-flop 306
And the gates 302, 304, 30 between the flip-flops 301, 309 and the path reaching the input terminal P11
7, 308 are nets 401, 402, 405, 407,
408 are connected. From the output terminal P2 of the flip-flop 301 to each terminal P3, P4, P7, P
8, pass the route of P13, P14, P15, P16,
There is a path reaching the input terminal P17 of the flip-flop 309.

In the initial schematic wiring in step 103,
Since the wiring is prohibited on the hard macro 310, the net 4
05 cannot pass through the hard macro 310, and the general wiring path of the net 405 is bypassed.
In the delay analysis of the subsequent step 104, the path between the flip-flops 301 and 306 satisfies the delay constraint, and the path between the flip-flops 301 and 309 is detected as a critical path violating the delay constraint. In step 105, since the critical path exists, the process returns to step 102. Returning to step 102 again, step 1
In 02, the path between the flip-flops 301 and 309 has violated the result of the delay analysis in step 104. For this reason, the operation is performed to change the arrangement position of the cells related to this path and to improve the delay time of the path. FIG. 6 shows the result.

By changing the positions of the gates 304, 307, 308 and the flip-flop 309, the delay constraint on the path between the flip-flops 301, 309 is satisfied.

In step 106, based on the result of the delay analysis in step 104, the improved schematic routing is performed on the initial schematic routing result in step 103 so as to reduce the degree of wiring congestion. In the result of the delay analysis in step 104, it is possible to distinguish between a net with a severe delay and a net other than the net. For a net having a severe delay, an initial schematic wiring path may be taken and assigned to a wiring layer having a short wiring delay time.
For other nets, general wiring routes and wiring layers are allocated so as to reduce the degree of wiring congestion.

In addition, in order to prevent the wiring channel from overflowing from the order of the net having the stricter delay as a result of the delay analysis result in step 104, the general wiring path and the wiring layer where the wiring delay is advantageous are allocated so that the general wiring path becomes shortest again. The general wiring may be redone by the method. In step 107, detailed wiring is performed based on the schematic wiring path in step 106.

According to the flow of the series of processes, a layout result in which a violation path is unlikely to be generated can be automatically realized.

The above embodiment has described the automatic layout design of an LSI having three or more wiring layers having different wiring resistance and wiring capacitance per unit line length of each layer. In the present embodiment, delay analysis is performed in a state where the wiring length of each net is assigned to the wiring layer with the shortest delay value in the shortest schematic path, that is, the wiring delay time of each net is minimized. Detect delay violation paths that cannot be improved. Based on this detection, the delay violation path is corrected by re-arrangement, and a rough wiring path is allocated to a wiring layer having a small delay value without increasing the wiring length for a net having a strict delay constraint. , An automatic layout method that does not cause the problem can be obtained.

The above embodiment is an example of a preferred embodiment of the present invention. However, it is not limited to this.
Various modifications can be made without departing from the spirit of the present invention.

[0049]

As is apparent from the above description, the LSI automatic layout method of the present invention allocates a wiring path having the shortest wiring length to a wiring layer advantageous in terms of delay for a net with severe delay constraints. Wiring is performed on a net having a sufficient delay constraint in consideration of the degree of wiring congestion. For this reason, the layout can be achieved without violating the delay constraint without deteriorating the wiring accommodability of the LSI.

After the placement, the general wiring route of each net is allocated to the wiring layer having the shortest wiring length and the shortest delay. Therefore, the timing analysis is performed with the wiring delay time of each net being the shortest. For this reason, it is possible to detect a delay violation path that cannot be resolved after the schematic routing, and to carry out a delay violation having a problem with a cell arrangement position to a subsequent process without fail and correct the path delay violation arrangement. Since the conventional general routing is performed, the number of layout corrections in a long processing unit called placement and routing can be reduced,
As a result, man-hours required for layout design can be reduced.

[Brief description of the drawings]

FIG. 1 is a flowchart illustrating an example of an embodiment of an LSI automatic layout method according to the present invention.

FIG. 2 is a conceptual diagram illustrating a calculation example of a wiring delay time.

FIG. 3 is a diagram for describing a layer in which a wiring delay time of a wiring is minimized.

FIG. 4 is a diagram showing a graph of a relationship between a wiring delay time T when a wiring is formed in arbitrary wiring layers A and B and a value of a wiring length L changes.

FIG. 5 is a diagram illustrating an example of an arrangement state before the arrangement is improved.

FIG. 6 is a diagram showing an example of an arrangement state after the arrangement is improved.

[Explanation of symbols]

 101 information input step 102 placement processing step 103 initial rough wiring step 104 delay analysis step 105 determination step 106 improved rough wiring step 107 detailed wiring step

Claims (6)

[Claims] An information input step of inputting information necessary for performing a layout design; an arrangement processing step of automatically arranging all cells; an initial schematic wiring step of executing global wiring of all nets; A delay analysis step of calculating a path delay time and extracting a critical path that violates a delay constraint value of each path; and, if there is a critical path in the delay analysis step, returning the processing to the placement processing step; If there is no, a process of determining whether or not there is a delay violation path that shifts the process to the next improved schematic routing process, and assigning the initial schematic routing route and the wiring layer with the smallest wiring delay to the net with a severe delay constraint value, An improved schematic routing step for allocating a schematic routing path and a wiring layer to the other nets so as to reduce the degree of wiring congestion; A detailed wiring step of determining a line path; and an automatic layout method for an LSI. 2. Information required in the information input step includes logical connection information, physical library information, delay library information,
2. The automatic layout method for an LSI according to claim 1, wherein the information includes path delay constraint information. 3. The automatic layout method for an LSI according to claim 1, wherein said placement processing step has an initial automatic placement of cells and an improved placement function of cells related to a net on a critical path. . 4. The LSI automatic layout method according to claim 1, wherein said initial schematic routing step is a step of obtaining a schematic routing path of each net by a shortest path. 5. The delay analysis step comprises: using a net initial wiring path of each net, a wiring capacitance per unit length of a wiring layer having a minimum delay value, and a wiring resistance value, the net wiring delay time and the path delay. 5. The LSI automatic layout method according to claim 1, further comprising a processing step of calculating a time and detecting a critical path violating a delay constraint value of the path. 6. The delay analysis step calculates a product of a wiring capacitance per unit length and a wiring resistance for each wiring layer to which a horizontal wiring is allocated, and determines a wiring layer having the smallest value as a wiring layer to which a horizontal wiring is allocated. Calculate the product of the wiring capacitance and wiring resistance per unit length for each wiring layer to which the delay time is the shortest, and for each wiring layer to which the vertical wiring is to be allocated, and assign the wiring layer with the smallest value to the vertical wiring. 6. The automatic layout method for an LSI according to claim 5, wherein the wiring layer has the shortest delay time among the layers.