JP2000152177A - Data processor and its method, and data reproducing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To interpolate an ID number and ID information even when SYNC blocks of different length are intermingled. SOLUTION: A delay line DL 51 whose length is (2L+α) can store two SYNC blocks whose length is L and three IDs of them. An acquisition section 60 stores the ID of an input SYNC block. A management section 62 counts number of the IDs stored in the DL 51. An ID generating section 61 selects a plurality of the IDs with the counted value of three stored in the management section 60 in a relation in cross reference with the IDs stored in the DL 51 and generates a plurality of interpolation IDs. Based on error information of SYNC blocks in the DL 51, the interpolation ID selected by a plurality of the interpolation IDs is superimposed on the SYNC block. In the case of receiving the SYNC block with a length K, where a relation of 2K>L>K holds, the count is 4 and a plurality of the IDs are selected. The number of the IDs stored in the DL 51 is counted to cope with the SYNC blocks of different length.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing apparatus and method capable of interpolating the ID of a synchronous block in which an error has occurred even when decoding a data string having synchronous blocks of a plurality of lengths, And a data reproducing apparatus.

[0002]

2. Description of the Related Art In recent years, digital video tape recorders, which use a magnetic tape as a recording medium and record and reproduce digital video signals and digital audio signals, are becoming widespread.

In such an apparatus, digital video data and digital audio data are stored in packet units of a predetermined length, and each packet has a synchronization pattern for detecting synchronization, an ID number for identifying each packet, and a data. The sync block is configured by adding ID information indicating the contents of the above and parity for error correction.
Then, the sync blocks are grouped into sectors according to the type of data, and are recorded on the magnetic tape as serial data in sector units. Recording is performed by a helical scan method in which tracks are formed diagonally on a magnetic tape by a rotating head.

At the time of recording, the length of each sync block in the same sector is the same, the ID numbers are continuous, and the ID information has the same value. The error correction coding is performed by, for example, a product code that performs double coding of an outer code and an inner code.

FIG. 21 schematically shows an example of the arrangement of each sector on a track. The rotating head traces from the left side to the right side of the figure to form a track. As described above, the track is actually formed obliquely with respect to the magnetic tape, and one frame of video data is recorded using a plurality of, for example, four tracks. A plurality of audio sectors for recording audio data are arranged between video sectors for recording video data. In this example, C
Since audio signals for eight channels from h1 to Ch8 can be handled, eight audio sectors A1 to A8 are arranged.

[0006] Between each sector, an edit gap (E) in which audio data is not recorded is inserted so that, for example, insert editing can be performed in sector units of an audio signal.
G) is arranged. A preamble is provided at the beginning of the track. In the preamble, a signal that makes it easy for the PLL for the reproduction clock to lock during reproduction, for example, data of “FF (hexadecimal notation)” is repeatedly recorded. Further, the shortest recording wavelength on the recording medium depends on the data amount for one track.

At the time of reproduction, tracks on the magnetic tape are traced by the rotating head, and a reproduction signal is obtained.
From the reproduced signal, a sync detection circuit detects a synchronization pattern from a reproduction bit string synchronized with the reproduction clock, adjusts the phase of the sync block, and cuts out the sync block.

[0008] The extracted sync block is subjected to inner code correction by the inner code parity added at the time of recording. If an error exists that exceeds the error correction capability of the error correction code, the data is not corrected and an error flag is set. The data that has been subjected to the inner code correction processing includes an ID number and an I
Based on the D information, rearrangement is performed in the outer code direction using, for example, a RAM, and outer code correction is performed.

At this time, the ID number and the ID
Since the information is used, if the ID number and ID information of the erroneous sync block are used as they are, inconvenience such as overwriting of normal data occurs. Therefore, the ID number and the ID information in which the error has occurred are used by being interpolated. For example, the ID numbers and ID information of the erroneous sync blocks are interpolated using the data of the previous and next sync blocks in the same sector.

Conventionally, since the length of the sync block is fixed, the above-described data interpolation may be performed at a predetermined timing, and the processing is not complicated.

[0011]

However, in recent years,
Video formats have been diversified due to the realization of digital broadcasting and the like, and a large number of video mats having different image frame sizes and different compression rates of video data have appeared. Also, video data has a huge capacity,
Normally, recording, reproduction and transmission are performed by compression encoding. Here, in order to cope with such various formats, for example, consider a multi-format digital video tape recorder capable of selecting a plurality of compression rates of video data and recording / reproducing.

When the compression ratio of video data is variable and the audio data is uncompressed, the length of the data packet of the video data and the length of the packet of the audio data are determined by:
It is difficult to always be the same. Therefore, each packet is made to have a different length. Therefore, in this case, the length of the sync block differs between video and audio.

When a plurality of sync blocks having different lengths coexist in one format, the timing of interpolation differs depending on the length of the sync blocks. Therefore, when the ID number and the ID information are interpolated by the above-described conventional method, there is a problem that a process and a circuit suitable for the length need to be prepared individually.

[0014] Therefore, there are problems that it is difficult to adjust the timing of each circuit and that the circuit scale becomes large.

Therefore, an object of the present invention is to provide a data processing apparatus and method capable of interpolating ID numbers and ID information even when sync blocks of different lengths are mixed, and a data reproducing apparatus each time. Is to do.

[0016]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problem, the present invention provides a method for decoding identification data of a data block supplied by decoding an error correction code added in units of a predetermined length. In a data processor configured to interpolate blocks up to p blocks, a data block to which identification information is added at a predetermined position is decoded by error correction coding performed at the time of recording, and is input. A memory means for storing a plurality of data blocks, a plurality of data blocks stored in the memory means, from among the held identification information, holding a plurality of identification information of the input data block in the identification information holding means; Identification information selecting means for selecting a plurality of pieces of identification information corresponding to each other; and identification information added to a data block stored in the memory means. Is counted, and when the count value reaches a predetermined value, a plurality of pieces of identification information generated from a plurality of pieces of identification information selected by the identification information selecting means based on error information obtained by decoding the sync block stored in the memory. Interpolation identification information selecting means for selecting interpolation identification information for interpolating identification information of a sync block corresponding to error information from interpolation identification information, and interpolation identification information corresponding to error information output from a memory means. Means for superimposing on the sync block thus selected, and when the interpolation identification information is selected by the interpolation identification information selecting means, the count value is decremented.

Further, the present invention reproduces data recorded on a recording medium after being subjected to error correction coding in units of a predetermined length to which identification information is added, and identifies the identification information of a data block in which the reproduced data is decoded. And the data block
In a data reproducing apparatus designed to interpolate up to the number of pieces of data, identification information is added at a predetermined position, error correction coding is performed in units of a predetermined length block, and data recorded on a recording medium is reproduced. Means for decoding, a memory means for storing a plurality of data blocks reproduced by the reproducing means, and a plurality of identification information of the data blocks reproduced by the reproducing means, held in the identification information holding means, Identification information selecting means for selecting, from among the identification information, a plurality of pieces of identification information corresponding to a plurality of data blocks stored in the memory means; and identification information added to the data blocks stored in the memory means. The number of information is counted, and when the count value reaches a predetermined value, error information due to decoding of the sync block stored in the memory is obtained. From the plurality of pieces of interpolation identification information generated from the plurality of pieces of identification information selected by the identification information selection means based on the interpolation identification information for interpolating the identification information of the sync block corresponding to the error information Information interpolation means for superimposing the interpolation identification information on the sync block output from the memory means and corresponding to the error information. When the interpolation identification information is selected by the interpolation identification information selection means, counting is performed. A data reproducing apparatus characterized in that a value is decremented.

Further, according to the present invention, identification information of a data block supplied by decoding an error correction code added in units of a predetermined length block is interpolated retroactively up to p data blocks. In the data processing method, a data block to which identification information is added at a predetermined position is input after decoding error correction coding performed at the time of recording, and a plurality of data blocks input to the memory unit are stored. And a plurality of identification information of the input data block held in the identification information holding means, and a plurality of identification information corresponding to the plurality of data blocks stored in the memory means among the held identification information. Counting the number of identification information added to the data block stored in the memory means. When the count value becomes a predetermined value,
Based on the error information obtained by decoding the sync block stored in the memory, a sink corresponding to the error information is selected from among a plurality of interpolation identification information generated from a plurality of identification information selected in the identification information selection step. A step of selecting interpolation identification information for interpolating the identification information of the block; and a step of superimposing the interpolation identification information on a sync block output from the memory means and corresponding to the error information. The data processing method is characterized in that, when the interpolation identification information is selected by the interpolation identification information selection step means, the count value is decremented.

As described above, according to the present invention, a plurality of input data blocks are stored in the memory means, the number of identification information added to the data blocks is counted, and the plurality of input data blocks are stored. Data block identification information is held. A plurality of pieces of identification information to be used for interpolation based on the count value are selected from the plurality of pieces of identification information held so as to correspond to the identification information of the plurality of data blocks stored in the memory means. Based on the error information of the plurality of data blocks stored in the memory means, an appropriate one of the plurality of identification information used for interpolation is selected, and the selected identification information is superimposed on the data block output from the memory means. Is done. Since the number of pieces of identification information of the data blocks stored in the memory means is counted and the identification information to be used for interpolation is selected based on the count value, data blocks having different lengths can be handled.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described with reference to digital VC.
An embodiment applied to R will be described. This embodiment is suitable for use in a broadcast station environment,
Recording and recording of video signals of multiple different formats
It enables playback. For example, a signal (480i signal) having 480 effective lines in the interlaced scanning based on the NTSC system and a signal (576 signals) having 576 effective lines in the interlaced scanning based on the PAL system.
i) are recorded with almost no hardware changes.
It is possible to reproduce. Furthermore, a signal having 1080 lines (1080i signal) in interlaced scanning,
In progressive scanning (non-interlace), the number of lines is 480, 720, and 1080, respectively.
Recording / reproduction such as 0p signal, 720p signal, and 1080p signal) can also be performed.

In this embodiment, a video signal is compression-encoded based on the MPEG2 system, and an audio signal is handled uncompressed. As is well known, MPEG
No. 2 is a combination of motion compensation predictive coding and compression coding by DCT. The data structure of MPEG2 has a hierarchical structure, and includes a block layer, a macroblock layer, a slice layer, a picture layer, a GOP layer, and a sequence layer from the lowest level.

The block layer is a unit for performing DCT, D
It consists of a CT block. The macroblock layer includes a plurality of D
It is composed of CT blocks. The slice layer is composed of a header section and any number of macroblocks that do not extend between rows. The picture layer includes a header section and a plurality of slices. A picture corresponds to one screen. G
The OP (Group Of Picture) layer includes a header portion, an I picture that is a picture based on intra-frame coding, and P and B pictures that are pictures based on predictive coding.

An I-picture (Intra-coded picture) uses information that is closed only in one picture when it is coded. Therefore, at the time of decoding, decoding can be performed using only the information of the I picture itself. A P-picture (Predictive-coded picture: a forward predictive coded picture) uses a previously decoded I-picture or P-picture which is temporally previous as a predicted picture (a reference picture for taking a difference). . Whether to encode the difference from the motion-compensated predicted image, to encode without taking the difference,
The more efficient one is selected for each macroblock. A B picture (Bidirectionally predictive-coded picture) is a temporally previous I-picture or P-picture which is temporally preceding, and a temporally backward I-picture, We use three types of I-pictures or P-pictures already decoded, as well as interpolated pictures made from both. Among the three types of difference coding after motion compensation and intra coding, the most efficient one is selected for each macroblock.

Therefore, as the macroblock type,
Intra-frame coding (Intra) macroblock, forward (Fward) inter-frame prediction macroblock predicting the future from the past, and backward (Backward) interframe prediction macroblock predicting the future from the future, There is a bidirectional macroblock to be predicted. All macroblocks in an I picture are intra-coded macroblocks. The P picture includes an intra-frame coded macro block and a forward inter-frame predicted macro block. The B picture includes all four types of macroblocks described above.

A GOP contains at least one I picture, and P and B pictures are allowed even if they do not exist. The top sequence layer is composed of a header section and multiple GOPs.
It is composed of

In the MPEG format, a slice is one variable-length code sequence. A variable-length code sequence is a sequence in which a data boundary cannot be detected unless a variable-length code is decoded.

At the head of the sequence layer, GOP layer, picture layer, slice layer, and macroblock layer, an identification code (referred to as a start code) having a predetermined bit pattern aligned in byte units is provided. Be placed. Note that the header section of each layer described above collectively describes a header, extension data, or user data. In the header of the sequence layer, the size of the image (picture) (the number of vertical and horizontal pixels) and the like are described. The time code, the number of pictures constituting the GOP, and the like are described in the header of the GOP layer.

The macro blocks included in the slice layer are:
It is a set of a plurality of DCT blocks, and the encoded sequence of the DCT block is a variable of a sequence of quantized DCT coefficients, with the number of consecutive 0 coefficients (run) and a non-zero sequence (level) immediately after it as one unit. It is a long code. The macroblock and the DCT block in the macroblock are not added with the identification codes arranged in byte units.
That is, they are not one variable-length code sequence.

The macro block is composed of one screen (picture).
It is divided into a grid of 6 pixels × 16 lines. A slice is formed by connecting these macroblocks in the horizontal direction, for example. The last macroblock of the previous slice of a continuous slice and the first macroblock of the next slice are continuous, and it is not allowed to form a macroblock overlap between slices. When the size of the screen is determined, the number of macroblocks per screen is uniquely determined.

On the other hand, in order to avoid signal deterioration due to decoding and encoding, it is desirable to edit the encoded data. At this time, the P picture and the B picture require a temporally preceding picture or a preceding and succeeding picture for decoding. Therefore, the editing unit cannot be set to one frame unit. In consideration of this point, in this embodiment, one GOP is made up of one I picture.

For example, a recording area in which recording data for one frame is recorded is a predetermined area. MPEG2
Since the variable length coding is used, the amount of generated data for one frame is controlled so that data generated during one frame period can be recorded in a predetermined recording area. Further, in this embodiment, one slice is composed of one macroblock so as to be suitable for recording on a magnetic tape, and one macroblock is applied to a fixed frame having a predetermined length.

FIG. 1 shows an example of the configuration of the recording side of the recording / reproducing apparatus according to this embodiment. At the time of recording, a predetermined interface, for example, SDI (Serial Data Interface)
The digital video signal is input from the terminal 101 via the receiving unit of the above. SDI is an interface defined by SMPTE for transmitting (4: 2: 2) component video signals, digital audio signals, and additional data. An input video signal is converted by a video encoder 102 into a DCT (Discrete Cosine Transform).
form), is converted into coefficient data, and the coefficient data is subjected to variable length coding. The variable length coded (VLC) data from the video encoder 102 is an elementary stream compliant with MPEG2. This output is supplied to one input terminal of the selector 103.

On the other hand, through the input terminal 104, the ANSI
SDTI (Serial Data Transport Inter), which is an interface defined by / SMPTE 305M
face) format data is input. This signal is synchronously detected by SDTI receiving section 105. And
Once stored in the buffer, the elementary stream is extracted. The extracted elementary stream is supplied to the other input terminal of the selector 103.

The elementary stream selected and output by the selector 103 is supplied to a stream converter 106. In the stream converter 106, the MPE
The DCT coefficients arranged for each DCT block based on the G2 rule are replaced with a plurality of DCTs constituting one macroblock.
Through the T block, frequency components are grouped, and the grouped frequency components are rearranged. The rearranged converted elementary stream is stored in the packing and shuffling unit 1.
07.

Since the video data of the elementary stream is variable-length coded, the data length of each macroblock is not uniform. In the packing and shuffling unit 107, macro blocks are packed in a fixed frame. At this time, the portion that protrudes from the fixed frame is sequentially packed into a surplus portion with respect to the size of the fixed frame. Also, system data such as time code is input to the input terminal 108.
Is supplied to the packing and shuffling unit 107, and the system data is subjected to a recording process similarly to the picture data. Also, shuffling is performed in which the macroblocks of one frame generated in the scanning order are rearranged and the recording positions of the macroblocks on the tape are dispersed. Shuffling can improve the image update rate even when data is reproduced in pieces during variable speed reproduction.

Video data and system data from the packing and shuffling unit 107 (hereinafter, also referred to as video data even when system data is included unless otherwise required) are supplied to the outer code encoder 109. A product code is used as an error correction code for video data and audio data. The product code encodes an outer code in a vertical direction of a two-dimensional array of video data or audio data, encodes an inner code in a horizontal direction thereof, and encodes data symbols doubly. As the outer code and the inner code, a Reed-Solomon code can be used.

The output of the outer code encoder 109 is supplied to the shuffling unit 110 and a plurality of ECCs (Error Correction
ig Code) blocks are shuffled to change the order in sync block units. The shuffling in sync block units prevents errors from concentrating on a specific ECC block. Shuffling part 1
Shuffling performed at 10 may be referred to as interleaving. The output of the shuffling unit 110 is
1 and mixed with audio data. In addition,
The mixing unit 111 includes a main memory, as described later.

Audio data is supplied from an input terminal denoted by reference numeral 112. In this embodiment, an uncompressed digital audio signal is handled. The digital audio signal is supplied to an input SDI receiver (not shown)
These are separated by the DTI receiving unit 105 or input through an audio interface. The input digital audio signal is supplied to A
It is supplied to the UX adding unit 114. The delay unit 113 is for time alignment of the audio signal and the video signal.
The audio AUX supplied from the input terminal 115 is auxiliary data, and is data having information related to audio data such as the sampling frequency of audio data. The audio AUX is added to the audio data by the AUX adding unit 114, and is treated the same as the audio data.

The audio data and AUX from the AUX adding unit 114 (hereinafter, AUX except when necessary)
Is also simply referred to as audio data. ) Is supplied to the outer code encoder 116. Outer code encoder 11
No. 6 encodes an outer code for audio data. The output of the outer code encoder 116 is the shuffling unit 1
17 and undergoes a shuffling process. As audio shuffling, shuffling in sync block units and shuffling in channel units are performed.

The output of the shuffling unit 117 is
1 and the video data and the audio data are converted into data of one channel. The output of the mixing unit 111 is ID
The adding unit 118 is supplied, and the ID adding unit 118 adds an ID including information indicating a sync block number. The output of the ID addition unit 118 is the inner code encoder 119
, And the inner code is encoded. Further, the output of the inner code encoder 119 is supplied to the synchronization adding section 120, and a synchronization signal for each sync block is added. By adding the synchronization signal, recording data in which the sync blocks are continuous is configured. This recording data is supplied to the rotary head 122 via the recording amplifier 121, and is recorded on the magnetic tape 123. In practice, the rotary head 122 is configured such that a plurality of magnetic heads having different azimuths of heads forming adjacent tracks are attached to the rotary drum.

The recording data may be scrambled as required. Further, digital modulation may be performed at the time of recording, and a partial response class 4 and Viterbi code may be used.

FIG. 2 shows an example of the configuration on the reproducing side according to an embodiment of the present invention. Rotating head 1 from magnetic tape 123
The reproduction signal reproduced at 22 is supplied to the synchronization detection unit 132 via the reproduction amplifier 131. Equalization and waveform shaping are performed on the reproduced signal. Further, demodulation of digital modulation, Viterbi decoding, and the like are performed as necessary. The synchronization detection unit 132 detects a synchronization signal added to the head of the sync block. The sync block is cut out by the synchronization detection.

The output of the synchronization detection block 132 is supplied to the inner code decoder 133, where the error of the inner code is corrected. The output of the inner code decoder 133 is supplied to the ID interpolation unit 134, and the ID of the sync block in which the error occurred due to the inner code, for example, the sync block number is interpolated. The output of the ID interpolation unit 134 is supplied to the separation unit 135, where the video data and the audio data are separated. As described above, the video data means DCT coefficient data and system data generated by MPEG intra coding,
Audio data is PCM (Pulse Code Modulation)
Means data and AUX.

The video data from the separation unit 135 is subjected to the reverse processing of shuffling in the deshuffling unit 136. The deshuffling unit 136 performs a process of restoring the shuffling in sync block units performed by the shuffling unit 110 on the recording side. Deshuffling part 136
Is supplied to the outer code decoder 137, and error correction by the outer code is performed. When an error that cannot be corrected occurs, an error flag indicating the presence or absence of the error is set to indicate the presence of the error.

The output of the outer code decoder 137 is supplied to a deshuffling and depacking unit 138. The deshuffling and depacking unit 138 performs processing for restoring shuffling in macroblock units performed by the packing and shuffling unit 107 on the recording side. In the deshuffling and depacking unit 138,
Disassemble the packing applied during recording. That is, the length of the data is returned in units of macroblocks, and the original variable length code is restored. Further, in the deshuffling and depacking unit 138, the system data is separated,
It is taken out to the output terminal 139.

Deshuffling and depacking section 13
The output of No. 8 is supplied to the interpolation unit 140, and the data for which the error flag is set (that is, there is an error) is corrected. That is, if it is determined that there is an error in the macroblock data before the conversion, the DCT coefficients of the frequency components after the error location cannot be restored. Therefore, for example, the data at the error location is replaced with a block end code (EOB), and the DCT coefficients of the subsequent frequency components are set to zero. Similarly, at the time of high-speed reproduction, only DCT coefficients up to the length corresponding to the sync block length are restored, and the coefficients thereafter are replaced with zero data. Further, the interpolation unit 1
In 40, when the header added to the head of the video data is an error, the header (sequence header, GOP
Header, picture header, user data, etc.) are also recovered.

Since the DCT coefficients are arranged from the DC component and the low-frequency component to the high-frequency component across the DCT block, even if the DCT coefficients are ignored from a certain point onward, the macro block , DCT coefficients from DC and low-frequency components can be distributed evenly to each of the DCT blocks constituting.

The output of the interpolation section 140 is supplied to the stream converter 141. In the stream converter 141, the reverse process to that of the stream converter 106 on the recording side is performed. That is, the DCT coefficients arranged for each frequency component across the DCT blocks are rearranged for each DCT block. Thereby, the reproduced signal is converted into an elementary stream conforming to MPEG2.

As for the input / output of the stream converter 141, a sufficient transfer rate (bandwidth) is ensured in accordance with the maximum length of the macroblock as in the recording side. When the length of the macroblock is not limited, it is preferable to secure a bandwidth three times the pixel rate.

The output of the stream converter 141 is supplied to the video decoder 142. Video decoder 142
Decodes the elementary stream and outputs video data. That is, the video decoder 142 performs an inverse quantization process and an inverse DCT process. The decoded video data is taken out to the output terminal 143. For the interface with the outside, for example, SDI is used. In addition, the elementary stream from the stream converter 141 is supplied to the SDTI transmitting unit 144. Although illustration of the path is omitted, the SDTI transmission unit 144 is also supplied with system data, reproduced audio data, and AUX, and
It is converted into a stream having a data structure of the TI format. The stream from the SDTI transmission unit 144 is output to the outside through the output terminal 145.

The audio data separated by the separation unit 135 is supplied to the deshuffling unit 151. The deshuffling unit 151 performs a process opposite to the shuffling performed by the shuffling unit 117 on the recording side. The output of the deshuffling unit 117 is supplied to the outer code decoder 152, and error correction by the outer code is performed. Outer code decoder 152
Output the error-corrected audio data. An error flag is set for data having an uncorrectable error.

The output of the outer code decoder 152 is supplied to an AUX separation section 153, where the audio AUX is separated.
The separated audio AUX is taken out to the output terminal 154. The audio data is supplied to the interpolation unit 155. The interpolating unit 155 interpolates a sample having an error. As the interpolation method, it is possible to use an average value interpolation for interpolating with the average value of correct data before and after in time, a previous value hold for holding a previous correct sample value, and the like. The output of the interpolation unit 155 is supplied to the output unit 156. The output unit 156 performs a mute process for inhibiting the output of an audio signal that is in error and cannot be interpolated, and performs a delay amount adjustment process for time alignment with a video signal. The reproduced audio signal is extracted from the output unit 156 to the output terminal 157.

Although not shown in FIGS. 1 and 2, a timing generator for generating a timing signal synchronized with input data, a system controller (microcomputer) for controlling the entire operation of the recording / reproducing apparatus, and the like are provided. Have been.

In this embodiment, recording of a signal on a magnetic tape is performed by a helical scan method in which an oblique track is formed by a magnetic head provided on a rotating rotary head. A plurality of magnetic heads are provided on the rotating drum at positions facing each other. That is, when the magnetic tape is wound around the rotary head at a winding angle of about 180 °, a plurality of tracks can be simultaneously formed by rotating the rotary head by 180 °. The magnetic heads are formed as a set of two magnetic heads having different azimuths. The plurality of magnetic heads are arranged such that azimuths of adjacent tracks are different from each other.

FIG. 3 shows an example of a track format formed on a magnetic tape by the rotary head described above. This is an example in which video and audio data per frame are recorded on eight tracks. For example, the frame frequency is 29.97 Hz, and the rate is 50 Mbp
s, the number of effective lines is 480, and the number of effective horizontal pixels is 720
A pixel interlace signal (480i signal) and an audio signal are recorded. When the frame frequency is 25H
z, the rate is 50 Mbps, the number of effective lines is 576, and the number of effective horizontal pixels is 720.
6i signal) and audio signal can also be recorded in the same tape format as in FIG.

One segment is composed of two tracks having different azimuths. That is, eight tracks are composed of four segments. Track number corresponding to azimuth for a set of tracks constituting a segment

[0] and a track number [1] are assigned. In the example shown in FIG. 3, track numbers are exchanged between the first eight tracks and the second eight tracks, and different track sequences are assigned to each frame. Thus, even if one of the set of magnetic heads having different azimuths becomes unreadable due to clogging or the like, the influence of an error can be reduced by using the data of the previous frame.

In each of the tracks, a video sector in which video data is recorded is arranged on both ends, and an audio sector in which audio data is recorded is interposed between the video sectors. 3 and FIG. 4, which will be described later, show the arrangement of audio sectors on the tape.

In the track format shown in FIG. 3, eight channels of audio data can be handled. A1 to A8 indicate sectors of channels 1 to 8 of the audio data, respectively. The audio data is recorded with its arrangement changed in segment units. For audio data, audio samples generated in one field period (for example, when the field frequency is 29.97 Hz and the sampling frequency is 48 kHz, 800 or 801 samples) are divided into even-numbered samples and odd-numbered samples. Each sample group and AUX form one ECC block of a product code.

In FIG. 3, since data for one field is recorded on four tracks, two ECC blocks per channel of audio data are recorded on four tracks. The data of two ECC blocks (including the outer code parity) is divided into four sectors, and as shown in FIG. 3, the data is dispersedly recorded on four tracks. Two ECCs
A plurality of sync blocks included in the block are shuffled. For example, two ECC blocks of channel 1 are constituted by four sectors to which reference numbers A1 are assigned.

In this example, video data of 4 ECC blocks is shuffled (interleaved) with respect to one track, divided into upper sectors and lower sides, and recorded. In the lower sector video sector, a system area is provided at a predetermined position.

In FIG. 3, SAT1 (Tr) and SAT2 (Tm) are areas where servo lock signals are recorded. In addition, a gap of a predetermined size (Vg1, Sg1, Ag, Sg) is provided between the recording areas.
2, Sg3 and Vg2).

FIG. 3 shows an example in which data per frame is recorded on eight tracks. Depending on the format of data to be recorded / reproduced, data per frame is recorded in four tracks.
Recording can be performed on tracks, six tracks, and the like.
FIG. 4A shows a format in which one frame has six tracks. In this example, the track sequence is

Only [0] is set.

As shown in FIG. 4B, the data recorded on the tape is composed of a plurality of equally-spaced blocks called sync blocks. FIG. 4C schematically shows a configuration of the sync block. As will be described later in detail, the sync block is composed of a SYNC pattern for detecting synchronization, an ID for identifying each sync block, a DID indicating the content of subsequent data, a data packet, and an inner code parity for error correction. Is done. Data is,
It is treated as a packet in sync block units. That is, the smallest data unit to be recorded or reproduced is one sync block. A number of sync blocks are arranged (FIG. 4B) to form, for example, a video sector (FIG. 4A).

FIG. 5 more specifically shows the data structure of a sync block of video data, which is the minimum unit of recording / reproduction. In this embodiment, one or two macroblocks of data (VLC data) are stored for one sync block according to the format of video data to be recorded, and the size of one sync block is reduced. The length is changed according to the format of the video signal to be handled. As shown in FIG. 5A, one sync block is
From the beginning, a 2-byte SYNC pattern, a 2-byte I
D, a 1-byte DID, for example, a data area variably defined between 112 bytes and 206 bytes, and a 12-byte parity (inner code parity). Note that the data area is also called a payload.

The first two-byte SYNC pattern is for synchronization detection and has a predetermined bit pattern. Synchronization detection is performed by detecting a SYNC pattern that matches the unique pattern.

FIG. 6A shows an example of the bit assignment of ID0 and ID1. The ID has important information inherent to the sync block, and each ID has 2 bytes (ID
0 and ID1). ID0 is 1
The identification information (SYNC ID) for identifying each of the sync blocks in the track is stored. SYNC
The ID is, for example, a serial number assigned to a sync block in each sector. The SYNC ID is represented by 8 bits. SYNC IDs are separately assigned to video sync blocks and audio sync blocks.

ID1 stores information on the track of the sync block. When the MSB side is bit 7 and the LSB side is bit 0, with respect to this sync block,
Bit 7 indicates whether the track is above (upper) or below (Lo)
wer), and bits 5 to 2 indicate the segment of the track. Bit 1 indicates the track number corresponding to the azimuth of the track.
Are bits for distinguishing video data and audio data by this sync block.

FIG. 6B shows an example of bit assignment of DID in the case of video. The DID stores information related to the payload. The content of DID differs between video and audio based on the value of bit 0 of ID1 described above. Bits 7 to 4 are undefined (Reserve
d). Bits 3 and 2 are the mode of the payload, for example, indicating the type of the payload.
Bits 3 and 2 are auxiliary. Bit 1 indicates that one or two macroblocks are stored in the payload. Bit 0 indicates whether the video data stored in the payload is an outer code parity.

FIG. 6C shows an example of bit assignment of DID in the case of audio. Bits 7-4 are R
Eserved. Bit 3 indicates whether the data stored in the payload is audio data or general data. If compression-encoded audio data is stored in the payload, bit 3 is a value indicating the data.
Bit 2 to bit 0 store information of a 5-field sequence in the NTSC system. That is, NT
In the SC system, the sampling frequency of an audio signal for one field of a video signal is 48 kHz.
Is either 800 samples or 801 samples, and this sequence is aligned every five fields. Bit 2 to bit 0 indicate where in the sequence it is located.

Referring back to FIG. 5, FIGS. 5B to 5E
Shows an example of the above-mentioned payload. 5B and 5C
Shows an example in which video data (variable-length coded data) of 1 and 2 macroblocks is stored for the payload, respectively. In the example shown in FIG. 5B in which one macroblock is stored, length information LT indicating the length of the following macroblock is arranged in the first three bytes.
The length information LT may or may not include its own length. 5C shown in FIG.
In an example in which a macroblock is stored, the length information LT of the first macroblock is arranged at the head, and the first macroblock is arranged subsequently. Then, length information L indicating the length of the second macroblock following the first macroblock
T is arranged, followed by a second macroblock.
The length information LT is information necessary for depacking.

FIG. 5D shows video A for the payload.
An example in which UX (auxiliary) data is stored will be described. The head length information LT describes the length of the video AUX data. Subsequent to the length information LT, 5-byte system information, 12-byte PICT information, and 92-byte user information are stored. The remaining portion of the payload length is reserved.

FIG. 5E shows an example in which audio data is stored in the payload. Audio data can be packed over the entire length of the payload. The audio signal is not subjected to compression processing or the like, and is handled in, for example, a PCM format. The present invention is not limited to this, and audio data compressed and encoded by a predetermined method can be handled.

In this embodiment, the length of the payload, which is the storage area of the data of each sync block, is not optimally set for the video sync block and the audio sync block because they are optimally set. . In addition, the length of a sync block for recording video data and the length of a sync block for recording audio data are set to optimal lengths according to the signal format. Thereby, a plurality of different signal formats can be handled uniformly.

FIG. 7A shows the order of DCT coefficients in video data output from the DCT circuit of the MPEG encoder. Starting from the DC component at the upper left in the DCT block, in the direction where the horizontal and vertical spatial frequencies increase,
DCT coefficients are output by zigzag scan. As a result, as shown in an example in FIG. 7B, a total of 64 (8
DCT coefficients of (pixel × 8 lines) are obtained by being arranged in the order of frequency components.

This DCT coefficient is equal to the V of the MPEG encoder.
Variable length coding is performed by the LC unit. That is, the first coefficient is fixed as a DC component, and the next component (AC
From the component), codes are assigned corresponding to the run of zero and the subsequent level. Therefore, the variable-length coded output for the coefficient data of the AC component is converted from the low (low-order) coefficient of the frequency component to the high (high-order) coefficient of AC ₁ ,
AC ₂ , AC ₃ ,... The elementary stream includes DCT coefficients subjected to variable length coding.

In the stream converter 106, the DCT coefficients of the supplied signal are rearranged. That is, in each macroblock, DCT coefficients arranged in order of frequency components for each DCT block by zigzag scan are rearranged in order of frequency components over each DCT block constituting the macroblock.

FIG. 8 shows the stream converter 106.
2 schematically shows the rearrangement of the DCT coefficients in. (4:
2: 2) In the case of a component signal, one macroblock is composed of four DCT blocks (Y ₁ ,
Y _2, and Y ₃ and Y _4), chroma signal Cb, DCT blocks (Cb ₁ of every two according to each of Cr, C
b ₂ , Cr ₁ and Cr ₂ ).

As described above, the video encoder 102
Then, a zigzag scan is performed in accordance with the rules of MPEG2, and as shown in FIG. 8A, for each DCT block,
DCT coefficient is changed from DC component and low frequency component to high frequency component,
The frequency components are arranged in order. When scanning of one DCT block is completed, scanning of the next DCT block is performed, and similarly, DCT coefficients are arranged.

That is, in the macro block, DCT blocks Y ₁ , Y ₂ , Y ₃ and Y ₄ , DCT block C
For each of b ₁ , Cb ₂ , Cr ₁ and Cr ₂ , the DCT coefficients are arranged in order of frequency from the DC component and the low-frequency component to the high-frequency component. Then, [DC, AC ₁ , AC
_2, AC _3, and..], So that codes are assigned, it is variable length coded.

The stream converter 106 decodes the variable-length coded and arranged DCT coefficients once by decoding the variable-length code to detect a break of each coefficient, and extends the frequency over each DCT block constituting the macro block. Summarize by component. This is shown in FIG. 8B. First, the DC components of the eight DCT blocks in the macroblock are summarized, the AC coefficient components of the eight DCT blocks having the lowest frequency components are summarized, and the AC coefficients of the same order are grouped in order. The coefficient data is rearranged across the DCT blocks.

The rearranged coefficient data is DC
(Y ₁ ), DC (Y ₂ ), DC (Y ₃ ), DC
(Y ₄ ), DC (Cb ₁ ), DC (Cb ₂ ), DC (C
r ₁ ), DC (Cr ₂ ), AC ₁ (Y ₁ ), AC ₁ (Y
₂ ), AC ₁ (Y ₃ ), AC ₁ (Y ₄ ), AC ₁ (Cb
₁ ), AC ₁ (Cb ₂ ), AC ₁ (Cr ₁ ), AC
₁ (Cr ₂ ),. Where DC, AC ₁ ,
AC ₂ ,... Are, as described with reference to FIG. 7, each of the variable-length codes assigned to the set consisting of the run and the subsequent level.

The converted elementary stream in which the order of the coefficient data is rearranged by the stream converter 106 is supplied to the packing and shuffling unit 107. The data length of the macroblock is the same for the converted elementary stream and the elementary stream before conversion. In the video encoder 102, even if the length is fixed in GOP (one frame) units by bit rate control, the length varies in macroblock units. The packing and shuffling unit 107 applies the data of the macroblock to the fixed frame.

FIG. 9 schematically shows the processing of packing macroblocks in packing and shuffling section 107. The macro block is applied to a fixed frame having a predetermined data length and is packed. The data length of the fixed frame used at this time is matched with the sync block length, which is the minimum unit of data during recording and reproduction. This is to simplify the processing of shuffling and error correction coding. In FIG. 9, for simplicity, it is assumed that one frame includes eight macroblocks.

As shown in an example in FIG. 9A, the lengths of eight macroblocks are different from each other due to the variable length coding. In this example, as compared with the length of one sync block, which is a fixed frame, the data of macro block # 1, the data of # 3 and the data of # 6 are each longer, and the data of macro block # 2, the data of # 5, # 7 data and # 8
The data of each is short. The data of the macro block # 4 has a length substantially equal to one sync block.

By the packing process, macro blocks are packed into a fixed-length frame having a length of one sync block. Data can be packed without excess or shortage because the amount of data generated in one frame period is controlled to a fixed amount. As shown in an example in FIG. 9B, a macroblock longer than one sync block is divided at a position corresponding to the sync block length. Of the divided macroblocks, the part (overflow part) that protrudes from the sync block length is placed in an area that is vacant in order from the top,
That is, it is packed after a macroblock whose length is less than the sync block length.

In the example of FIG. 9B, the macro block # 1
The portion that exceeds the sync block length is first packed after the macro block # 2, and when it reaches the length of the sync block, it is packed after the macro block # 5. Next, the portion of the macro block # 3 that is outside the sync block length is packed behind the macro block # 7. Further, the part of the macro block # 6 that protrudes from the sync block length is packed after the macro block # 7, and the part that protrudes further is packed after the macro block # 8. Thus, each macroblock is packed in a fixed frame of the sync block length.

The length of each macroblock can be checked in advance by the stream converter 106.
As a result, the packing unit 107 can know the end of the data of the macro block without decoding the VLC data and checking the contents.

FIG. 10 shows an example of an error correction code used in one embodiment. FIG. 10A shows one ECC block of an error correction code for video data.
B is 1E of an error correction code for audio data.
Indicates a CC block. In FIG. 10A, VLC data is data from the packing and shuffling unit 107. A SYNC pattern, ID, and DID are added to each row of the VLC data, and a parity of an inner code is added to form one SYNC block.

That is, a 10-byte outer code parity is generated from a predetermined number of symbols (bytes) aligned in the vertical direction of the array of VLC data, and the ID, DID and VLC data (or external data) aligned in the horizontal direction are generated. Parity of the inner code is generated from a predetermined number of symbols (bytes) of the code parity. In the example of FIG. 10A, 10 outer code parity symbols and 12 inner code parity symbols are added. As a specific error correction code, a Reed-Solomon code is used. FIG.
At 0A, the lengths of VLC data in one SYNC block are different at 59.94 Hz, 25 Hz, 23.
This is because the frame frequency of video data is different, such as 976 Hz.

As shown in FIG. 10B, the product code for audio data is the same as that for video data.
The parity of the 10-symbol outer code and the parity of the 12-symbol inner code are generated. In the case of audio data, the sampling frequency is, for example, 48 kHz.
And one sample is quantized to 16 bits. One sample may be converted into another bit number, for example, 24 bits. According to the difference in the frame frequency described above, 1SYN
The amount of audio data in the C block is different.
As described above, one field of audio data /
One channel forms two ECC blocks.
One ECC block includes one of even-numbered and odd-numbered audio samples and audio AUX as data.

Next, the ID interpolation section 134 on the reproducing side of the recording / reproducing apparatus shown in FIG. 2 will be described in more detail. The ID interpolation unit 134 interpolates ID numbers (ID0) and ID information (ID1) for two types of sync blocks having different lengths L and K (2K>L> K). In the following, in order to avoid complexity, the ID number and the ID information are collectively referred to as an ID.

FIG. 11 shows an example in which interpolation is performed by the ID interpolation unit 134. In this embodiment, the ID interpolation unit 13
4 is the ID of the sync block input earlier in time
Is interpolated using the ID of the sync block input later. At this time, as shown in FIGS. 11A and 11B, interpolation is performed on a sync block input one or two before the sync block having no error in the ID.

As in the example shown in FIG. 11C, no interpolation is performed for a sync block that is three or more previous blocks. In this case, for example, the ID is interpolated by an inertia circuit that mechanically generates the ID based on the previously detected ID.

FIG. 12 shows an ID interpolation unit 13 according to the present invention.
FIG. 4 is a functional block diagram of FIG. The sync block whose inner code has been corrected by the inner code decoder 133 is supplied to the terminal 50. The sync block supplied to the terminal 50 is supplied to the delay line 51 having a length of (2L + α) and to the ID information holding unit 60. Note that the length α added to the length 2L in the delay line 51 is a small value with respect to L. For example, α is
This is a length that can further store an ID for the length 2L.

In the ID information holding section 60, the ID of the supplied sync block is extracted. This ID is supplied to both the acquired information management unit 62 and the interpolation ID generation unit 61. This ID is supplied to the control unit 63 as a data input start signal.

The acquired information management unit 62 counts the pulses supplied together with the input data, and
The number of unprocessed input data that has not been processed among the sync blocks stored in 1 is obtained.
In the control unit 63, based on the unprocessed input data number information and the data input start signal, an interpolation ID
A plurality of predetermined selections I from a plurality of holding IDs held in
A holding ID selection signal for selecting D is output, and an interpolation ID selection signal for selecting an interpolation ID actually used for interpolation from the interpolation ID generated from the selection ID is output. Further, the control unit 63 outputs an ID interpolation timing instruction signal for controlling the timing of superimposing the interpolation ID and the sync block.

On the other hand, in the interpolation ID generation section 61, a plurality of IDs are selected from the plurality of supplied holding IDs based on the holding ID selection signal, and a plurality of interpolation IDs are generated. The selected plurality of interpolation IDs are supplied to the interpolation ID selection unit 64, and an interpolation ID actually used for interpolation is selected based on the interpolation ID selection signal supplied from the control unit 63. The selected interpolation ID is supplied to one input terminal of the adder 52.

A sync block delayed by (2L + α) by the delay line 51 is supplied to the other input terminal of the adder 52. In accordance with the instruction of the ID interpolation timing instruction signal from the control unit 63, the adder 52 superimposes the interpolation ID on the sync block, and outputs the ID of the sync block.
Is interpolated. The output of the adder 52 is output to an output terminal 53 as output data.

FIGS. 13 to 16 show each part of the configuration of FIG. 12 in more detail. FIG. 13 shows the configuration of the ID information acquisition unit 60. The input data input from the input terminal 50 is
It is supplied to the ID information extraction circuit 20. The ID information extraction circuit 20 generates a data input start signal 31 based on the input data input timing and extracts an ID from the input data. The ID information holding circuit 22 is a register for holding an ID, for example, and stores IDs for a plurality of blocks.
21 is held. I held by the ID information holding circuit 22
A plurality of D21 are output as the holding IDs 23.

Note that the ID information extraction circuit 20 uses ID0
As shown in FIG. 17, extraction of ID1 and ID1 is performed using a sync pulse as a trigger. The sync pulse is
This signal is output as a result of the sync pattern detection by the SYNC detection circuit 132, and indicates the head of the sync block. The ID that arrives after a predetermined timing from the sync pulse is extracted.

FIG. 14 shows the structure of the control unit 63. The control unit 63 includes an ID information selection circuit 34 and an ID interpolation timing generation circuit 37. The ID interpolation timing generation circuit 37 includes, for example, a delay circuit having a predetermined delay,
An ID interpolation timing instruction signal 38 is generated from the input data input start signal 31. On the other hand, in the ID information selection circuit 34, the unprocessed input data number information 32 supplied from the acquisition information management unit 62, which will be described later, and the error information included in the ID supplied as the data input start signal (error due to inner code correction). ), A retained ID selection signal 35 and an interpolation ID selection signal 36 are generated.

For example, based on the number of unprocessed input data, a retained ID selection signal 35 for selecting which of a plurality of generated interpolation IDs to use is generated. Further, from the interpolation ID selection signal 36, an interpolation ID to be used for actual interpolation is selected from an interpolation ID generated by an interpolation ID generation circuit 26 described later based on a plurality of holding IDs selected by the holding ID selection signal 35. For this purpose, an interpolation ID selection signal 36 is generated.

FIG. 15 shows the configuration of the interpolation ID generation unit 61. The interpolation ID generation unit 61 includes the selector 24 controlled by the held ID selection signal 35 and the interpolation ID generation circuit 26. The plurality of held IDs 23 output from the ID information acquisition unit 60 are supplied to the selector 24. For example, three of the plurality of holding IDs 23 are selected by the selector 24 as the selection ID 25 based on the holding ID selection signal 35 and supplied to the interpolation ID generation circuit 26. Selection ID
25 is the I of each block in the delay line 51.
Three IDs that correspond to D are selected.
The interpolation ID generation circuit 26 generates three interpolation IDs 27 from the supplied selection ID 25.

FIG. 16 shows the configuration of the acquired information management unit 62. The acquisition information management unit 62 includes the number management counter 30 that counts the number of unprocessed blocks among the sync blocks stored in the delay line 51. The counter value is incremented based on the data input start signal 31. The counter is decremented by the ID interpolation timing instruction signal. The count value is output as the unprocessed input data number 32.

FIG. 18 is a block diagram showing the configuration of I
4 shows a configuration of a D interpolation unit 134. FIG. 18 is similar to FIG.
2 corresponds to the functional block diagram of FIG. In FIG. 18, a plurality of interpolation IDs 27 generated by the interpolation ID generation circuit 26 are supplied to an interpolation ID selection unit 64. Then, the interpolation ID selection signal 36 from the ID information selection circuit 34
Is used to select an ID used for interpolation. This interpolation I
D29 is supplied to the adder 52, and is superimposed on a sync block for which ID is to be interpolated, output from the delay line 51, based on the ID interpolation timing instruction signal 38.

Next, the ID interpolation unit 13 based on the above configuration
Operation 4 will be described in further detail. FIG. 19 is a diagram illustrating an example in which a sync block having a length of L is input to the circuit. In the delay line 51 shown in FIG. 19A, the right side is data input earlier in time.

In this embodiment, a sync block (block A in FIG. 19A) for which ID interpolation processing is to be performed.
The ID included in a sync block (block C in the figure) input after a maximum of two blocks
Interpolation is possible based on That is, based on the ID of block C, an interpolation ID for block A is generated,
The interpolation ID is superimposed on the block A.

Therefore, it is necessary not to interpolate each information of the block A until the ID and the error information of the block C are obtained. For that purpose, a delay line of at least 2L is required. On the other hand, if the delay line is set for only 2L, the block A starts to be output from the delay line before the error information of the block C is obtained, and the interpolation processing of the block A is performed. Therefore, an appropriate length α until the ID and error information of the block C are obtained.
Add a minute delay line. For this reason, the delay line needs a length of (2L + α).

At the time of the state shown in FIG. 19A, the ID of the sync block C and the error information are
0 has already been acquired and is held in the ID information holding circuit 22. As shown in FIG. 19B, the ID information holding circuit 22 is configured by serially connecting four delay lines 70 to 73 having a length L. Outputs R, S, T and U of the four delay lines 70 to 73 are supplied to the selector 24.

On the other hand, the sync block A has not yet come out of the delay line 51, and is in a state where interpolation processing has not been performed. Note that the sync block Z indicates a block for which interpolation has already been completed. Also, the sync block C is
Although the whole is not stored in the delay line 51, the head ID portion is stored, and the delay line 51 has IDs for three sync blocks.

Therefore, in this state, the count value of the number management counter 30 becomes [3]. When the count value is [3], the ID held in the ID information holding circuit 22 is changed so that the IDs of the sync blocks A, B, and C stored in the delay line 51 correspond to each other. select. The selection is made by the ID information selection circuit 34
The selector 24 is controlled by the holding ID selection signal 35 from the CPU. In the example of FIG. 19B, data R, S, and T are selected.

The interpolation ID generation circuit 26 reversely generates interpolation IDs (data R ', S' and T ') based on the three selected IDs. As a result, for example, three IDs having consecutive values of the ID number (ID0) are generated. This reverse generation is performed mechanically even if there is an error in the ID.

The inversely generated interpolation ID is the error information 3
In accordance with the interpolation ID selection signal 36 based on No. 3, the interpolation ID selection unit 64 further narrows down to one interpolation ID. For example, when the sync block A has an error and the sync block B has no error, a correct interpolation ID can be obtained by using the data R ′ corresponding to the sync block B.

When ID interpolation is performed, the count value of the number management counter 30 is decremented. That is,
The count value of the number management counter 30 mainly fluctuates between [3] and [2]. The counting by the number management counter 30 is performed based on the sync pulse regardless of whether the input sync block ID is an error.

Next, referring to FIG. 20, (2K>L> K)
The following describes a case where a sync block of length K is input. When a sync block of length K is input to the ID interpolation unit 134, the state of the delay line 51 is such that a maximum of four sync blocks are stored as shown in FIG. 20A, for example. Sync block A
Is a block that has an error in the ID and for which interpolation is desired.

At this time, the ID of the sync block D is I
Although held in the D information holding circuit 22, the ID of the sync block A has not been interpolated yet. for that reason,
The count value of the number management counter 30 becomes [4]. When the sync block length is K, when the count value is [4], processing for interpolating ID is performed.

Note that the lengths of the sync blocks are L and K.
Is determined based on the ID and DID information. Based on these pieces of information, an instruction may be given by a system controller (not shown).

In this case, as in the case of the sync block having the length L, the first three ID interpolation-unprocessed ID lines stored in the delay line 51 having the length (2L + α) are used. The ID information holding circuit 22 selects three IDs held in the delay lines 70 to 73 so that the IDs correspond to the IDs of the sync blocks. In the example of FIG. 20B, data S, T, and U are selected.
In practice, based on the count value of the number management counter 30, which three of the IDs held in the delay lines 70 to 73 are selected is determined. IDs for interpolation are inversely generated by the selected three IDs (data S ′, T ′ and U ′). The inversely generated data is narrowed down to one based on error information or the like, and used as an interpolation ID.

The number of IDs held in the ID information storage circuit 22 can be obtained as follows: ID number = FIX ((2L + α) / K) +1 (1) FIX represents the integer part of the value in parentheses.

[0120]

As described above, according to the present invention, the number of sync blocks stored in a delay line of a predetermined length is managed, and whether to select an interpolation ID and perform interpolation processing based on this number is determined. Have decided. Therefore, even if inputs of a plurality of block lengths are mixed,
Since the interpolation process can be performed with one configuration, there is an effect that the circuit scale for ID interpolation can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration on a recording side according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a reproducing side according to an embodiment of the present invention.

FIG. 3 is a schematic diagram illustrating an example of a track format.

FIG. 4 is a schematic diagram illustrating another example of a track format.

FIG. 5 is a schematic diagram illustrating a plurality of examples of a configuration of a sync block.

FIG. 6 shows an ID and a DID added to a sync block.
FIG.

FIG. 7 is a schematic diagram for explaining an output method of a video encoder and variable-length encoding.

FIG. 8 is a schematic diagram for explaining rearrangement of an output order of a video encoder.

FIG. 9 is a schematic diagram for explaining a process of packing data rearranged in order into a sync block.

FIG. 10 is a schematic diagram for explaining an error correction code for video data and audio data.

FIG. 11 is a schematic diagram illustrating an example in which interpolation is performed by an ID interpolation circuit.

FIG. 12 is a functional block diagram of an ID interpolation circuit according to the present invention.

FIG. 13 is a block diagram illustrating a configuration of an ID information acquisition unit.

FIG. 14 is a block diagram illustrating a configuration of a control unit.

FIG. 15 is a block diagram illustrating a configuration of an interpolation ID generation unit.

FIG. 16 is a block diagram illustrating a configuration of an acquisition information management unit.

FIG. 17 is a schematic diagram illustrating a sync pulse.

FIG. 18 is a more specific block diagram of an ID interpolation circuit according to the present invention.

FIG. 19 is a schematic diagram illustrating an example in which a sync block having a length of L is input.

FIG. 20 is a schematic diagram illustrating an example in which a sync block having a length of K is input.

FIG. 21 is a schematic diagram schematically showing an example of an arrangement of each sector on a track.

[Explanation of symbols]

20 ... ID information extraction circuit, 22 ... ID information holding circuit, 23 ... holding ID, 24 ... selector, 26
... Interpolation ID generation circuit, 27 ... Interpolation ID, 29
... interpolation ID, 30 ... number management counter, 34
..ID information selection circuit, 37 ... interpolation timing generation circuit, 51 ... delay line, 52 ... adder,
Reference numeral 60: ID information acquisition unit, 61: Interpolation ID generation unit, 62: Acquisition information management unit, 63: Control unit, 6
4 ... Interpolation ID selector, 132 ... SYNC detection circuit, 133 ... Inner code decoder, 134 ... ID interpolation circuit

Claims (7)

[Claims] 1. A data processing apparatus configured to interpolate data block identification information supplied by decoding an error correction code added in units of blocks of a predetermined length to p data blocks. A data unit to which identification information is added at a predetermined position is input after decoding error correction coding performed at the time of recording, and a plurality of the input data blocks are stored; and A plurality of block identification information is held in the identification information holding means, and a plurality of pieces of identification information corresponding to the plurality of data blocks stored in the memory means are selected from the held identification information. Identification information selecting means; counting the number of identification information added to the data block stored in the memory means; Becomes a predetermined value, a plurality of interpolation identifications generated from the plurality of identification information selected by the identification information selecting means based on the error information by the decoding of the sync block stored in the memory. From among the information, interpolation identification information selecting means for selecting interpolation identification information for interpolating the identification information of the sync block corresponding to the error information, and the interpolation identification information output from the memory means,
Means for superimposing on the sync block corresponding to the error information, wherein when the interpolation identification information is selected by the interpolation identification information selecting means, the count value is decremented. Data processing device. 2. The data processing device according to claim 1, wherein if the identification information can be interpolated by going back up to p sync blocks up to a maximum of p, the identification information selecting means may execute the identification processing on the held plurality of blocks. A data processing device which selects (p + 1) pieces of the above-mentioned pieces of identification information from the top in time from among the pieces of identification information. 3. The data processing apparatus according to claim 2, wherein a sync block having a length of L and said L and (2K>L> K)
And at least one of the length K sync blocks having the relationship of (1) is input, and the memory means stores the length L sync blocks such that (p + 1) identification information of the length L sync blocks are stored. A data processing device characterized in that the data can be stored, and the identification information holding means holds [FIX (2L / K) +1] pieces of the identification information. 4. A method for reproducing data recorded on a recording medium after being subjected to error correction coding in units of a predetermined length to which identification information has been added, and identifying the identification information of the data block in which the reproduced data has been decoded by the data block. In the data reproducing apparatus, the data is interpolated retroactively up to p times, and the identification information is added at a predetermined position, and the data which is error-correction coded in units of a predetermined length and recorded on the recording medium is reproduced. Reproduction means for decoding the error correction code; memory means for storing a plurality of data blocks reproduced by the reproduction means; and identification information holding means for storing a plurality of the identification information of the data blocks reproduced by the reproduction means. Among the plurality of data blocks stored in the memory means from among the stored identification information. Identification information selecting means for selecting a plurality of pieces of identification information; counting the number of identification information added to the data block stored in the memory means; when the count value reaches a predetermined value, storing in the memory Based on the error information obtained by the decoding of the sync block being performed, among the plurality of interpolation identification information generated from the plurality of identification information selected by the identification information selecting means, An interpolation identification information selecting unit that selects interpolation identification information for interpolating the identification information of the sync block; and the interpolation identification information output from the memory unit.
Means for superimposing on the sync block corresponding to the error information, wherein when the interpolation identification information is selected by the interpolation identification information selecting means, the count value is decremented. Data playback device. 5. The data processing device according to claim 4, wherein if the identification information can be interpolated by going back up to p sync blocks up to a maximum of p, the identification information selecting means outputs the plurality of stored plurality of blocks. A data processing device which selects (p + 1) pieces of the above-mentioned pieces of identification information from the top in time from among the pieces of identification information. 6. The data processing device according to claim 5, wherein a sync block having a length of L and said L and (2K>L> K)
, And at least one of the sync blocks of length L is input to the memory means so that (p + 1) pieces of identification information of the sync blocks of length L are stored in the memory means. Can be stored, and the identification information holding means holds [FIX (2L / K) +1] pieces of the identification information. 7. A data processing method for interpolating identification information of a data block supplied by decoding an error correction code added in block units of a predetermined length to p data blocks retroactively. A step of storing a plurality of data blocks to which a data block to which identification information is added at a predetermined position is decoded and input by error correction coding performed at the time of recording; A plurality of identification information of the input data block is held in the identification information holding means, and a plurality of identifications corresponding to the plurality of data blocks stored in the memory means are identified from the held identification information. A step of selecting identification information for selecting information; and counting the number of identification information added to the data block stored in the memory means. When the count value reaches a predetermined value, the count value is generated from the plurality of pieces of identification information selected in the identification information selection step based on the error information obtained by decoding the sync block stored in the memory. A step of selecting interpolation identification information for interpolating the identification information of the sync block corresponding to the error information from among the plurality of pieces of interpolation identification information thus obtained; and storing the interpolation identification information in the memory means. Output from
Superimposing on the sync block corresponding to the error information, and when the interpolation identification information is selected by the interpolation identification information selection step means, the count value is decremented. Data processing method.