JP2000148065A - Substrate for electrooptical device, electrooptical device, electronic equipment and projection display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a substrate for an electrooptical device of a digital drive system without making to be apparent a write-in order on a display picture, dissolving non-uniformity in the display picture and obtaining high picture quality. SOLUTION: A digital storage circuit M provided respectively corresponding to each pixel has a first latch circuit F1 fetching the digital data Di inputted to a signal electrode Xi and temporarily storing them, and a second latch circuit L2 reading the advanced data D1 stored in a former frame period 1F in the latch circuit F1 in a reading period R2 preceding a writing period W2 of the back frame period 2F, temporarily storing them and statically driving a pixel electrode 14 based on a storage output Q. The write-in order of the data Di stays in the first latch circuit L1, and doesn't extend to the second latch circuit L2. The non-uniformity in the display picture is dissolved, and the high picture quality is obtained. Since the second latch circuit L2 static drives the pixel electrode 14, perfect digital drive is attained.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electro-optical device substrate such as a reflective liquid crystal panel substrate, and more particularly to an electro-optical device substrate in which pixels are arranged in a matrix.

[0002]

2. Related Art The applicant of the present invention has disclosed, on Japanese Patent Application No. 8-279388 filed on Oct. 22, 1996, the structures of a liquid crystal panel substrate, a liquid crystal panel and a projection display device described below.

[0003] The projection display device using a reflection type liquid crystal panel as a light valve (liquid crystal projector), as shown in FIG. 5, the light source unit 1 arranged along a system optical axis L ₀
10, a polarization illuminating device 100 schematically including an integrator lens 120 and a polarization conversion element 130, and a polarization beam splitter 200 for reflecting an S-polarized light beam emitted from the polarized light illuminating device 100 by an S-polarized light flux reflecting surface 201.
And the S-polarized light flux reflecting surface 20 of the polarizing beam splitter 200
A dichroic mirror 412 for separating the blue light (B) component of the light reflected from 1, a reflective liquid crystal light valve 300B for modulating the separated blue light (B),
A dichroic mirror 413 that reflects and separates a red light (R) component of the light flux after blue light is separated by the dichroic mirror 412, and a reflective liquid crystal light valve 300R that modulates the separated red light (R). When,
A reflective liquid crystal light valve 300G for modulating the remaining green light (G) transmitted through the dichroic mirror 413;
Three reflective liquid crystal light valves 300R, 300G, 3
The light modulated at 00B is reversed in the optical path to make dichroic mirrors 413, 412 and a polarizing beam splitter 200.
And a projection optical system 500 composed of a projection lens for projecting the combined light onto the screen 600. Each reflective liquid crystal light valve 300R, 300G,
As 300B, a reflective liquid crystal panel 30 as shown in the sectional view of FIG. 6 is used.

The reflective liquid crystal panel 30 includes a reflective liquid crystal panel substrate 31 fixed on a support substrate 32 made of glass, ceramic, or the like with an adhesive, and a sealing material 36 on the reflective liquid crystal panel substrate 31. A glass substrate (opposite substrate) 35 on the light incident side having a counter electrode (common electrode) 33 made of a transparent conductive film (ITO) which is surrounded in a frame shape and is disposed opposite to each other at an interval; and a reflective liquid crystal panel substrate 31 A well-known TN (Twisted Nematic) type liquid crystal filled in a gap sealed by a sealing material 36 between the substrate and the glass substrate 35 or a liquid crystal molecule in which liquid crystal molecules are substantially vertically aligned in a state where no voltage is applied.
And an H (Super Homeotropic) type liquid crystal 37.

FIG. 7 shows a main circuit configuration of a reflective liquid crystal panel substrate 31 used in the reflective liquid crystal panel 30, and FIG. 8 shows an enlarged plan layout of the reflective liquid crystal panel substrate 31. Reflective liquid crystal panel substrate 31
Is a rectangular pixel area (display area) 20 in which a large number of pixel electrodes 14 shown in FIG. 6 are arranged in a matrix, and a gate line (scanning electrode, row electrode) located outside the left and right sides of the pixel area 20. A scanning line driving circuit (Y driver) 2 including a shift register and a buffer circuit for scanning Y _{0 to} Y _n.
2 (22R, 22L) and the data line (source line, signal electrode, column electrode) X ₀ located outside the upper side of the pixel region 20.
A precharge and test circuit 23 for to X _m,
The data lines X _{0 to} X 4 are located outside the lower side of the pixel region 20.
_m , an image signal sampling circuit 24 for sampling and supplying an image signal corresponding to the image data, a scanning line driving circuit 22, a precharge and test circuit 23, and the above-described sealing material 3 outside the image signal sampling circuit 24.
7 are arranged along the lower end of the frame-shaped seal region 27 where the positioning is performed, and an anisotropic conductive film (ACF) 38 is arranged.
And a plurality of terminal pads 26 which are fixedly connected to the flexible tape wiring 39 via a line, and which are located between the row of the terminal pads 26 and the sealing region 27 and generate a selection pulse for the image signal sampling circuit 24. Register 2
1 and relay terminal pads (so-called silver dots) 29R and 29L located on both sides of the shift register 21 for supplying power to the counter electrode 33 of the glass substrate 35.

The shift register 21 and the image signal sampling circuit 24 constitute a signal line driving circuit (X driver) 40 for driving the data lines X _{1 to} X _m . The signal line drive circuit 40 employs a sequential drive system point feeds the data signals one by one to the data lines X ₀ to X _m. It is also possible to employ a line-sequential drive system feeds the simultaneously data signal to all the data lines X ₀ to X _m. The pixel region 20 in which the pixels (pixel electrodes 14) are arranged in a matrix shape has a data line X ₀ arranged in a lattice shape.
And to X _m and the gate lines Y ₀ to Y _n, have their intersection point pixels arranged MOSFET for selecting every (insulated gate field effect transistor) T to (T ₀₀ ~T _nm).
The source S of the transistor T of each pixel is connected to the data line X, the gate G is connected to the gate line, and the drain D is connected to the pixel electrode 14 and the storage capacitor C as described later. The pixel electrode 14 of the reflective liquid crystal panel substrate 31 is connected to a liquid crystal cell LC of a liquid crystal 37 filled between the pixel electrode 14 and a glass substrate 35 as an opposite substrate.

The peripheral circuits (scanning line drive circuits 22R and 22L, precharge and test circuit 23, and image signal sampling circuit 2) located inside the seal area 27
4), a light-shielding film 25 (see FIG. 6) in the same layer as the pixel electrode 14 in the uppermost layer is provided in order to prevent light from entering.

FIG. 9 is an enlarged plan view showing a part of the pixel region 20 of the reflective liquid crystal panel substrate 31, and FIG.
FIG. 4 is a cutaway view showing a state cut along AA ′ in FIG. In FIG. 10, reference numeral 1 denotes a single crystal silicon P ⁻ type semiconductor substrate (or an N ⁻ type semiconductor substrate), for example, 20 mm.
It is a large corner. Reference numeral 2 denotes a P-type well region formed on the surface (main surface) side of an element (e.g., MOSFET) forming region of the semiconductor substrate 1; It is an oxide film (so-called LOCOS). The P-type well region 2 shown in FIG. 10 is a pixel region 2 in which a large number of pixels such as 768 × 1024 pixels are arranged in a matrix.
0, and is formed as a pixel region 2
A P-type well region for forming elements constituting peripheral circuits other than 0 (scanning line driving circuits 22R and 22L, precharge and test circuit 23, image signal sampling circuit 24, and signal line driving circuit 21); Are separated.

In the field oxide film 3, two openings are formed in a partitioned area for each pixel. A gate electrode 4a made of polysilicon or metal silicide formed at the center of the inside of one opening via a gate insulating film 4b.
The N ⁺ type source region 5a and the N ⁺ type drain region 5b formed on the surface of the P type well region 2 on both sides of the gate electrode 4a are N channel type MOSFETs for pixel selection.
(Insulated gate field effect transistor) T. Each gate electrode 4a of a plurality of pixels adjacent in the row direction extends as it is in the pixel row direction to form a gate line 4 (Y in FIG. 7).

A common P-type capacitor electrode region 8 formed in the row direction on the surface of the P-type well region 2 inside the other opening, and an insulating film (dielectric film) is formed on the P-type capacitor electrode region 8. )
The capacitor electrode 9a made of polysilicon or metal silicide formed via the capacitor 9b constitutes a storage capacitor C for holding a signal selected by the pixel selection transistor T.

A first interlayer insulating film 6 is formed on gate electrode 4a and capacitor electrode 9a, and a first metal layer mainly composed of aluminum is formed on insulating film 6.

In the first metal layer, a data line 7 (X in FIG. 7) extending in the column direction, a protruding comb-like shape from the data line 7, and a conductive contact with a source region 4b through a contact hole 6a. Source electrode wiring 7a, contact hole 6
b, and a relay wiring 10 that makes conductive contact with the drain region 5b through the contact hole 6b and makes conductive contact with the capacitor electrode 9a through the contact hole 6c.

A second interlayer insulating film 11 is formed on the first metal layer forming the data line 7, the source electrode wiring 7a and the relay wiring 10, and an aluminum film is formed on the second interlayer insulating film 11. Is formed as a second metal layer. The second metal layer includes a light shielding film 12 covering one surface of the pixel region 20. The second metal layer forming the light-shielding film 12 includes peripheral circuits formed around the pixel region 20 (scanning line drive circuits 22R and 22L, precharge and test circuit 23, image signal sampling circuit 24, and It is used as a wiring for connection between elements in the signal line driving circuit 21).

An opening 12a for penetrating the plug is formed at a position of the light shielding film 12 just above the relay wiring 10. A third interlayer insulating film 13 is formed on the light-shielding film 12, and a pixel electrode 14 as a rectangular reflective electrode corresponding to substantially one pixel is formed on the third interlayer insulating film 13. I have. The third and second interlayer insulating films 13 and 11 are positioned so as to be located inside the light-shielding film 12 corresponding to the openings 12a.
Is provided. After a high melting point metal such as tungsten is buried in the contact hole 16 by the CVD method, the high melting point metal layer deposited on the third interlayer insulating film 13 and the third interlayer insulating film 1 are formed.
The surface side of No. 3 is cut by a CMP (Chemical Mechanical Polishing) method and flattened like a mirror surface. Next, for example, an aluminum layer is formed by a low-temperature sputtering method, and a rectangular pixel electrode (reflection electrode) having a side of about 15 to 20 μm is formed by patterning.
14 is formed. Relay wiring 10 and pixel electrode 1 above it
4 are electrically connected to each other by a columnar connection plug (interlayer conductive portion) 15. Then, a passivation film 17 is entirely formed on the pixel electrode 14.

The connection plug 15 is formed by flattening the third interlayer insulating film 13 by a CMP method,
There is also a method in which a contact hole is opened and a high melting point metal such as tungsten is buried therein.

[0016]

The driving method of the reflective liquid crystal panel substrate 31 is as follows. First, the scanning line driving circuit 22 selects the gate line Y ₀ , and in the selection period (horizontal period), the signal line is selected. From the line driving circuit 40 to the data lines X ₀ to
X pixel selection period one by one to the _m (column selection period)
A data signal is sent to each of the pixels on the first column, and a data signal is written to the storage capacitor C and the liquid crystal cell LC connected to the pixel electrode 14 in a dot-sequential manner.

Next, the scanning line driving circuit 22 controls the gate line Y ₁
In the selection period where is selected, in the pixels on the second row, data signals are written to the storage capacitor C and the liquid crystal cell LC connected to the pixel electrode 14 in a dot-sequential manner. In this manner, when the data signal is written to the pixel on the (n + 1) -th row at the end, the writing period for all the pixels (one-frame transfer of the image signal on the signal line driving circuit 40 side) ends, and thereafter , The next one-frame transfer is started.

However, when the next one frame transfer is started, the data signal on the pixel in the first row and the first column is refreshed (rewritten) in the selection period in which the gate line Y ₀ is selected. In the other pixels on one row and the pixels on the second row and below, the signal of the previous frame remains as it is. For this reason, in the writing period, the pixels that switch between the image belonging to the previous frame and the image belonging to the subsequent frame progress dot-sequentially and actually appear as they are on the display screen, resulting in an uneven display screen.

In the case of a display screen having a relatively small number of pixels, the writing period can be shortened, so that the nonuniformity of the display screen as described above does not matter much. However, as the number of pixels increases, the writing time of all pixels increases. As a result, the display period of all pixels is reciprocally shortened, and the non-uniformity of the display screen becomes conspicuous, and the image quality is reduced. Of course, the signal line driving circuit 40 can adopt the line sequential method instead of the dot sequential method, but in such a case, in the writing time of all the pixels, the switching pixel between the image belonging to the previous frame and the image belonging to the subsequent frame is not sufficient. Since the display proceeds in a line-sequential manner and appears on the display screen as it is, the display screen also becomes uneven. When the number of pixels is increased, the image quality is reduced due to unevenness of the display screen.

For this reason, there is a limit in increasing the size of the screen or increasing the definition due to the number of pixels.

In view of the above problems, the first aspect of the present invention
The problem is that even if a dot-sequential or line-sequential writing method is adopted, the writing sequence does not become apparent on the display screen, the unevenness of the display screen can be eliminated, and a substrate for an electro-optical device that can obtain high image quality can be obtained. To provide.

A second object of the present invention is to provide a liquid crystal (L)
C), DMD, FED, PDP, EL, LED
It is an object of the present invention to provide a substrate for an electro-optical device suitable for a digitally driven display device such as the one described above.

[0023]

According to a first aspect of the present invention, there is provided an electro-optical device having a pixel electrode corresponding to a matrix intersection between a scanning electrode and a signal electrode. , LC, DMD, FED,
In a substrate for a digital drive type display device such as PDP, EL, LED, etc., a pixel drive operation based on temporarily stored preceding digital data (for example, data of a previous frame) and arrives at a signal electrode after a predetermined time from the preceding digital data. Digital storage means for simultaneously and concurrently performing a temporary storage operation on delayed digital data of the same pixel (for example, data of a subsequent frame) is provided for each pixel.

In the conventional active element circuit, the timing for temporarily storing data in the storage capacitor and the timing for driving the electro-optical material with pixels using the data coincide with each other. According to this, the timing for temporarily storing the data from the signal electrodes and the timing for reading out the temporarily stored data and driving the pixels are positively shifted until all the pixel data is accumulated. , The data of all the pixels is written and accumulated, and then the simultaneous display (still display) of all the pixels can be realized in the next frame period. Here, the certain period is
In addition to the full frame period, in a color sequential display system (field color sequential system), when one full frame period includes R, G, and B subframe periods in order, the subframe period also corresponds to a certain period. I have.

In the present invention, regardless of the writing sequence such as the dot-sequential system or the line-sequential system, the writing sequence is limited to the temporary storage sequence, and does not appear as the pixel driving sequence.
It is possible to realize frame switching display of all pixels simultaneously and display simultaneousness of all pixels. As a result, unevenness of the display screen can be eliminated, and a high quality electro-optical device substrate can be provided. Therefore, regardless of the number of pixels, it is possible to realize a large screen and high definition of high image quality. Further, the display time and the writing time are not inconsistent within one frame period, and the display time can be made longer for all pixels than before, so that higher image quality can be achieved. Further, the writing operation of all pixels can be realized over a certain period (for example, one frame period), and the writing period can be lengthened. It is possible to simplify the peripheral circuit configuration or increase the number of pixels by reducing the signal transfer speed. In addition, there is no need for a frame memory for display data externally attached to the electro-optical device substrate.

When the signal on the signal electrode is of a pulse width modulation type, it is needless to say that digital driving of the pixel can be realized. However, in the present invention, the pixel driving type is not a dynamic driving but a static driving based on temporarily stored data. Since driving is performed, there is no attenuation of the pixel driving signal, and complete digital driving is possible.

In the first means, for example, when there are a plurality of memory cells connected in parallel which operate alternately or exclusively with respect to the signal electrodes,
It is necessary to switch each storage cell, and the pixel electrode cannot always be statically driven by the same storage cell.

Therefore, a second means adopted by the present invention is to provide an electro-optical device substrate having pixel electrodes at pixels corresponding to matrix intersections of scanning electrodes and signal electrodes, respectively.
Digital storage means for temporarily storing and holding digital data arriving at the signal electrode while sequentially shifting the data to a plurality of cascade-connected storage cells, and driving pixels based on the storage output of the last-stage storage cell, corresponds to each pixel. It is characterized by being provided.

According to such digital storage means,
Since the memory cell for statically driving the pixel electrode always serves as the last-stage memory cell, complete digital driving is possible. In general, it is sufficient to configure the memory cells in two stages, but three or more memory cells may be provided.
When the number of storage cells is two or more, a delay means having a phase shift amount of a certain period or more is provided, and it can be said that it corresponds to a shift register or an FIR filter having one or more taps.

In the case where the number of storage cells is two, the digital storage means includes first latch means for fetching digital data arriving at the signal electrode and temporarily storing the digital data; The first latch means reads the preceding digital data before the data fetch operation of the first latch means, temporarily stores the data, and drives the pixel based on the stored output. Here, the second latch means is characterized in that it is driven statically, and the first latch means is characterized in that it functions as data delay means.

The first latch means has first data selection means for taking in digital data, and first flip-flop for temporarily storing data taken in by the first data selection means, and Is temporarily stored with the second data selecting means for taking in the output data of the first flip-flop and the data taken in by the second data selecting means, and the storage output is electrically connected to the pixel electrode. And a second flip-flop. The first flip-flop functions as data delay means,
Function as static driving means for the pixel electrodes.

The data selection means can have various configurations. For example, the first data selection means is a first data transfer transistor that is turned on in synchronization with a first timing pulse, and the first flip-flop is a first synchronization transistor that performs a storage operation in synchronization with the first timing pulse. A second flip-flop, a second data selecting means, a second data transfer MOSFET, which is turned on in synchronization with a second timing pulse generated before the second timing pulse, and a second flip-flop, A second synchronous flip-flop that performs a storage operation in synchronization with a pulse can be provided.
The data selection means can be constituted by one transistor, which is effective for reducing the number of elements.

The first data selecting means operates as a first one-input type gate element in synchronization with the first timing pulse, and the first flip-flop operates as a memory in synchronization with the first timing pulse. A first synchronous flip-flop, a second data selecting means, a second one-input type gate element that performs a logical operation in synchronization with the second timing pulse, and a second flip-flop, the second timing pulse. And a second synchronous flip-flop that performs a storage operation in synchronization with the second synchronous flip-flop. When a one-input type gate element is used as the data selection means, two or more transistors are required. However, it is effective for reduction of power consumption, waveform shaping, and energy amplification, and functions as a write driving means to ensure storage operation. Contribute. The one-input gate element may be, for example, a clocked inverter or a three-state buffer.

Various configurations are possible for the flip-flop. For example, the first synchronous flip-flop is provided with a first even-numbered inverting circuit in which an even number of inverters are cyclically connected, and an electric signal between an input of the first-stage inverter and an output of the feedback-stage inverter synchronized with the first timing pulse. A first storage hold control transistor for temporarily disconnecting a connection, a second synchronous flip-flop comprises a second even inverting circuit in which an even number of inverters are cyclically connected, and a second timing pulse. And a second memory holding control transistor for temporarily disconnecting the electrical connection between the input of the first-stage inverter and the output of the feedback-stage inverter in synchronization with the first storage inverter.

When a logical value different from the logical value stored and held in the even number inverting circuit is set from the data selecting means,
If the output of the feedback stage inverter is connected to the input of the even number inverting circuit, the set logical value and the held logical value interfere with each other,
It becomes unstable. Therefore, at the time of setting, the storage holding is temporarily interrupted by the storage holding control transistor so that the data from the data selection means can be set with priority. After this data setting, the storage control transistor is turned on, so that data storage is achieved.

Also, the first synchronous flip-flop is
A first even-numbered inverting circuit in which even-numbered inverters are cyclically connected, wherein the feedback-stage inverter is a clocked inverter that interrupts a logical operation in synchronization with a first timing pulse, and a second synchronous flip-flop is A second even-numbered inverting circuit in which even-numbered inverters are cyclically connected,
The feedback stage inverter can be a clocked inverter that interrupts the logic operation in synchronization with the second timing pulse. In such a case as well, at the time of setting, the data holding from the data selecting means can be set with the setting priority by temporarily suspending the storage holding by the clocked inverter.

As the even-numbered inverting circuit, a larger number of stages enhances the buffering effect, but a double inverting circuit composed of two inverters may be used. The number of elements can be reduced.

In the electro-optical device substrate of the present invention, a serial-parallel conversion shift register for sending digital data to signal electrodes, a scan electrode selection shift register for sequentially selecting scan electrodes, and a scan electrode selection shift register Latch timing means for generating the first timing pulse based on the scan electrode drive waveform from the shift register for use as a peripheral drive circuit. Cost reduction can be achieved by high-density integration.

The substrate for an electro-optical device according to the present invention is not limited to a substrate in which the above-mentioned digital storage unit is formed in a single crystal semiconductor substrate, but may be formed by forming a TFT or the like by a thin film technique on an insulating transparent substrate such as a glass substrate or a quartz substrate. It may be formed. Although the number of elements is slightly larger than that of the conventional active element circuit, the aperture ratio does not matter much in a projection display device or the like. Fully available.

An electro-optical device is assembled by using an electro-optical device substrate and a transparent substrate facing the electro-optical device, and sandwiching an electro-optical material in a gap therebetween. As electro-optic materials,
Not only liquid crystals but also new electro-optical materials for voltage-driven elements such as EL (electroluminescence) materials and DMD (digital mirror device) materials can be used.

Here, in the electro-optical device, a common voltage that is switched every predetermined period (for example, a frame period) is applied to the counter electrode of the transparent substrate via the electro-optical device substrate or directly to the counter electrode of the transparent substrate. In this case, the AC driving of the electro-optical material can be performed even when the AC driving of the pixel electrode is difficult. For example, when the electro-optic material is a liquid crystal, liquid crystal deterioration can be prevented. Further, since the logic amplitude of the signal applied to the pixel electrode can be relatively reduced, the active element of the digital storage means can be formed as a low withstand voltage element, and the occupied area can be reduced by miniaturizing the element. By increasing the rate, a high-density high-definition display device can be realized.

When such an electro-optical device is used in a display section of various electronic devices, a high-quality display can be obtained.
For example, it is suitable for a light valve of a projection display device.

[0043]

Next, embodiments of the present invention will be described with reference to the accompanying drawings.

[Embodiment 1] FIG. 1 shows Embodiment 1 of the present invention.
And FIG. 2A is a circuit diagram showing a digital storage circuit provided for each pixel of the matrix liquid crystal display element driving circuit formed on a panel substrate for a reflection type liquid crystal panel according to the present invention. FIG. 2B is a timing chart for explaining the operation of the digital memory circuit element circuit, and FIG. 3 is a timing chart for explaining the overall operation of the matrix liquid crystal display element driving circuit.

The reflection type liquid crystal panel substrate of this embodiment is also shown in FIG.
Similar to the conventional panel substrate shown in FIG. 8, active elements are formed on the main surface of a large-sized single crystal semiconductor substrate (for example, 20 mm square), and an interlayer insulating film and a conductive layer are alternately stacked thereon. It has a large number of rectangular pixel electrodes (reflection electrodes) 14 (see FIG. 2A) which are formed and arranged in a matrix in a pixel region which occupies a main area in plan view.

A matrix liquid crystal display element driving circuit 50 shown in FIG. 1 includes a matrix circuit 51 formed immediately below a pixel region of a semiconductor substrate, and display digital data (DATA) received by serial transfer. A serial-parallel conversion shift register (signal electrode drive circuit, X driver) 52 for line-sequentially sending signal electrodes (X) X _{0 to} X _m addressed to one row per column, and digital storage for each pixel of a matrix circuit 51 A latch control signal (write timing signal) is supplied to the circuit M (M _{00 to} M _nm ) in a row-
Scan electrodes Y ₁ (Y _{10 to} Y _1n ) and Y ₂ (Y ₂₀ to
Y _2n ), and a second timing pulse (positive-phase read clock pulse RCK (φ3)) for driving all the pixel electrodes 14 at the same time. Phase read clock pulse
Each pixel row transmitting the RCK bar (φ4) has two scanning electrodes Y ₃ (Y _{30 to} Y _3n ) and Y ₄ (Y _{40 to} Y _4n ). Here, the serial-parallel conversion shift register 52 and the scan electrode drive circuit 53 constitute a peripheral circuit for the matrix circuit 51 in the central pixel area.

The serial-parallel conversion shift register 52, the display digital data (DATA = D _m ~D ₀₎ in synchronization with the shift clock CLX shift transferred one horizontal period each to the signal electrode X ₀ to X _m of the serial column The corresponding pixel data D ₀ to
Appear D _m . The scan electrode drive circuit 53 supplies a scan start pulse (frame start pulse) DY to a shift clock.
A scan electrode side shift register (Y shift register) 53a which shift-transfers in synchronization with CLY and sequentially generates row drive timing pulses Φ _{0 to} Φ _n on a pixel row every one vertical period.
And a first timing pulse (a positive-phase latch control pulse φ1 and a negative-phase latch control pulse φ1) on scan electrodes Y ₁ and Y ₂ based on row drive timing pulses Φ _{0 to} Φ _n and write clock pulse WCK. and a latch timing circuit 53b for generating φ2.

The latch timing circuit 53b generates row drive timing pulses Φ _{0 to} Φ corresponding to each pixel row.
The logical product of _n and the write clock pulse WCK and outputs as positive phase of the latch control pulse φ1 to the first on the scanning electrode Y _1, the inverted output of the AND output φ1 as a latch control pulse φ2 of opposite phase Logic circuits G _{0 to} G _n that output signals on the _two scan electrodes Y ₂ .

The matrix circuit 51 includes a digital storage circuit M shown in FIG. 2A at each matrix intersection of a signal electrode X extending in the column direction and a scanning electrode Y extending in the row direction. (M _{00 to} M _nm ). Each digital storage circuit M includes a data input D of the digital data D _i coming to the signal electrode X _i is input, the pixel electrodes sandwiching the liquid crystal 37 between the common electrode 33 of the opposite substrate (not shown) side 14, a storage output Q for applying a drive voltage
With the door, the prior frame period (the odd frame period) a first latch circuit for capturing by temporarily storing digital data D _i coming to the signal electrode X _i in L1
When, the storage output Q with temporarily storing read digital data D _i temporarily stored in the first latch circuit L1 in the lagging frame period (e.g., the even frame period) before the latch operation of the first latch circuit L1 And a second latch circuit L2 that outputs the data to the second latch circuit L2. Vcom in FIGS. 1 and 2A is a common potential applied to the common electrode 33 on the counter substrate (not shown).

The first latch circuit L1 includes an N-channel first data transfer MOSFET (T1) for taking in digital data in synchronization with the positive-phase latch control pulse φ1 on the first scan electrode _Y1i. , First MOS for data transfer
The data passed through the FET (T1) is transferred to the second scan electrode Y _2i.
And a first synchronous flip-flop F1 that performs a temporary storage operation in synchronization with the disappearance of the above-mentioned latch control pulse φ2 having the opposite phase. The second latch circuit L2, the third scan electrode Y _3i on the positive phase of the read clock pulse RCK (phi
3) an N-channel type second data transfer MOSFET (T2) for taking in the output data of the first synchronous flip-flop F1 in synchronization with 3) and a second data transfer MOSF
A second synchronous flip-flop that temporarily stores data passing through ET (T2) in synchronization with the disappearance of the negative-phase latch control pulse φ4 on the fourth scan electrode _Y4i , and outputs the data to its storage output Q F2, the first synchronous flip-flop F1 having two inverters INV1, INV2
, And temporarily disconnects the electrical connection between the input of the first stage INV1 and the output of the feedback stage INV2 in synchronization with the negative-phase latch control pulse φ2.
Channel-type first storage control MOSFET (Q
1). Second synchronous flip-flop F
Reference numeral 2 designates a second double inverting circuit in which two inverters INV3 and INV4 are cyclically connected, and an electrical connection between the input of the first-stage inverter INV3 and the output of the feedback-stage inverter INV4 in synchronization with the read pulse φ4 having the opposite phase. Storage control MOSFET for temporarily disconnecting dynamic connection
(Q2).

[0051] As shown in FIG. 3, in the odd frame period 1F, the liquid crystal alternating signal FR which replaces each cutting frame rises, in synchronism with the rising edge, the positive phase of the on the third scan electrode Y ₃₀ to Y _3n Read timing pulse RCK
(Φ3) is generated, and the fourth scan electrodes Y _{40 to} Y _4n
A read timing pulse RCK (φ4) having an opposite phase is generated above. At the same time when the AC signal FR rises, the scan start pulse DY is applied to the scan electrode side shift register 53a,
The row drive timing pulses Φ _{0 to} Φ _n are sequentially generated in synchronization with the shift clock CLY generated at regular intervals, and the write clock pulse WCK is generated by the shift clock CLY.
Occurs in synchronization with. Therefore, the first scan electrodes Y ₁₀ to Y positive phase of the latch control pulse .phi.1 ₀ to [phi] is on _1n pixel row
1 _n (φ1) is generated and the second scan electrodes Y ₂₀ to Y ₂₀ .
On Y _2n , latch control pulses φ2 _{0 to} φ2 _n (φ
2) is generated.

Accordingly, the first to fourth scan electrodes Y _{i1 to} Y _i4
Generates pulses φ1 to φ4 in the order shown in FIG. Previous frame period (eg, odd frame period) 1
When the latch control pulses φ1 and φ2 are generated on the first scan electrode Y _i1 and the second scan electrode Y _i2 during the writing period W1 of F, the first synchronous flip-flop F1 generates the first
The data transfer MOSFET (T1) is turned on and the first memory holding control MOSFET (Q1) is turned off, so that the output of the feedback stage inverter INV2 does not return to the first stage inverter INV1 and the first data transfer MOSFET (T1) is turned off. MOS
The logic value of the preceding data D1 from the FET (T1) is applied to the first-stage inverter INV1, and its inverted logic value appears at the output of the first-stage inverter INV1. Latch control pulse φ1
And φ2 have disappeared and the writing period W1 ends, the first
Since the data transfer MOSFET (T1) is turned off and the first storage holding control MOSFET (Q1) is turned on, the output of the feedback-stage inverter INV2 is fed back to the first-stage inverter INV1, and the first synchronous flip-flop is turned off. The storage operation of F1 functions again, and the preceding data D1 is temporarily stored in the first synchronous flip-flop F1.

In the next lagging frame period (eg, even frame period) 2F, the third scanning electrode Y _i3 in the reading period W1.
And the read clock pulse φ3 on the fourth scan electrode Y _i4.
And φ4 occur, the second synchronous flip-flop F
2, the second MOSFET for data transfer (T2)
Is turned on and the second memory holding control MOSFET
Since (Q2) is turned off, the output of the feedback-stage inverter INV4 does not feed back to the first-stage inverter INV3, and the inverted logical value of the preceding data D1 from the first synchronous flip-flop F1 is applied to the first-stage inverter INV3. The inverted logic value, that is, the logic value of the data D1 is
Appears at the output of NV3. When the read clock pulses φ3 and φ4 disappear and the read period W1 ends, the second data transfer MOSFET (T2) is turned off, and
Since the second storage control MOSFET (Q2) is turned on, the output of the feedback-stage inverter INV4 is fed back to the first-stage inverter INV3, and the second synchronous flip-flop FV is turned on.
The storage operation of No. 2 functions again, the preceding data D1 is temporarily stored in the second synchronous flip-flop F2, and the storage output Q is continuously supplied to the pixel electrode 14. afterwards,
When the latch control pulses φ1 and φ2 are generated on the first scan electrode Y _i1 and the second scan electrode Y _i2 during the writing period W2,
As in the above-described order, the storage content of the first synchronous flip-flop F1 is rewritten to the delay data D2.

Although the writing method of this example is a line sequential method,
The write sequence stays only in the first synchronous flip-flop F1, and the write sequence does not spread to the second synchronous flip-flop F2. Therefore, frame switching display of all pixels can be performed at the same time, and nonuniformity of the display screen can be eliminated. Irrespective of the number of pixels, it is possible to realize a large screen with high image quality or high definition. Since simultaneous still display of all pixels of the previous frame can be realized during the writing operation of the subsequent frame, the display time and the writing time do not conflict within one frame period, and the display time can be made longer than before, and Even higher image quality can be achieved. In addition, since the writing period can be lengthened, the signal transfer speed of the display data DATA can be reduced, and the peripheral circuit configuration can be simplified. In addition, an external frame memory for display data can be eliminated. A higher pixel count can be realized.

The second flip-flop F2 of this embodiment functions as a driver for statically driving the pixel electrode 14. Unlike dynamic driving, there is no attenuation of the pixel driving signal and complete digital driving becomes possible.

Note that the first and second data transfer M
The OSFETs (T1, T2) are turned on / off mutually exclusively, and the first and second storage holding control MOSFETs (Q
1, Q2) are also turned on / off mutually exclusively, but the first and second data transfer MOSFETs (T1, T2)
2) are of opposite conductivity types, and the first and second storage holding control MOSFETs (Q1, Q2) are also of opposite conductivity types, so that both the positive-phase pulse and the negative-phase pulse are digital storage circuits. M need not be sent to the scanning electrode 2
Books can be reduced.

[Embodiment 2] FIG. 4 is a circuit diagram showing another digital storage circuit. In FIG. 4, the same components as those of the first embodiment are denoted by the same reference numerals, and the description thereof will be omitted.

The substrate for the reflection type liquid crystal panel of this example is also shown in FIG.
Similar to the conventional panel substrate shown in FIG. 8, active elements and capacitive elements are formed on the main surface of a large-sized single crystal semiconductor substrate (for example, 20 mm square), and an interlayer insulating film and a conductive layer are alternately formed thereon. And a large number of rectangular pixel electrodes (reflection electrodes) 14 arranged in a matrix in a pixel region that occupies a main area in plan view. This example also has the same serial-to-parallel conversion shift register 52 and scan electrode drive circuit 53 as in the first embodiment, but the configuration of the digital storage circuit M 'is different from that of the first embodiment. ing.

[0059] The digital storage circuit M ', similar to the digital storage circuit M, the pixel electrode 14 digital data D _i is sandwiching liquid crystals 37 on the data input D and the common electrode 33 to enter coming to the signal electrode X _i and a storage output Q for applying a driving voltage, and the preceding frame period (the odd frame period) a first latch circuit L1 which takes in temporarily storing digital data D _i coming to the signal electrode X _i in ' succeeding frame period (e.g., the even frame period) at the output of the first digital data D _i temporarily stored in the latch circuit L1 in the storage output Q while Loading temporarily stored before latching operation of the first latch circuit L1 And a second latch circuit L2 '.

The first latch circuit L1 'receives the digital data _Di as an input, and performs a logical operation on the first clocked inverter K1 in synchronization with the positive-phase latch control pulse φ1 on the first scan electrode _Y1i. And a first synchronous flip-flop F for temporarily storing the output data in synchronization with the disappearance of the opposite-phase latch control pulse φ2 on the second scan electrode _Y2i.
1 '. Also, the second latch circuit L2 '
Includes a clocked inverter K2 for logic operation in synchronization with the first output data of the synchronous flip-flop F1 and the input third scan electrodes Y _3i on the positive-phase read clock pulse RCK (.phi.3), the read clock pulse RCK bar opposite phase of output data on the fourth scan electrode Y _4i (phi
4) Temporary storage operation is performed in synchronization with the disappearance of
And a second synchronous flip-flop F2 '.

The first synchronous flip-flop F1 '
A first double inverting circuit in which two inverters INV1 and INV2 'are cyclically connected, and a feedback stage inverter I
NV2 'is a clocked inverter which interrupts the logic operation in synchronization with the opposite-phase latch control pulse φ2, and the second synchronous flip-flop F2' also has two inverters IN
V3, INV4 'is a second double inverting circuit in which the feedback stage inverter INV4' is a clocked inverter which interrupts the logic operation in synchronization with the read clock pulse φ4 having the opposite phase.

As shown in FIG. 2B, during the writing period W1 of the preceding frame period (eg, odd frame period) 1F, the latch control pulses φ1 and φ2 are applied on the first scanning electrode Y _i1 and the second scanning electrode Y _i2. Occurs, in the first synchronous flip-flop F1 ', the first clocked inverter K1 performs a logical operation and the feedback stage inverter INV
2 'interrupts the logic operation, so that the feedback stage inverter IN
The output of V2 'does not feed back to the first-stage inverter INV1, the logical value of the preceding data D1 from the first clocked inverter K1 is applied to the first-stage inverter INV1, and its inverted logical value appears at the output of the first-stage inverter INV1. When the latch control pulses φ1 and φ2 disappear and the writing period W1 ends, the first clocked inverter K1 suspends the logical operation and the feedback stage inverter INV2 ′ performs the logical operation, so that the output of the feedback stage inverter INV2 ′ Is fed back to the first-stage inverter INV1, the storage operation of the first synchronous flip-flop F1 'is re-functioned, and the preceding data D1 is temporarily stored in the first synchronous flip-flop F1'.

In the next lagging frame period (for example, even frame period) 2F, the third scanning electrode Y _i3 in the reading period W1.
And the read clock pulse φ3 on the fourth scan electrode Y _i4.
And φ4 occur, the second synchronous flip-flop F
In 2 ', since the second clocked inverter K1 performs a logical operation and the feedback-stage inverter INV4' interrupts the logical operation, the output of the feedback-stage inverter INV4 'does not feed back to the first-stage inverter INV3, and the first synchronous operation is performed. The logic value of the preceding data D1 from the formula flip-flop F1 'is applied to the first-stage inverter INV3, and its inverted logic value appears at the output of the first-stage inverter INV3. When the read clock pulses φ3 and φ4 disappear and the read period W1 ends, the logic operation of the second clocked inverter K1 is interrupted, and the output of the feedback stage inverter INV4 ′ is performed because the feedback stage inverter INV4 ′ performs the logic operation. Is fed back to the first-stage inverter INV4, and the storage operation of the second synchronous flip-flop F2 'is re-functioned, and the preceding data D1
Is temporarily stored in the second synchronous flip-flop F2 ', and its storage output Q is continuously supplied to the pixel electrode 14. Thereafter, when the latch control pulses φ1 and φ2 are generated on the first scan electrode Y _i1 and the second scan electrode Y _i2 during the writing period W2, the first synchronous flip-flop F1 ′ is turned on in the same manner as described above. The stored content is rewritten to the delay data D2.

This embodiment also has the same operation and effect as the first embodiment.

Since the digital storage circuit M 'of this embodiment uses a clocked inverter, the power consumption can be reduced.
It is effective for waveform shaping and energy amplification, and contributes to secure memory operation. Note that the clocked inverters K1,
Instead of K2, a three-state buffer may be used.

In the above-described embodiment, the counter electrode (common electrode) 33 on the transparent substrate assembled to face the reflective liquid crystal panel substrate may have a fixed potential, but a relatively high voltage (switching for each frame). The liquid crystal alternating signal FR) may be applied.

By performing a so-called common swing in which the common potential Vcom of the counter electrode 33 is alternated for each frame, it is possible to prevent the deterioration of the liquid crystal cell LC, and it is also possible to relatively reduce the logical amplitude of the signal applied to the pixel electrode 14. Therefore, the active elements constituting the digital storage circuit M (M ') can be formed as low withstand voltage elements. This allows
An occupied area can be reduced by miniaturizing the element, and a high-density, high-definition display device can be realized by increasing the aperture ratio.

The liquid crystal panel substrate of the above embodiment is suitable for use in a reflection type liquid crystal panel. The reflection type liquid crystal panel can be used not only for the light valve of the liquid crystal projector described above, but also for a wristwatch type electronic device, a word processor and the like. ,
The present invention can be applied to a portable information processing device such as a personal computer, a display portion of a mobile phone, and a display portion of other various electronic devices.

Although the liquid crystal panel substrate of the above embodiment has switching elements formed on the main surface of the semiconductor substrate, the present invention is not limited to the semiconductor substrate but may be an insulating substrate such as a glass substrate or a quartz substrate. Can be used. It goes without saying that the present invention can be applied to a case where a thin film transistor (TFT) or the like is formed on an insulating substrate as a switching element.

Further, the present invention is not limited to the liquid crystal panel substrate,
It can be applied to other flat display substrates.

[0071]

As described above, according to the present invention, a pixel based on preceding digital data temporarily stored and held in a substrate for an electro-optical device provided with pixel electrodes at pixels corresponding to matrix intersections of scanning electrodes and signal electrodes, respectively. Digital storage means for simultaneously and concurrently performing the driving operation and the temporary storage operation for the delayed digital data of the same pixel arriving at the signal electrode after a predetermined time from the preceding signal is provided for each pixel. Since it is a feature, the following effects are obtained.

(1) The digital data writing sequence does not appear as a pixel driving sequence as it is, and frame switching display of all pixels at the same time and display simultaneousness of all pixels can be realized.

As a result, unevenness of the display screen can be eliminated, and a high quality electro-optical device substrate can be provided. Therefore, regardless of the number of pixels, it is possible to realize a large screen and high definition of high image quality. Further, the display time and the writing time do not conflict with each other within one frame period, and the display time of all the pixels can be made longer than before, so that higher image quality can be achieved. Further, the writing operation of all pixels can be realized over a certain period (for example, one frame period), and the writing period can be lengthened. It is possible to simplify the peripheral circuit configuration or increase the number of pixels by reducing the signal transfer speed. Moreover,
A frame memory for display data externally attached to the substrate for the electro-optical device becomes unnecessary.

Further, in the present invention, the pixel driving method is not the dynamic driving but the static driving based on the temporarily stored data.
Completely digital drive becomes possible.

(2) Further, according to the present invention, in a substrate for an electro-optical device provided with pixel electrodes at pixels corresponding to matrix intersections of scanning electrodes and signal electrodes, a plurality of storages in which digital data arriving at signal electrodes are cascaded. Digital storage means for temporarily storing the data while sequentially shifting the cells and driving the pixels based on the storage output of the last storage cell is provided for each pixel. According to such digital storage means,
Since the storage cell that statically drives the pixel electrode always serves as the last-stage storage cell, complete digital drive is possible.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a matrix liquid crystal display element driving circuit built in a panel substrate for a reflective liquid crystal panel according to a first embodiment of the present invention.

FIG. 2A is a circuit diagram showing a digital storage circuit provided for each pixel of the matrix liquid crystal display element driving circuit,
FIG. 2B is a timing chart for explaining the operation of the digital storage circuit.

FIG. 3 is a timing chart for explaining an overall operation of the matrix liquid crystal display element driving circuit.

FIG. 4 is a circuit diagram showing another digital storage circuit according to Embodiment 2 of the present invention.

FIG. 5 is a schematic configuration diagram showing a video projector as an example of a projection display device using a reflective liquid crystal panel as a light valve.

FIG. 6 is a sectional view showing a reflection type liquid crystal panel.

FIG. 7 is a circuit diagram showing an active matrix liquid crystal display element driving circuit of a conventional reflective liquid crystal panel substrate used for a reflective liquid crystal panel.

FIG. 8 is a plan view showing the reflective liquid crystal panel substrate of FIG. 8;

9 is a partial plan view showing a pixel region of the reflective liquid crystal panel substrate of FIG.

FIG. 10 is a sectional view showing a state of being cut along the line AA ′ in FIG. 9;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... P ^- type semiconductor substrate 2 ... P type well region 3 ... Field oxide film 4 ... Gate line 4a ... Gate electrode 4b ... Gate insulating film 5b ... N ⁺ type drain region 6 ... First interlayer insulating film 6a, 6b Reference numeral 6c Contact hole 7 Data line 7a Source electrode wiring 8 P-type capacitance electrode region 9a Capacitance electrode 9b Insulating film (dielectric film) 10 Relay wiring 11 Second interlayer insulating film 12 Light-shielding film 12a ... Plug penetration opening 12b ... Connection wiring 13 ... Third interlayer insulating film 14 ... Pixel electrode 15 ... Connection plug (interlayer conductive part) 17 ... Passivation film 20 ... Pixel area (display area) 21 ... Data line drive circuit (X driver) 22R, 22L scanning line drive circuit (Y driver) 23 precharge and test circuit 24 image signal sampling circuit 25 light shielding film 26 input terminal Sub pad 27 ... Seal area 29R, 29L ... Relay terminal pad (silver point) 30 ... Reflective liquid crystal panel 31 ... Reflective liquid crystal panel substrate 32 ... Support substrate 33 ... Counter electrode (common electrode) 35 ... Glass substrate 37 ... Liquid crystal Reference numeral 38: anisotropic conductive film (ACF) 39: flexible tape wiring 50: matrix liquid crystal display element driving circuit 51: matrix circuit 52: shift register for serial / parallel conversion (X driver) 53: scanning electrode driving circuit (Y driver) 53a ... Scan electrode side shift register 53b Latch timing circuit 100 Polarized illumination device 110 Light source unit 120 Integrator lens 130 Polarization conversion element 200 Polarized beam splitter 201 S-polarized light beam reflecting surface 412, 413 Dichroic mirror 300B, 300R , 300G… Reflective liquid crystal light Lube 500 ... projection system 600 ... screen _{M, M 00 ~M nm, M} '... digital storage circuit L1, L1' ... first latch circuit L2, L2 '... second latch circuit T1 ... first data transfer MOSFET T2: second data transfer MOSFET F1, F1 ': first synchronous flip-flop F2, F2': second synchronous flip-flop INV1-INV4: CMOS inverter K1, K2, INV2 ', INV4' ... clocked inverter G ₀ ~G _n ... logic φ1, φ1 ₀ ~φ1 _n ... positive phase of the latch control pulse φ2, φ2 ₀ ~φ2 _n ... reversed phase latch control pulse .phi.3 ... positive phase of the read clock pulse .phi.4 ... Read clock pulse in opposite phase Φ ₀ -Φ _n ... row drive timing pulse WCK ... write timing pulse RCK ... read timing Pulse L ₀ ... system optical axis LC ... liquid crystal cell _{X, X i, X 0 ~X} m ... signal electrodes Y ... scan electrodes Y _i1, Y ₁₀ ~Y _1n ... first scan electrodes Y _i2, Y ₂₀ ~Y _2n ... Second scan electrode Y _i3 , Y _{30 to} Y _3n . Third scan electrode Y _i4 , Y _{40 to} Y _4n . Fourth scan electrode FR. Liquid crystal alternating signal CLX, CLY... Shift clock DY... Pulse _Di : Digital data _Vcom : Counter potential (common potential).

Claims (15)

[Claims] 1. An electro-optical device substrate comprising a pixel electrode corresponding to a matrix intersection of a scanning electrode and a signal electrode, the pixel driving operation being based on preceding digital data temporarily stored and held for a predetermined time from the preceding digital data. A digital storage means for simultaneously and concurrently performing a temporary storage operation for delayed digital data of the same pixel arriving at the signal electrode later is provided correspondingly for each pixel. substrate. 2. In an electro-optical device substrate provided with a pixel electrode at each pixel corresponding to a matrix intersection of a scan electrode and a signal electrode, digital data arriving at the signal electrode is sequentially shifted to a plurality of cascade-connected storage cells. A substrate for an electro-optical device, wherein digital storage means for temporarily storing and holding the data and driving the pixels based on the storage output of the last storage cell is provided in correspondence with each of the pixels. 3. The digital storage device according to claim 2, wherein the digital storage means takes in the digital data arriving at the signal electrode and temporarily stores the digital data, and the first latch means stores the digital data more than the digital data. The preceding digital data stored a fixed time ago is stored in the first
And temporarily stores the data before the data fetch operation of the latch means and drives the pixels based on the stored output.
And a latching means for the electro-optical device. 4. The first latch means according to claim 3, wherein said first latch means is a first data selection means for taking in said digital data, and a first flip-flop for temporarily storing data taken in by said first data selection means. A second data selection unit that captures output data of the first flip-flop; and temporarily stores data captured by the second data selection unit;
A second flip-flop whose storage output is electrically connected to the pixel electrode. 5. The first data selection means according to claim 4, wherein said first data selection means is a first data transfer transistor which is turned on in synchronization with a first timing pulse, and said first flip-flop is said first data transfer means. A first synchronous flip-flop that performs a storage operation in synchronization with a timing pulse, wherein the second data selection unit is turned on in synchronization with a second timing pulse generated before the second timing pulse; 2. The data transfer transistor of claim 2,
Wherein the flip-flop is a second synchronous flip-flop that performs a storage operation in synchronization with the second timing pulse. 6. The device according to claim 4, wherein the first data selection means is a first one-input type gate element that performs a logical operation in synchronization with the first timing pulse, and wherein the first flip-flop is provided with the first flip-flop. A first synchronous flip-flop that performs a storage operation in synchronization with a first timing pulse;
The second data selection means is a second one-input type gate element that performs logical operation in synchronization with the second timing pulse, and the second flip-flop stores the data in synchronization with the second timing pulse. An electro-optical device substrate, which is a second synchronous flip-flop that operates. 7. The substrate for an electro-optical device according to claim 6, wherein the one-input gate element is a clocked inverter. 8. The substrate for an electro-optical device according to claim 6, wherein said one-input type gate element is a three-state buffer. 9. The first synchronous flip-flop according to claim 5, wherein the first synchronous flip-flop comprises: a first even-numbered inverting circuit in which even-numbered inverters are cyclically connected; A first memory holding control transistor for temporarily disconnecting an electrical connection between an input of the first-stage inverter and an output of the feedback-stage inverter in synchronization with a pulse; and the second synchronous flip-flop has an even number. A second even number inverting circuit in which the inverters are cyclically connected, and a second memory for temporarily disconnecting an electrical connection between an input of the first-stage inverter and an output of the feedback-stage inverter in synchronization with the second timing pulse. A substrate for an electro-optical device, comprising: a holding control transistor. 10. The first synchronous flip-flop according to claim 5, wherein the first synchronous flip-flop is a first even-numbered inverting circuit in which an even number of inverters are cyclically connected, and the feedback stage thereof is An inverter is a clocked inverter that interrupts a logical operation in synchronization with the first timing pulse, and the second synchronous flip-flop is a second even-numbered inverting circuit in which an even number of inverters are cyclically connected. Wherein the feedback stage inverter is a clocked inverter that interrupts a logic operation in synchronization with the second timing pulse. 11. The substrate for an electro-optical device according to claim 9, wherein the even number inverting circuit is a double inverting circuit including two of the inverters. 12. The shift register for serial / parallel conversion according to claim 1, wherein the digital data is sent to the signal electrode, and a shift electrode for sequentially selecting the scan electrode. A substrate for an electro-optical device, comprising: a register; and latch timing means for generating the first timing pulse based on a scan electrode drive waveform from the scan electrode selection shift register as a peripheral drive circuit. . 13. An electric device comprising an electro-optical material sandwiched in a gap between an electro-optical device substrate defined in claim 1 and a transparent substrate facing the electro-optical device substrate. Optical device. 14. An electronic apparatus comprising the electro-optical device defined in claim 13 for a display unit. 15. A projection display device comprising the electro-optical device defined in claim 14 for a light valve.