JP2000049763A - Receiver, automatic frequency correction device and communication equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce power consumption due to over-sampling, to improve frequency errors between a transmitter and a receiver and to obtain satisfactory reception characteristics in a receiver and an automatic frequency correction device used for the communication equipment of a digital mobile object communication system. SOLUTION: In this receiver, a circuit operation control signal generation means 116 for generating control signals 117 for switching a circuit operation at receiving of preamble signals and the time of receiving the other signals by using data identification timing signals 115 and a sampling clock changeover means 120 for generating a sampling clock 121 changed in the number of samplings, based on the control signals 117 are provided to reduce the number of samplings at times other than the time of receiving the preamble signals and reduce the power consumption of a circuit. Furthermore, by arranging this automatic frequency correction device 118 and using a master clock 119 corrected in the frequency error, satisfactory reception characteristics are obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is used for a communication apparatus such as a digital mobile communication system which requires clock recovery, and which corrects the frequency of a master clock oscillator serving as a reference for performing digital signal processing. The present invention relates to a correction device and a reception device using the same.

[0002]

2. Description of the Related Art In the prior art, when a clock is reproduced only by a preamble signal, oversampling is continued in a portion other than the preamble signal even after the clock is reproduced, so that power consumption required for an operation of oversampling a signal other than the preamble signal is required. Was extra.

When clock recovery is performed only in the preamble portion, the estimated data identification timing signal generally differs from the originally desired received data timing by one due to the frequency shift of the master clock between the transmitter and the receiver.
The error rate is degraded because of the gradual shift between frames.

As a conventional countermeasure, it is possible to set the frame length so that the frequency deviation of the master clock does not cause a problem, or to increase the number of quantizations for phase detection, that is, the number of oversampling.

However, shortening the frame length leads to a decrease in transmission efficiency, and increasing the number of quantizations requires a significant increase in the frequency of the master clock. It was not practical because of the problem.

[0006]

As described above, in the communication device used for mobile communication or the like, the transmission efficiency is not reduced.
In addition, it is required to obtain good reception characteristics without significantly increasing the frequency of the master clock.

SUMMARY OF THE INVENTION It is an object of the present invention to reduce power consumption required for an operation of oversampling, to improve a frequency error of a master clock between transmitting and receiving apparatuses which affects transmission efficiency, and to obtain a good receiving characteristic. And

[0008]

According to the present invention, there is provided a receiver for detecting a preamble signal from a received signal and generating a data identification timing signal indicating the detection timing. Means, a circuit operation control signal generating means for generating a control signal for switching a circuit operation between the time of receiving the preamble signal and the time of receiving other signals using the data identification timing signal, and And a sampling clock switching means for generating a sampling clock signal in which the number of samplings of the reception signal is switched.The number of samplings can be switched between when the preamble signal is received and when other signals are received. The number of samples can be reduced except when receiving a preamble signal. It is possible to reduce the power consumption of the circuit Te.

As a result, a low power consumption receiving device and a communication device using the same can be obtained.

[0010] The receiving apparatus of the present invention further includes clock recovery means for recovering a clock for determining received data by using a data identification timing signal, wherein the clock recovery means controls the clock based on a control signal. Since the reproduction operation is turned on / off, the power consumption of the circuit can be further suppressed by turning off the clock reproduction operation except when the preamble signal is received.

As a result, a low power consumption receiving apparatus and a communication apparatus using the same can be obtained.

Further, according to the present invention, a receiving apparatus receives a frame synchronization signal generated using received data, detects an edge thereof, and uses the edge to detect a reception timing of a preamble signal included in the received signal. Edge generation means for generating an edge signal indicating the following, and circuit operation control signal generation means for using the edge signal to generate a control signal for switching a circuit operation between reception of the preamble signal and reception of other signals And a sampling clock switching means for generating a sampling clock signal in which the sampling number of the reception signal is switched based on the control signal, and when the preamble signal is received and when other signals are received. The sampling number can be switched by using the sampling function except when the preamble signal is received. It is possible to suppress the power consumption of the circuit by reducing the.

As a result, a low power consumption receiving device and a communication device using the same can be obtained.

Further, the receiving apparatus of the present invention further comprises a data identification timing signal generating means for detecting a preamble signal from the received signal and generating a data identification timing signal indicating the detection timing, and using the data identification timing signal. Clock recovery means for performing clock recovery for determining received data by using the clock recovery means, wherein the clock recovery means is configured to turn on / off the clock recovery operation based on a control signal. By turning off the clock recovery operation, the power consumption of the circuit can be further reduced.

As a result, a low power consumption receiving device and a communication device using the same can be obtained.

Alternatively, according to the present invention, there is provided an automatic frequency compensating apparatus which receives a data identification timing signal and a timing signal which is an edge signal, and detects a phase error using the timing signal and a past timing signal. Means for estimating a frequency shift between a transmitter-side master clock and a receiver-side master clock using the phase error, and generating a frequency control signal for controlling an oscillation frequency of the receiver-side master clock. D / A conversion means for digital-to-analog conversion of the frequency control signal, filter means for removing high-frequency components from the output of the D / A conversion means, and oscillation frequency corrected using the output of the filter means Or a voltage-controlled oscillator that generates the receiver-side master clock,
Alternatively, instead of the D / A conversion means, the filter means, and the voltage-controlled oscillator, a digitally-controlled oscillator that generates the receiver-side master clock whose oscillation frequency has been corrected using the frequency control signal is provided. so,
The frequency deviation between the transmitter and the receiver can be automatically corrected.

As a result, a receiving apparatus and a communication apparatus using the receiving apparatus which can suppress the deterioration of the error rate without lowering the transmission efficiency can be obtained.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention according to claim 1 of the present invention provides a data identification timing signal generating means for detecting a preamble signal from a received signal and generating a data identification timing signal indicating the detection timing, Using an identification timing signal, a circuit operation control signal generating means for generating a control signal for switching a circuit operation between the time of receiving the preamble signal and the time of receiving other signals, and generating the control signal based on the control signal. A sampling clock switching means for generating a sampling clock signal with a changed number of samplings. The receiver is capable of switching the number of oversamplings as needed by a control signal, thereby consuming unnecessary power. Is suppressed.

According to a second aspect of the present invention, there is provided a clock recovery means for recovering a clock for determining received data using a data identification timing signal, wherein the clock recovery means performs the clock recovery operation based on a control signal. ON /
2. The receiver according to claim 1, wherein the clock recovery operation can be switched on / off as needed by a control signal, so that unnecessary power consumption can be suppressed. Have.

According to the third aspect of the present invention, the control signal is a binary digital signal, and the value of the sampling clock switching means is changed between when the preamble signal is received and when other signals are received. 3. The receiving apparatus according to claim 2, wherein the switching is performed to generate a sampling clock signal in which a sampling number is switched, and to be used as an enable signal of a clock recovery operation for a clock recovery unit. It is.

According to a fourth aspect of the present invention, a frame synchronization signal generated by using received data is input, an edge of the signal is detected, and the reception timing of a preamble signal included in the received signal is determined by using the edge. Edge generation means for generating an edge signal, and circuit operation control signal generation means for generating a control signal for switching a circuit operation between the time of receiving the preamble signal and the time of receiving other signals using the edge signal. And a sampling clock switching means for generating a sampling clock signal in which the sampling number of the reception signal is switched based on the control signal. Since the switching can be performed, there is an effect that unnecessary power consumption is suppressed.

According to a fifth aspect of the present invention, there is provided a data identification timing signal generating means for detecting a preamble signal from a received signal and generating a data identification timing signal indicating the detection timing, and receiving using the data identification timing signal. 5. The receiver according to claim 4, further comprising clock recovery means for performing clock recovery for data determination, wherein the clock recovery means turns on / off the clock recovery operation based on a control signal. On / off of the clock recovery operation can be switched as required by the control signal, so that unnecessary power consumption can be suppressed.

According to the present invention, the control signal is a binary digital signal, and the value of the sampling clock switching means is changed between when the preamble signal is received and when other signals are received. The receiving apparatus according to claim 5, wherein the switching is performed to generate a sampling clock signal in which a sampling number is switched, and to be used as an enable signal of a clock recovery circuit for a clock recovery unit. It is.

According to a seventh aspect of the present invention, there is provided a phase error detecting means for inputting a timing signal generated by using a trigger pulse signal and detecting a phase error by using the timing signal and a past timing signal; Frequency error estimating means for estimating a frequency shift between a transmitter-side master clock and a receiver-side master clock using the phase error, and generating a frequency control signal for controlling an oscillation frequency of the receiver-side master clock; D / A conversion means for digital-to-analog conversion of a frequency control signal, filter means for removing high-frequency components from the output of the D / A conversion means, and the receiver for correcting the oscillation frequency using the output of the filter means And a voltage-controlled oscillator for generating a side master clock. Substantial raising of the frequency of the master clock for increasing the number to improve the error rate is not required,
This has the effect that the frequency deviation between the transmitter and the receiver can be automatically corrected with a simple circuit.

According to an eighth aspect of the present invention, there is provided a phase error detecting means for inputting a timing signal generated using a trigger pulse signal, and detecting a phase error using the timing signal and a past timing signal; Frequency error estimating means for estimating a frequency shift between a transmitter-side master clock and a receiver-side master clock using the phase error, and generating a frequency control signal for controlling an oscillation frequency of the receiver-side master clock; A digitally-controlled oscillator for generating the receiver-side master clock whose oscillation frequency has been corrected using a frequency control signal, wherein the automatic frequency correction device is used to improve the error rate by increasing the number of oversampling. It is not necessary to significantly raise the frequency of the master clock, and a simple circuit automatically compensates for frequency deviation between the transmitter and receiver. It has the effect that it can be.

According to a ninth aspect of the present invention, the phase error detecting means counts the master clock on the receiver side up to a preset oversampling number at the time of receiving the preamble signal, and thereafter sets the count value to the initial value. Back,
A counter that repeats counting up to the oversampling number again, a counter value judging device that reads the count value of the counter at all or a part of timing of the timing signal, and a count value that is read at a timing earlier than the count value. And a subtractor for calculating a difference from the phase difference as a phase error.

According to a tenth aspect of the present invention, the frequency error estimating means estimates a frequency shift based on the phase error and sets a weighting amount, and the receiver side using the weighting amount. 10. The automatic frequency correction device according to claim 7, further comprising frequency control signal generation means for generating a frequency control signal for controlling an oscillation frequency of the master clock. .

Further, as in the invention according to claim 11,
The timing signal is a data identification timing signal generated by using a trigger pulse signal generated in synchronization with a detection timing of a preamble signal detected from a reception signal. The same effect is exhibited by the automatic frequency correction device of the above.

Further, as in the invention according to claim 12,
The timing signal detects an edge from a frame synchronization signal, which is a trigger pulse signal generated in synchronization with the frame interval in the received data, and generates the signal to indicate the reception timing of the preamble signal included in the received signal using the edge. 8. An edge signal which has been obtained.
The automatic frequency correction device according to any one of the first to tenth aspects has a similar effect.

According to a thirteenth aspect of the present invention, there is provided the automatic frequency correction device according to the eleventh aspect, wherein the data identification timing signal generated by the data identification timing signal generation means is input as a timing signal. 4. The receiving device according to claim 1, wherein the receiver-side master clock to be output is used as a master clock of a digital unit, wherein power consumption is suppressed and frequency deviation between the transmitter and the receiver is reduced. This has the effect that a receiving device having a stable master clock automatically corrected can be obtained.

According to a fourteenth aspect of the present invention, there is provided the automatic frequency compensating apparatus according to the twelfth aspect, wherein the edge signal generated by the edge generating means is input as a timing signal, and the receiver side outputs the signal. The receiver according to any one of claims 4 to 6, wherein the master clock is used as a master clock of a digital unit, and the power consumption is suppressed and the frequency deviation between the transmitter and the receiver is automatically corrected. There is an effect that a receiving device having a master clock obtained is obtained.

According to a fifteenth aspect of the present invention, there is provided a communication device having the receiving device according to any one of the first to sixth, thirteenth, and fourteenth aspects. This has the effect that a communication device using a receiving device having a stable master clock that has been automatically corrected can be obtained.

An embodiment of the present invention will be described below with reference to FIGS. (Embodiment 1) In this embodiment, π / 4DQPSK
A communication using modulation will be described as an example.

FIG. 1 is a block diagram showing a configuration of a receiving apparatus according to the present embodiment, and mainly shows a demodulation baseband unit. 100 and 101 are the in-phase component and the quadrature component of the received signal that has passed through the Nyquist filter after quadrature detection. After being converted into digital signals 104 and 105 by A / D converters 102 and 103, respectively, they are converted into a phase information signal 107 by a phase converter 106. The phase information signal 107 is input to the adder 110, and the difference between the phase information signal 107 and the signal 109 delayed by one symbol by the delay unit 108 is detected to perform baseband differential detection. Based on the received signal 111 after baseband differential detection, the data identification timing reference signal generation circuit 112 generates a data identification timing reference signal 113 that generates a specific pattern when the receiving device receives the preamble signal.
The data identification timing signal generation circuit 114 detects a preamble signal based on the data identification timing reference signal 113, and generates a data identification timing signal 115 in synchronization with the detection timing.

That is, the data identification timing signal generation means has a data identification timing reference signal generation circuit 112 and a data identification timing signal generation circuit 114, detects a preamble signal from a received signal, and performs data identification indicating the detection timing. A timing signal 115 is generated.

The circuit operation control signal generator 116 estimates the timing between the reception of the preamble signal and the reception of the other signals based on the data identification timing signal 115. When the other signals are received, a circuit operation control signal 117 which is a binary digital signal of 0 is generated.

The sampling clock switch 120 generates a sampling clock 121 in which the frequency of the master clock 119 is switched, for example, according to the state of the circuit operation control signal 117. Then, using the sampling clock 121, the sampling cycle of the A / D converters 102 and 103 is switched. By this means, the number of samplings can be reduced except when the preamble signal is received, so that power consumption can be reduced.

The clock reproducing circuit 122 reproduces the symbol clock 123 and the bit clock 124 based on the generation timing of the data identification timing signal 115.
Using the symbol clock 123 and the bit clock 124, the determiner 125 determines the received signal 111 and outputs received data 126.

Here, the clock recovery circuit 122 uses the circuit operation control signal 117 as an enable signal, and performs the above-described clock recovery operation only when a preamble signal is received. By maintaining the phase, the clock recovery operation can be stopped. By doing so, the clock recovery operation can be turned off except when the preamble signal is received, so that the power consumption of the circuit can be further reduced.

The automatic frequency compensator 118 detects a frequency deviation between the master clock of the transmitter and the master clock of the receiver based on the data identification timing signal 115, and controls the frequency of the master clock of the digital section of the receiver. Thereby, the master clock 119 in which the frequency deviation of the master clock between the transmitter and the receiver is corrected is output to each circuit.
By using this, a stable master clock in which the frequency deviation between the transmitter and the receiver is automatically corrected can be supplied to each unit, and the deterioration of the error rate can be suppressed without lowering the transmission efficiency.

As described above, according to the present embodiment, the receiving apparatus detects a preamble signal from a received signal, and generates a data identification timing signal indicating the detection timing. Using an identification timing signal, a circuit operation control signal generating means for generating a control signal for switching a circuit operation between the time of receiving the preamble signal and the time of receiving other signals, and generating the control signal based on the control signal. By having a sampling clock switching means for generating a sampling clock signal with a switched sampling number, the sampling number can be switched between when the preamble signal is received and when other signals are received. Except during reception, reduce the number of samples and turn off the circuit. It is possible to suppress the power.

Further, there is provided clock recovery means for recovering a clock for determining received data using a data identification timing signal, wherein the clock recovery means turns on / off the clock recovery operation based on a control signal. By turning off the clock recovery operation except when the preamble signal is received, the power consumption of the circuit can be further suppressed.

With such a configuration, a receiving device with reduced power consumption and a communication device using the same can be obtained.

Further, by having an automatic frequency compensating device for outputting a master clock in which the frequency deviation of the master clock between the transmitter and the receiver is corrected based on the data identification timing signal to each section of the circuit, A stable master clock whose frequency deviation is automatically corrected can be supplied to each unit.

With such a configuration, it is possible to obtain a receiving apparatus and a communication apparatus using the receiving apparatus which can suppress the deterioration of the error rate without lowering the transmission efficiency.

(Embodiment 2) In this embodiment, π /
The communication using 4DQPSK modulation will be described as an example.

FIG. 2 is a block diagram showing a configuration of the receiving apparatus according to the present embodiment, and mainly shows a demodulation baseband unit. 100 and 101 are the in-phase component and the quadrature component of the received signal that has passed through the Nyquist filter after quadrature detection. After being converted into digital signals 104 and 105 by A / D converters 102 and 103, respectively, they are converted into a phase information signal 107 by a phase converter 106. The phase information signal 107 is input to the adder 110, and the difference between the phase information signal 107 and the signal 109 delayed by one symbol by the delay unit 108 is detected to perform baseband differential detection. Based on the received signal 111 after baseband delay detection, the data identification timing reference signal generation circuit 112 generates a data identification timing reference signal 113 that generates a specific pattern when the receiving device receives the preamble signal.
The data identification timing signal generation circuit 114 detects a preamble signal based on the data identification timing reference signal 113, and generates a data identification timing signal 115 in synchronization with the detection timing.

That is, the data identification timing signal generation means has a data identification timing reference signal generation circuit 112 and a data identification timing signal generation circuit 114, detects a preamble signal from a received signal, and performs data identification indicating the detection timing. A timing signal 115 is generated.

The channel decoder 200 receives the received data 1
With 26 as an input signal, a unique word is detected to perform frame synchronization, and a frame synchronization signal 201 is generated.
The edge generation circuit 202 detects an edge of the frame synchronization signal 201, and uses the edge to generate an edge signal 2 indicating detection of a preamble signal, which is adjusted to indicate a reception timing of a preamble signal included in the reception signal.
03 is generated.

The circuit operation control signal generator 116 estimates the timing between the reception of the preamble signal and the reception of other signals based on the edge signal 203. For example, when the preamble signal is received, 1 is set. 0 when receiving a signal
, A circuit operation control signal 117 which is a binary digital signal.

The sampling clock switch 120 generates a sampling clock 121 in which the frequency of the master clock 119 is switched, for example, according to the state of the circuit operation control signal 117. Then, using the sampling clock 121, the sampling cycle of the A / D converters 102 and 103 is switched. By this means, the number of samplings can be reduced except when the preamble signal is received, so that power consumption can be reduced.

The clock reproducing circuit 122 reproduces the symbol clock 123 and the bit clock 124 based on the generation timing of the data identification timing signal 115.
Using the symbol clock 123 and the bit clock 124, the determiner 125 determines the received signal 111 and outputs the received data 126, and the channel decoder 200 receives the received data 126 and inputs the frame synchronization signal as described above. 201 is generated.

Here, the clock recovery circuit 122 uses the circuit operation control signal 117 as an enable signal, and performs the above-described clock recovery operation only when receiving a preamble signal. By maintaining the phase, the clock recovery operation can be stopped. By doing so, the clock recovery operation can be turned off except when the preamble signal is received, so that the power consumption of the circuit can be further reduced.

Further, the automatic frequency correction device 118 detects a frequency shift between the master clock of the transmitter and the master clock of the receiver based on the edge signal 203 and controls the frequency of the master clock of the digital section of the receiver. A circuit which outputs a master clock 119 in which the frequency deviation of the master clock between the transmitter and the receiver is corrected to each part of the circuit. By using this, a stable master clock in which the frequency deviation between the transmitter and the receiver is automatically corrected is supplied to each part. And the deterioration of the error rate can be suppressed without lowering the transmission efficiency.

As described above, according to the present embodiment, a receiving apparatus receives a frame synchronization signal generated using received data, detects its edge, and uses the edge to include the frame synchronizing signal in the received signal. Edge generating means for generating an edge signal indicating a reception timing of a preamble signal to be generated, and a control signal for switching a circuit operation between when the preamble signal is received and when other signals are received using the edge signal. A circuit operation control signal generating means, and a sampling clock switching means for generating a sampling clock signal in which the number of samplings of the reception signal is switched based on the control signal, so that when the preamble signal is received, Since the number of samplings can be switched between when the signal is received,
Except when the preamble signal is received, the number of samplings can be reduced to reduce the power consumption of the circuit.

Further, a data identification timing signal generating means for detecting a preamble signal from the received signal and generating a data identification timing signal indicating the detection timing,
Clock recovery means for performing clock recovery for receiving data determination using the data identification timing signal, wherein the clock recovery means is configured to turn on / off the clock recovery operation based on a control signal. Accordingly, the power consumption of the circuit can be further suppressed by turning off the clock recovery operation except when the preamble signal is received.

With such a configuration, a receiving device with reduced power consumption and a communication device using the same can be obtained.

Further, by providing an automatic frequency compensator for outputting a master clock in which the frequency deviation of the master clock between the transceivers is corrected based on the edge signal to each section of the circuit, the frequency deviation between the transceivers is provided. Can be supplied to each section.

With such a configuration, it is possible to obtain a receiving apparatus and a communication apparatus using the same, which suppress the deterioration of the error rate without lowering the transmission efficiency.

(Embodiment 3) FIG. 3 is a block diagram showing a configuration of an automatic frequency correction device according to the present embodiment. 3, a phase error detection circuit 300 receives a timing signal generated using a trigger pulse signal, detects a phase error with a past timing signal, and generates a phase error signal 301. FIG. 3 shows a case where the data identification timing signal 115 generated in synchronization with the detection timing of the preamble signal detected from the received signal is used as the timing signal.
At 0, for example, based on the generation timing of the data identification timing signal 115 during one frame, a phase error with the past data identification timing signal is detected to generate a phase error signal 301.

The frequency error estimating circuit 302 estimates the frequency error of the master clock between the transmitter and the receiver based on the phase error signal 301, and generates a frequency control signal 303.

The frequency control signal 303 is converted into an analog signal 3 by a D / A converter 304 for performing digital / analog conversion.
After the high-frequency component is removed by a low-pass filter (LPF) 306, the control voltage signal 3
07 is input to a voltage controlled oscillator (VCO) 308.

The VCO 308 controls the oscillation frequency using the control voltage signal 307, generates a corrected master clock 119, and outputs it to each circuit.

By correcting the oscillation frequency of the master clock 119 in this manner, the frequency shift between the transmitter and the receiver can be automatically performed by a simple circuit without greatly increasing the frequency of the master clock to increase the number of oversampling. Can be corrected.

Further, the automatic frequency correction device according to the present embodiment may be configured as shown in FIG. FIG. 4 is a block diagram showing a configuration of the automatic frequency correction device according to the present embodiment. 4, the phase error detection circuit 300 and the frequency error estimation circuit 302 have the same configuration and perform the same operation as in FIG.

In FIG. 4, the frequency control signal 303 is input to a digital control oscillator 400, which controls the oscillation frequency using the frequency control signal 303, generates a corrected master clock 119, and Output to each part.

By correcting the oscillation frequency of the master clock 119 in this manner, the frequency shift between the transmitter and the receiver can be automatically performed by a simple circuit without greatly increasing the frequency of the master clock to increase the number of oversampling. Can be corrected.

Further, the phase error detection circuit 300 shown in FIGS. 3 and 4 can have the configuration shown in FIG. FIG. 5 is a block diagram showing a configuration of the phase error detection circuit 300 in the automatic frequency correction device according to the present embodiment.

In FIG. 5, for example, when performing oversampling of 16 times the symbol rate at the time of receiving a preamble, the counter 500 counts up from 0 to 15 at the timing of the master clock 119, counts up to 15, and then returns to 0 again. To count up to 15 is repeated.

When the data identification timing signal 115 is input, the counter 500
And outputs the counter value 501 as the counter determination value 503 until the next data identification timing signal 115 is input.

The delay unit 504 determines the counter determination value 503 output from the counter value determination unit 502 at the time when the data identification timing signal 115 is input, and outputs the same until the next data identification timing signal 115 is input. Keep doing.

That is, the delay unit 504 outputs the immediately preceding counter decision value 50 output from the counter value decision unit 502.
Continue to output 5.

Then, the counter judgment value 503 and the immediately preceding counter judgment value 505 are input to a subtracter 506, and the difference between them is calculated to generate a phase error signal 301.

The frequency error estimating circuit 302 shown in FIGS. 3 and 4 can have the configuration shown in FIG. FIG.
3 is a block diagram showing a configuration of a frequency error estimating circuit 302 in the automatic frequency correction device according to the present embodiment.

In FIG. 6, a weighting circuit 600 performs weighting for frequency control using a phase error signal 301, and a frequency control signal generator 602 generates a frequency control signal 303 based on the weighted signal 601. ,Output.

Although the data identification timing signal is used as the timing signal in the above description, an edge is detected from the frame synchronization signal generated in synchronization with the frame interval in the received data, and the edge is detected and included in the received signal. Even if an edge signal generated to indicate the reception timing of the preamble signal is used as a timing signal,
Similar functions and effects are shown.

As described above, according to the present embodiment, the automatic frequency correction device receives a data identification timing signal and a timing signal as an edge signal, and uses the timing signal and a past timing signal to generate a phase error. Phase error detection means for detecting the frequency error between the transmitter-side master clock and the receiver-side master clock using the phase error, and a frequency control signal for controlling the oscillation frequency of the receiver-side master clock. A frequency error estimating means for generating, a D / A converting means for digital / analog converting the frequency control signal, a filter means for removing high frequency components from an output of the D / A converting means, and an output of the filter means. Or a voltage-controlled oscillator that generates the receiver-side master clock whose oscillation frequency has been corrected. Alternatively, in place of the D / A conversion means, the filter means, and the voltage-controlled oscillator, a digitally-controlled oscillator that generates the receiver-side master clock whose oscillation frequency is corrected using the frequency control signal is provided. This makes it possible to automatically correct the frequency deviation between the transmitter and the receiver with a simple circuit without significantly increasing the frequency of the master clock to increase the number of oversampling and improve the error rate. Master clock can be obtained.

By using the automatic frequency compensator having such a configuration for the receiving device and further using it for the communication device, it is possible to suppress the deterioration of the error rate without lowering the transmission efficiency. And a communication device.

In addition, such a configuration (Embodiment 1)
1 and FIG. 2 of (Embodiment 2), it is possible to obtain a receiving device and a communication device with reduced power consumption in addition to the above effects.

[0080]

As described above, according to the present invention, it is possible to reduce the power consumption of a receiving apparatus and a communication apparatus using the same by switching the number of samplings and turning on / off a clock recovery operation. Further, by automatically correcting the frequency deviation between the transmitting and receiving devices with a simple circuit, it is possible to suppress the deterioration of the error rate without lowering the transmission efficiency and without significantly increasing the frequency of the master clock.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a receiving apparatus according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a receiving apparatus according to an embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of an automatic frequency correction device according to one embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of an automatic frequency correction device according to one embodiment of the present invention.

FIG. 5 is a block diagram showing a configuration of a phase error detection circuit according to one embodiment of the present invention.

FIG. 6 is a block diagram showing a configuration of a frequency error estimating circuit according to one embodiment of the present invention;

[Invention of sign]

 102, 103 A / D converter 106 Phase converter 108 Delayer 110 Adder 111 Received signal after baseband delay detection 112 Data identification timing reference signal generation circuit 113 Data identification timing reference signal 114 Data identification timing signal generation circuit 115 Data Identification timing signal 116 Circuit operation control signal generator 117 Circuit operation control signal 118 Automatic frequency corrector 119 Master clock 120 Sampling clock switch 121 Sampling clock 122 Clock regeneration circuit 123 Symbol clock 124 Bit clock 125 Judge 126 Receive data 200 Channel decoder Reference Signs List 201 Frame synchronization signal 202 Edge generation circuit 203 Edge signal 300 Phase error detection circuit 301 Phase error signal 302 Frequency error estimation Circuit 303 Frequency control signal 304 D / A converter 305 Analog signal 306 LPF 307 Control voltage signal 308 VCO 400 Digitally controlled oscillator 500 Counter 501 Counter value 502 Counter value judgment device 503 Counter judgment value 504 Delay device 505 Previous counter judgment Value 506 Subtractor 600 Weighting circuit 601 Weighting signal 602 Frequency control signal generator

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Kentoku Kunieda 3-10-1, Higashi-Mita, Tama-ku, Kawasaki City, Kanagawa Prefecture Inside Matsushita Giken Co., Ltd. (72) Inventor Yuri Yamamoto 3-chome, Higashi-Mita, Tama-ku, Kawasaki City, Kanagawa Prefecture No. 10 No. 1 Matsushita Giken Co., Ltd. (72) Inventor Morikazu Sagawa 3-10-1, Higashi-Mita, Tama-ku, Kawasaki City, Kanagawa Prefecture F-term in Matsushita Giken Co., Ltd. 5K067 AA23 AA43 DD25 EE02 EE68

Claims (15)

[Claims] 1. A data identification timing signal generating means for detecting a preamble signal from a received signal and generating a data identification timing signal indicating the detection timing, and using the data identification timing signal to determine when the preamble signal is received Circuit operation control signal generation means for generating a control signal for switching a circuit operation between when a signal other than the above is received, and a sampling clock switch for generating a sampling clock signal in which the number of samples of the reception signal is switched based on the control signal And a receiver. 2. A clock recovery unit for recovering a clock for determining received data using a data identification timing signal, wherein the clock recovery unit turns on / off the clock recovery operation based on a control signal. The receiving device according to claim 1, wherein: The control signal is a binary digital signal, and the sampling clock switching means switches the sampling clock by switching the value between when the preamble signal is received and when the other signal is received. 3. The receiving apparatus according to claim 2, wherein a signal is generated and used as an enable signal of a clock recovery operation for a clock recovery unit. 4. An edge for inputting a frame synchronization signal generated using received data, detecting an edge thereof, and using the edge to generate an edge signal indicating reception timing of a preamble signal included in the received signal. Generating means, using the edge signal, a circuit operation control signal generating means for generating a control signal for switching a circuit operation between the time of receiving the preamble signal and the time of receiving other signals, based on the control signal A sampling clock switching means for generating a sampling clock signal in which the number of samplings of the reception signal is switched. 5. A data identification timing signal generating means for detecting a preamble signal from a received signal and generating a data identification timing signal indicating the detection timing, and using the data identification timing signal to reproduce a clock for determining received data. 5. The receiving apparatus according to claim 4, further comprising clock recovery means for performing, wherein the clock recovery means turns on / off the clock recovery operation based on a control signal. 6. The control signal is a binary digital signal, and the sampling clock switching means switches the sampling clock by switching the value between when the preamble signal is received and when the other signal is received. 6. The receiving apparatus according to claim 5, wherein a signal is generated and used as an enable signal of a clock recovery operation for a clock recovery unit. 7. A phase error detection means for inputting a timing signal generated using a trigger pulse signal and detecting a phase error using the timing signal and a past timing signal, and transmitting using the phase error. Estimate the frequency difference between the receiver side master clock and the receiver side master clock,
Frequency error estimating means for generating a frequency control signal for controlling the oscillation frequency of the receiver-side master clock; D / A converting means for digital / analog converting the frequency control signal; and an output from the D / A converting means. An automatic frequency correction apparatus comprising: filter means for removing high-frequency components; and a voltage-controlled oscillator for generating the receiver-side master clock whose oscillation frequency has been corrected using the output of the filter means. 8. A phase error detection means for inputting a timing signal generated using a trigger pulse signal and detecting a phase error using the timing signal and a past timing signal, and transmitting using the phase error. Estimate the frequency difference between the receiver side master clock and the receiver side master clock,
Frequency error estimating means for generating a frequency control signal for controlling the oscillation frequency of the receiver-side master clock; and a digitally controlled oscillator for generating the receiver-side master clock whose oscillation frequency has been corrected using the frequency control signal. An automatic frequency correction device, comprising: 9. The phase error detecting means counts the master clock on the receiver side up to a preset oversampling number at the time of receiving a preamble signal, thereafter returns the count value to an initial value, and counts up to the oversampling number again. A counter that repeats the above, a counter value determiner that reads the count value of the counter at the timing of all or part of the timing signal, and calculates the difference between the count value and the count value read at a previous timing as a phase error. The automatic frequency correction device according to claim 7, further comprising a subtractor that performs the subtraction. 10. A frequency error estimating means for estimating a frequency shift based on a phase error and setting a weighting amount, and a frequency control for controlling an oscillation frequency of a receiver-side master clock using the weighting amount. 10. The automatic frequency correction device according to claim 7, further comprising a frequency control signal generation unit that generates a signal. 11. The timing signal according to claim 7, wherein the timing signal is a data identification timing signal generated using a trigger pulse signal generated in synchronization with a detection timing of a preamble signal detected from a received signal.
The automatic frequency correction device according to any one of the above. 12. A timing signal detects an edge from a frame synchronization signal which is a trigger pulse signal generated in synchronization with a frame interval in received data, and uses the edge to detect a reception timing of a preamble signal included in the received signal. 11. The automatic frequency correction device according to claim 7, wherein the edge signal is an edge signal generated as follows. 13. The receiver-side master clock having the automatic frequency correction device according to claim 11, wherein the data identification timing signal generated by the data identification timing signal generation means is input as a timing signal. 4. The receiving device according to claim 1, wherein the receiving device is used as a master clock of a digital unit. 14. The automatic frequency correction device according to claim 12, wherein the edge signal generated by the edge generation means is input as a timing signal, and the receiver-side master clock output from the automatic frequency correction device is used as a master of the digital unit. The receiving device according to any one of claims 4 to 6, wherein the receiving device is used as a clock. 15. A communication device comprising the receiving device according to claim 1.