JP2000048131A - Method for testing ic card and device therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an IC card testing technique for reducing the data transmitting time, and for speeding up test by reducing data transfer between a tester and an IC card to the minimum. SOLUTION: At the time of data writing test to the EEPROM of a non- contact or contact type IC card, a writing data generation program and a command are transmitted from an IC card tester to the IC card (603). The IC card analyzes the command (606), and operates the command processing of the data writing test (607), and repeats data writing/reading/comparison judgment from a start address to an end address (608-613), and transmits only a final test result to an IC card tester (614). The IC card tester integrally judges the writing function test of the EEPROM based on the final rest result (616).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test technology for an IC card, and more particularly, to a distributed architecture capable of performing a high-speed test by greatly reducing data transfer time, a parallel simultaneous test, and a multiple simultaneous test. The present invention relates to a technique which is effective when applied to an IC card testing method and apparatus.

[0002]

2. Description of the Related Art For example, as a technique studied by the present inventor, an IC card is a card having the same shape as a card with a magnetic stripe, such as a credit card and a bank cash card, which are now widely used in society. inside,
A portable information storage medium that incorporates a CPU and a memory and utilizes the latest technology suitable for the advanced information society is expected to develop in the future. This IC card is C
Under the control of a PU control program, information can be exchanged with an external device through a contact-type contact terminal or a non-contact-type antenna coil. In addition, the built-in memory is controlled so as to be accessed only when processing is performed in a certain procedure for security.

Since such an IC card has various and various functions, a test before shipment is important. For example, regarding the test method of IC card,
JP-A-5-108905, JP-A-3-90983
And the like. The technique disclosed in Japanese Patent Application Laid-Open No. Hei 5-108905 relates to a test method for testing a plurality of IC cards simultaneously.
A write test to M is performed at the same time. Also,
The technique disclosed in JP-A-3-90983 relates to a test apparatus for providing a plurality of test units and simultaneously testing different types of IC cards, and constitutes a plurality of test groups which can be independently tested by a plurality of test boards. Things.

[0004]

The inventors of the present invention have studied the test method for an IC card as described above, and have found the following.

The techniques described in the above-mentioned Japanese Patent Application Laid-Open Nos. 5-108905 and 3-90983 test a plurality of IC cards using one tester or one system controller, and thus the test time is reduced. In most cases, the data transfer time between the tester or the system controller and the IC card is more than the test time of the IC card. That is, it is considered that the repetition of the transmission of the test data and the reception of the test result to the IC card occupies most of the test time.

For example, the technology described in the above publication is
It is considered that the test is performed in the processing sequence as shown in FIG. As shown in FIG. 11, the address, data, and command are serially transferred from the tester to the IC card, and the IC card that has received the data analyzes the command, performs a data write test for command processing, and returns the test result. Send to tester. Thereafter, similarly, the transmission of the test result by the command processing is repeated from the serial transfer of the address, data, and command, so that the test time is increased.

Accordingly, an object of the present invention is to focus on the data transfer time between a tester and an IC card, minimize the data transfer between the tester and the IC card, reduce the data transfer time, and increase the speed of the test. It is an object of the present invention to provide an IC card test method and apparatus capable of realizing the IC card.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0009]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, in the IC card test method according to the present invention, a test command and a test data generation program are transmitted to the IC card, the IC card analyzes the test command, and stores the test command in the internal memory based on the test data generation program. From the start address to the end address, a functional test such as a data write test / read test is repeatedly performed, and only the final comparison / judgment result is returned from the IC card. It has each step of comprehensively determining the function test of the memory.

In particular, a parallel / simultaneous test method of a data write verify test of an EEPROM and other tests such as a CPU operation test, a RAM / ROM data rewrite / read function test, a floating operation unit function test, and a test of a plurality of IC cards Output the result synchronously,
In this method, a simultaneous test method for a large number of IC cards based on synchronization determination is employed.

The test apparatus for an IC card according to the present invention includes a transmitting means for transmitting a test command and a test data generation program to the IC card, an analysis of the test command, and a data writing test based on the test data generation program. / Receiving means for receiving a final comparison / determination result from the IC card by repeating a functional test such as a read test, and determining means for comprehensively determining a functional test of the internal memory of the IC card based on the final comparison / determination result Things. In particular, the transmitting means, the receiving means, and the determining means comprise a plurality of sets which can operate independently.

According to the test method and apparatus for the IC card, after transmitting the test data generation program from the tester, the IC card performs a functional test such as a data write test / read test from the start address to the end address. By repeatedly returning only the final comparison determination result, data transfer between the tester and the IC card can be minimized and the data transfer time can be reduced, so that the test can be speeded up. .

In particular, since the data write verify test and other tests can be performed simultaneously in parallel,
The test efficiency can be improved. Also, multiple ICs
Since a large number of cards can be tested simultaneously by the synchronization determination, the test efficiency can be similarly improved.

[0015]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, the same members are denoted by the same reference numerals, and the description thereof will not be repeated.

FIG. 1 is an explanatory view showing a schematic structure of an IC card according to an embodiment of the present invention, and FIG.
FIG. 3 is a configuration diagram showing an IC card tester, FIG. 4 is a configuration diagram showing software of the IC card tester, FIG. 5 is an explanatory diagram showing a connection configuration between the IC card tester and the IC card, 6 is a flowchart showing the test processing of the IC card, FIG. 7 is a timing chart showing the test processing, FIG. 8 is an explanatory view showing the connection configuration of the IC card tester and the IC card at the time of the parallel simultaneous test, and FIG. 9 is an EEPROM. FIG. 10 is a timing chart showing a parallel simultaneous test with a write verify test, and FIG. 10 is an explanatory diagram showing a connection configuration at the time of simultaneous testing of a plurality of IC card testers and IC cards.

First, an example of a schematic structure of the IC card according to the present embodiment will be described with reference to FIG. FIG. 1A is a non-contact type IC card capable of exchanging information without contacting an external device, and FIG. 1B is a contact type I card capable of exchanging information by contacting an external device.
C cards are shown. In the non-contact type IC card, an LSI chip 2 and an antenna coil 3 electrically connected to the LSI chip 2 are incorporated in a plastic card 1. On the other hand, in a contact type IC card, an LSI chip 2 and a contact terminal 4 electrically connected to the LSI chip 2 are incorporated in a plastic card 1. The shape of this IC card is, for example, about 54 mm in length, about 85 mm in width, and about 0.25 to 0.8 mm in thickness.

An example of the internal configuration of this IC card is, as shown in FIG. 2, for example, a CPU 11 for controlling the entire control inside a chip 2, and a read-only memory for storing programs and data. A ROM 12, a writable / readable RAM 13, and an electrically erasable / rewritable EEPROM 14, an arithmetic unit 15 for performing arithmetic processing, and an interface 16 for controlling input / output with the outside are provided. Data transfer is possible. The data transfer between the chip 2 and the external device is performed by radio waves from the antenna coil 3 through the interface 16 inside the chip 2 and, in the case of the non-contact type, through the modulation / demodulation circuit 17 under the control of a control program by the CPU 11. On the other hand, in the case of the contact type, the contact is performed by the contact of the contact terminal 4. ROM12, R
Internal memories such as the AM 13 and the EEPROM 14 are controlled so as to be accessed only when processing is performed according to a certain procedure in order to protect data.

The test contents of the IC card include a DC test and various margin tests, and an IC card function operation test (AC function test). The DC test and various margin tests include a margin test for power supply voltage fluctuation, a margin test for timing fluctuation, an input signal voltage level margin test, an output voltage level test, open / short of each terminal, power supply current and leak current measurement, and the like. As the IC card function operation test, the CPU in the card
There are an operation test, a RAM and ROM data rewriting / reading function test, an EEPROM data writing / reading function test, and an IC card floating arithmetic unit function test.

Next, an example of the configuration of the IC card tester will be described with reference to FIGS. FIG. 3 shows the configuration of the IC card tester, and FIG. 4 shows the software configuration. This IC card tester shows a configuration example applied to a contact type IC card. However, a non-contact type IC card is almost the same except that the input / output configuration with the IC card tester is different.

The IC card tester has functions of a tester, a reader / writer, a card issuing device, etc., and as shown in FIG. 3, a host CPU unit 20 for developing a test condition program and managing test data, and a test execution unit. And a tester main unit 30 for executing control and test plan / debugging, and are connected by a LAN. Host CP
The U unit 20 is connected with a printer 21 for print output, an MO drive 22 for auxiliary storage, and the like, so that a user can create a test plan and manage measurement results. The tester main unit 30 is connected to each corresponding IC card 33 via a common contact probe unit 32 from each measurement control unit 31 which can operate independently corresponding to the device under test. Can be increased or decreased (for example, up to about 32 sheets), so that a test system can be constructed according to the performance before and after the testing process.

The tester main body 30 includes a satellite CPU 3
4, a handler i / f 35, a system power supply 36, a safety circuit 37, and a plurality of measurement control units 31. Each measurement control unit 31 is provided with a controller 38, a device power supply 39, an AC measurement unit 40, a DC measurement unit 41, an MPX 42, a test head 43, and the like. Tests are possible. Hereinafter, each component will be described in detail.

The satellite CPU 34 transfers test conditions, reads test results, and controls handlers to a plurality of measurement control units 31. Also, test plan debugging can be executed from the satellite CPU 34.

The handler i / f 35 is a unit for controlling a handler of the IC card 33 or a soft COB handler. Perform parallel communication.

The controller 38 sends a device power supply 39 to the tester hardware according to the user-written test conditions.
Voltage setting, condition setting of AC measuring unit 40, DC measuring unit 4
Perform the condition setting of 1 and pin assignment of various conditions.
The test of the IC card 33 is executed. It also manages the measurement results.

The device power supply 39 sets the voltage level to be applied to the power supply terminal of the IC card 33,
It has a function of measuring a power supply current flowing through the card 33.

The AC measuring section 40 sets a clock frequency and a duty ratio to be applied to the IC card 33, sets an output voltage level of the driver, a comparator level, and the like. Perform the test.

The DC measuring unit 41 is a unit that performs open / short check of input / output pins of the IC card 33 and measures leak current.

The MPX 42 has a function of allocating the AC measuring section 40 and the DC measuring section 41 to predetermined pins of the IC card 33 by relay switching.

The test head 43 has a signal driver applied to the IC card 33, an output signal judgment comparator, and the like. In addition, a virtual ground that minimizes measurement errors due to cable loss is supplied to improve measurement accuracy.

In this IC card tester, the host C
As shown in FIG. 4, the software of the PU unit 20 includes a test plan editor 51, a test plan compiler 52,
It is composed of data communication software 53, data output display software 54, system operation management software 55, and the like. The software of the satellite CPU 34 includes a measurement control system 61, an online debugger 62, test condition and data communication software 63, a histogram utility 64, a calibration software 65, and the like. Host CPU unit 20 and satellite CPU 3
The four are connected by a network (LAN). Hereinafter, each software will be described in detail.

The test plan editor 51 is an editor for creating test conditions, and can directly activate the test plan compiler 52 from the test plan editor 51. If a condition description error or the like occurs in the compilation result, the cursor is moved to a predetermined error occurrence location and the description error location is indicated. As a result, a test plan can be efficiently created.

The test plan compiler 52 translates the test plan created by the test plan editor 51 into an object that can be executed by the tester. The test plan compiler 52 also generates detailed information for test plan debugging.

The software of the data communication software 53 is
Transfers (assigns) test plans, reads measurement results, and sets and issues various other functions.

The software of the data output display software 54 converts the test result read by the data communication into a CRT,
Output to printer, HD, etc. In addition, it is possible to output a test result report (lot number, worker name, test start time, end time, total number of tests, number of good / defective products, number of defects by test number, etc.).

The software of the system operation management software 55 performs security management of the apparatus by using a password or the like.

The measurement control system 61 controls the handler and controls the controller 38 (test execution unit).
Controls test plan execution. With this software, the measurement results of the plurality of measurement control units 31 are managed and transmitted to the host CPU unit 20 as needed. The test status is output to the liquid crystal display panel of the tester main unit 30, and the number of tests, the number of good / defective products, and the like up to the present can be viewed.

The online debugger 62 is a test plan debugging tool. Functions include execution of a test plan line by line, test stop (pause) at a source line number or a test number of a predetermined test plan, change of test conditions, DC test, execution from an AC test keyboard, measurement result Display and the like can be performed. Thus, the test plan can be efficiently debugged. It can also be used as a failure analysis tool.

The software of the data communication software 63 is
The test plan (test conditions) received from the host CPU unit 20 is transmitted to the controller 38. Also, the measurement results received from each controller 38 are put together and the host CPU
Or to the unit 20.

The histogram utility 64 obtains the distribution of measured data for each DC test for a predetermined production lot of the IC card 33. By using this, the user can use this data as an index for process control.

The software of the calibration software 65 is used when calibrating the hardware of the system. This IC card tester
Since the measurement control unit 31 is compatible with maintenance by replacing the unit, this calibration is performed when the unit is replaced.

The test process of the IC card 33 is performed using the IC card tester configured as described above. This test process is included in the IC card manufacturing process 0th issue process, the IC card inspection process, the 1st issue process, the 2nd issue process, and the like. Tests are performed.

The IC card manufacturing process 0th order issuance step is a step of checking hardware components. The IC card 33 checks the normal operation of the IC card 33,
Processing such as initialization of the card 33, creation of an MF, writing of a card identifier (manufacturer, version information, etc.), writing of a card ID, writing of a cryptographic function, and a loop test are performed.

In the IC card inspection step, reading of the card ID is repeatedly performed as a screening test on the IC card 33 on which the manufacturing process is completed. The card ID written by writing the card ID of the IC card manufacturing processing function is used for the test.

The primary issuance processing step is a step of performing an operational check, and the IC card 33 that has been manufactured and inspected has been completed.
Write basic information, confirm basic information,
Processing such as F, EF, key creation, data writing, data confirmation, and security setting is performed.

The secondary issuance processing step is a step of writing individual information such as a user ID. This allows
After the DC test, various margin tests, and functional operation tests of the IC card 33 are completed, the IC card 33 in which individual information and the like are written is completed, and can be issued to the user.

Next, an example of a connection configuration between the IC card tester and the IC card 33 in FIG. 5, an example of a test processing flow of the IC card 33 in FIG. 6, and an example of a test processing timing in FIG. A description will be given of a data write (read) test to the EEPROM 14 in the manufacturing process 0th order issuing step. This writing test is performed in the parallel connection configuration of the IC card tester and the IC card 33 shown in FIG. 3, and here shows a test example by connecting one IC card 33 as shown in FIG.

(1) The IC card tester uses the clock signal C
After setting test conditions such as LK and power supply voltage VCC (step 601), a write start address and a write end address are set (step 602). further,
A write data generation program and a command are transmitted to the IC card 33 (step 603). Here, the processing shifts to the program transmitted by the trigger (step 604).

(2) The operation of the IC card 33 starts when the test conditions of the IC card tester are set, and the IC card 33 waits in a command reception waiting state (step 605). At this time, for example, the control program stored in the ROM 12 is started under the control of the CPU 11, and the write data generation program transmitted from the IC card tester is transmitted to the EEPROM.
It is temporarily stored in M14.

(3) Upon receiving the command, the IC card 33 analyzes the command (step 606) and performs a command process for a data write test (step 60).
7). Based on the test data generation program, a write address is set (step 608), and write data for this set address is generated to generate an EEPROM.
Write to M14 (step 609).

(4) The IC card 33 reads the written data (step 610), and compares the read data with an expected value (step 611).
If the comparison results match, the address is incremented (step 612), and it is determined whether or not the address is the end address (step 613).
The process from 08 is repeated. On the other hand, if the comparison results do not match, the process proceeds to transmitting the final test result.

(5) In the IC card 33, data writing / reading / reading / writing from the start address to the end address is performed.
When the comparison is completed, only the final test result is transmitted to the IC card tester (step 614). The final test result is only information on the match / mismatch with the expected value, and this information is returned from the IC card 33.

(6) When the IC card tester receives the final test result from the reception waiting state (step 615), the EEPROM 14 tests the EEPROM 14 based on the final test result.
Comprehensive judgment of the writing function test is performed (step 61)
6). By this comprehensive judgment, if the test results match, it is judged as a good product, and if not, it is judged as a defective product. As described above, a test of writing data to the EEPROM 14 inside the IC card 33 can be performed.

Similarly, in a data read test from the EEPROM 14, an IC card
Only a read data generation program and a command are transmitted to the C card 33, and thereafter the IC card 3
In step 3, the data read / comparison determination from the start address to the end address is repeated, and only the final test result is transmitted to the IC card tester, whereby the EE
A data read test from the PROM 14 can be performed.

In the case of this data write / read test, the timing of the test processing is as shown in FIG.
For example, the test on pages 1 to 256 is performed only by transferring the test data generation program and command conditions and the final test result transfer only to the IC card tester and the IC card 33.
What should be done between and. On the other hand, in the processing flow of FIG. 11, as shown in FIG.
Since it is necessary to transfer the conditions of the address, data and command for each of the 56 pages, and to transfer the check result each time, the improvement has been desired as a problem in serial transfer.

In particular, the write / read data generation program of the IC card tester, which is a feature of the present embodiment, is erased when the power of the IC card tester is turned off. Further, compared with the case of using an IC card test in which a BIST function or the like is incorporated in a device, since the algorithm is implemented by software, it is easy to modify a program and to easily cope with a version upgrade such as improvement.

Next, an example of a connection configuration at the time of a parallel simultaneous test of the IC card tester and the IC card 33 in FIG.
A parallel simultaneous test method of the write verify test of the EEPROM 14 and another test will be described with an example of the timing of the write verify test of the EPROM 14.

This write verify test is a test for verifying whether the contents of the EEPROM 14 built in the IC card 33 are correct. Normally, the contents of the EEPROM 14 cannot be output to the outside due to security. On the contrary, the contents are transmitted by transmitting correct data from the outside, and are compared and determined inside the IC card 33. In this case, the data in the EEPROM 14 is about 10 to 16 kB, and it takes a long time for data transfer, which is an issue for the test.

For example, as shown in FIG.
In the write verify test of No. 4, the waiting time of the comparison / determination processing performed in synchronization with the reception of the reception flag for the control signal is effectively used. That is, the CPU in the IC card 33 is in an idling state during a period other than the comparison and determination processing, and by using this period to perform another test, the test efficiency can be improved. Specifically, during this time, it is possible to carry out functional tests of each part of the IC card 33, such as a CPU operation test, a RAM / ROM data rewriting / reading function test, and a floating operation unit function test.

Next, a method for simultaneously testing a plurality of IC cards at the time of a test for writing data to the EEPROM 14 will be described with reference to an example of a connection configuration for simultaneous testing of a plurality of IC cards with the IC card 33 shown in FIG.

Of the tests of a large number of IC cards 33 connected in parallel, the data write test of the EEPROM 14 varies in data write time for each device. For this reason, in the result response from each IC card 33, a timing difference occurs between the devices, which hinders the simultaneous processing of many devices. Therefore, in this embodiment, means for changing the level of the input / output pin and notifying the IC card tester of the end of data writing is provided in each IC card 3.
3, a method of monitoring the level change of input / output pins with an IC card tester to control a test processing sequence, and adopting a method of synchronizing devices by software by a result request command from the IC card tester. Can be realized by:

For example, in each IC card 33, the level of the input / output line is changed from the intermediate level to the high level at the same time when the data writing is completed. The IC card tester monitors the input / output lines and senses the flag from the intermediate level to the high level. Then, when a predetermined time including a margin for the response has elapsed, or when responses have been returned from all devices, the processing shifts to the determination processing.

Further, a test result request command is transmitted from the IC card tester to each IC card 33. Each IC card 33 transmits the test result to the IC card tester in synchronization with the clock signal. Then, the transmitted result data is subjected to simultaneous determination processing by the IC card tester. As described above, since the IC cards 33 can be individually tested irrespective of the test speed, the soft wait time is eliminated. As a result, a parallel test can be efficiently realized for many devices at the same time.

Therefore, according to the test technique of the IC card 33 of the present embodiment, the controller 38 is provided inside and the IC card tester having each measurement control unit 31 capable of performing independent and parallel tests is provided. The following operational effects can be obtained by conducting a test using

(1) From the IC card tester, the IC card 3
After sending the test data generation program to
The IC card 33 repeats the data write test / read test from the start address to the end address, and returns only the final comparison / determination result.
Since the data transfer time between the C card tester and the IC card 33 can be minimized and the data transfer time can be reduced, the test can be sped up.

(2) In the write verify test of the EEPROM 14, the waiting time of the comparison / determination processing is effectively used, and other functional tests such as the CPU operation test are simultaneously performed at a time other than the comparison / determination processing. Therefore, the test efficiency can be improved.

(3) In the IC card tester, the test processing sequence is controlled by monitoring the level change of the input / output pins of each IC card 33, and the result data is determined in synchronization with the clock signal. Since a large number of IC cards 33 can be tested simultaneously by the synchronization determination, the test efficiency can be improved as in the case of the parallel simultaneous test.

Although the invention made by the inventor has been specifically described based on the embodiment, the present invention is not limited to the embodiment, and various modifications may be made without departing from the gist of the invention. It goes without saying that it is possible. For example, the EEPROM inside the IC card is
However, the present invention is not limited to this, and can be applied to other erasable / rewritable memories such as a flash EEPROM.

[0069]

Advantageous effects obtained by typical ones of the inventions disclosed in the present application will be briefly described.
It is as follows.

(1) After transmitting the test data generation program from the tester, the IC card repeats functional tests such as data write test / read test from the start address to the end address, and returns only the final comparison / judgment result. By doing so, the data transfer time between the tester and the IC card can be minimized and the data transfer time can be reduced, so that the test can be sped up.

(2) Data write verify test of EEPROM 14, CPU operation test, RAM and ROM
Since other tests such as a data rewrite / read function test and a floating operation unit function test can be performed simultaneously in parallel, it is possible to improve test efficiency.

(3) Since the test results of a plurality of IC cards can be output in synchronization and a large number of IC cards can be tested simultaneously,
Test efficiency can be improved.

(4) According to the above (1) to (3), a high-speed test by greatly reducing the data transfer time, a parallel simultaneous test,
By adopting the simultaneous test of many devices, it is possible to realize a high-speed test and an improvement in efficiency.

[Brief description of the drawings]

FIGS. 1A and 1B are explanatory views showing a schematic structure of an IC card according to an embodiment of the present invention.

FIG. 2 is an internal configuration diagram showing an IC card according to an embodiment of the present invention.

FIG. 3 is a configuration diagram showing an IC card tester in one embodiment of the present invention.

FIG. 4 is a configuration diagram showing software of an IC card tester in one embodiment of the present invention.

FIG. 5 is an explanatory diagram showing a connection configuration between an IC card tester and an IC card in one embodiment of the present invention.

FIG. 6 is a flowchart showing a test process of an IC card in one embodiment of the present invention.

FIG. 7 is a timing chart showing a test process of the IC card according to the embodiment of the present invention.

FIG. 8 is an explanatory diagram showing a connection configuration at the time of a parallel simultaneous test of an IC card tester and an IC card in one embodiment of the present invention.

FIG. 9 illustrates an embodiment of an EEPROM.
FIG. 9 is a timing chart showing a parallel simultaneous test with a write verify test of FIG.

FIG. 10 is an explanatory diagram showing a connection configuration at the time of simultaneous testing of a plurality of IC card testers and IC cards in one embodiment of the present invention.

FIG. 11 is a flowchart showing a test process of an IC card as a premise of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Plastic card 2 LSI chip 3 Antenna coil 4 Contact terminal 11 CPU 12 ROM 13 RAM 14 EEPROM 15 Operation unit 16 Interface 17 Modulation / demodulation circuit 20 Host CPU unit 21 Printer 22 MO drive 30 Tester main unit 31, Measurement control unit 32 Contact Probe unit 33 IC card 34 Satellite CPU 35 Handler i / f 36 System power supply 37 Safety circuit 38 Controller 39 Device power supply 40 AC measurement unit 41 DC measurement unit 42 MPX 43 Test head 51 Test plan editor 52 Test plan compiler 53 Data communication Software 54 Data output display software 55 System operation management software 61 Measurement control system 62 Online debugger 63 Data communication software 64 Histogram utility 65 calibration software

 ────────────────────────────────────────────────── ─── Continuation of the front page (72) Hideaki Mayuzumi, Inventor 3-3-2 Fujibashi, Ome-shi, Tokyo F-term in Hitachi Tokyo Electronics Co., Ltd. 5B058 CA23 KA28 5L106 AA00 AA07 AA10 FF01

Claims (7)

[Claims] An IC for performing an electrical characteristic test of an IC card
A method of testing a card, comprising transmitting a test command and a test data generation program to the IC card, wherein the IC card analyzes the test command,
Repeating the function test from the start address to the end address for the internal memory based on the test data generation program, returning only the final comparison / determination result from the IC card; A step of comprehensively determining a function test of an internal memory of the IC card based on the determination result. 2. The method for testing an IC card according to claim 1, wherein the step of repeatedly performing the function test includes the step of generating data corresponding to a set address based on the test data generation program. A step of writing the generated data to the internal memory of the IC card; a step of reading the written data; a step of comparing the read data with an expected value; and incrementing the set address when the comparison result matches. And repeating the processing from the step of generating the data from the start address to the end address to perform a write function test of the internal memory of the IC card.
Test method for C card. 3. The IC card test method according to claim 1, wherein the step of repeatedly performing the function test includes a step of reading data corresponding to a set address based on the test data generation program, and the step of reading the data. Comparing the data with the expected value, and incrementing the set address when the comparison result matches,
A test method for an IC card, comprising repeating a process from a step of reading the data from a start address to an end address, and performing a read function test of an internal memory of the IC card. 4. The IC card test method according to claim 1, wherein the electrical characteristics test of the IC card includes a CPU operation test, a RAM and ROM data rewrite / read function test, and an EEPROM data write / read function test. And a parallel operation test of the EEPROM data write verification test and another test including a floating operation unit function test.
Test method for C card. 5. The method for testing an IC card according to claim 1, wherein said IC card has a plurality of IC cards, and test results of said plurality of IC cards are output in synchronization with each other.
IC for performing simultaneous testing of multiple C cards
Card testing method. 6. An IC for performing an electrical characteristic test of an IC card.
A card testing device, comprising: transmitting means for transmitting a test command and a test data generating program to the IC card; and analyzing the test command and repeating the functional test based on the test data generating program. An IC card test apparatus, comprising: receiving means for receiving a final comparison determination result from the IC card; and determination means for comprehensively determining a functional test of an internal memory of the IC card based on the final comparison determination result. 7. The IC card test apparatus according to claim 6, wherein said transmitting means, said receiving means, and said judging means comprise a plurality of independently operable sets. apparatus.