JP2000047624A - Driving circuit for display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To decrease the number of necessary capacitors if when a DC source voltage is set to a high boosting ratio when boosted by making use of a charge pump circuit. SOLUTION: A 1st boosting circuit 4 which has a charge pump circuit composed of diodes D11 to D14, capacitors C11 to C14, and semiconductor switching elements T11 to T14 boosts the output voltage of a battery 2 by about four times and outputs the boosted voltage. A 2nd boosting circuit which has a charge pump circuit composed of diodes D21 to D23, capacitors C21 to C23, semiconductor switching elements T21 to T26, etc., boosts the output voltage of the 1st boosting circuit 4 by about three times and outputs the resulting voltage. Consequently, the voltage of about 12 times as high as the output voltage of the battery 2 is applied to a driving circuit part 6 for driving a display device 1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving circuit for a display device requiring a high driving voltage such as an EL display panel, and more particularly to a high-voltage semiconductor switching device in which a high-voltage output obtained by boosting a DC power supply voltage is used. The present invention relates to a drive circuit for a display device which is supplied to a display device through a drive circuit portion including elements.

[0002]

2. Description of the Related Art Since a relatively high drive voltage is required for driving an EL display panel, a booster circuit for boosting a power supply voltage in a battery-driven device such as a vehicle-mounted EL display panel. However, it is desirable to employ a transformerless structure for the booster circuit provided for such an application in order to reduce the overall size. For this reason, in the related art, it is conceivable to use a booster circuit using a charge pump circuit, which has a disadvantage that the fluctuation of the output voltage is relatively large, but has a great advantage that the integration into an IC is easy with a simple circuit configuration. In this case, the booster circuit can be incorporated in a driver IC for driving an EL display panel.

As a booster circuit utilizing such a charge pump circuit, for example, a booster circuit described in Japanese Patent Application Laid-Open No. 7-322604 is known. In the booster circuit described in this publication, a plurality of charge pump circuits each including a plurality of diodes and capacitors for boosting a power supply voltage in multiple stages are provided, and these are connected in parallel. A configuration in which a series connection switch means for selectively connecting each capacitor located in the final stage of the circuit in series is provided, and a sum voltage of a voltage generated in the final stage capacitor and a power supply voltage is output as a final boosted voltage. It has become.

[0004]

In the case of the above-described conventional booster circuit, the number of capacitors required increases in proportion to the increase of the boosting ratio. Therefore, when it is required to boost a power supply voltage of about 5 V to about 200 V or more, such as when a booster circuit is built in a driver IC for driving an EL display panel, an extremely large number of capacitors are required. There will be circumstances. As a result, there arises a problem that the size of the booster circuit increases, the size of the entire driver IC increases, and the manufacturing cost increases.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to increase the DC power supply voltage by using a charge pump circuit and to set a high boosting ratio. It is an object of the present invention to provide a drive circuit for a display device which can reduce the number of capacitors required even in such a case, and can realize a reduction in size and a reduction in manufacturing cost.

[0006]

To achieve the above object, the means described in claim 1 can be adopted. According to this means, the DC power supply voltage is boosted by the first booster circuit that forms a charge pump circuit by a plurality of diodes and capacitors, and a group of semiconductor switching elements for charging and discharging the capacitors, This first
The output voltage from the booster circuit is boosted by a second booster circuit comprising a charge pump circuit comprising a plurality of diodes and capacitors, and a group of high-voltage semiconductor switching elements for charging and discharging the capacitors. As a result, the output voltage is supplied to the display device through the drive circuit unit. At this time, M capacitors are provided in the charge pump circuit forming the first booster circuit, the boosting ratio thereof is set to about M times, and N charge pump circuits forming the second booster circuit are provided in the charge pump circuit. If a capacitor is provided and its boost ratio is set to about N times, the finally obtained output voltage will be about M × N times the DC power supply voltage. Accordingly, it is only necessary to provide (M + N) capacitors in order to obtain an output voltage that is about M × N times the DC power supply voltage. This reduces the number of capacitors required for setting a large boost ratio. it can. As a result, the overall size can be reduced, and the manufacturing cost can be reduced.

Further, as in the invention according to claim 2, the second
Is provided with a plurality of stages of a charge pump circuit composed of a plurality of diodes and capacitors and a group of high-voltage semiconductor switching elements for charging and discharging the capacitors, the high voltage The number of capacitors required to obtain an output can be further reduced.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) A first embodiment in which the present invention is applied to a driver IC for driving an EL display panel will be described below with reference to FIGS. In FIG. 1 showing a circuit configuration of a main part, an EL element 1a represented by an equivalent circuit is a position where a plurality of scanning electrodes and data electrodes intersect in a matrix type EL display panel 1 (corresponding to a display device according to the present invention). Therefore, there are actually a number corresponding to (the number of scanning electrodes × the number of data electrodes). Battery 2
A driver IC 3 supplied from a DC power supply according to the present invention is provided to supply a high voltage to the data electrode group or the scanning electrode group of the EL display panel 1. , The second booster circuit 5, the drive circuit section 6, a gate control circuit (not shown) for controlling the operation of the drive circuit 6, and the operation of the first booster circuit 4 and the second booster circuit 5 (Not shown) is integrated into a single chip on the same semiconductor substrate.

Although the number of the drive circuit units 6 is provided in accordance with the number of electrodes to which a voltage is applied, only one drive circuit unit is shown in FIG. 1 for convenience of explanation. Driver IC
Numeral 3 actually provides a device for driving the data electrodes of the EL display panel 1 and a device for driving the scanning electrodes of the EL display panel 1 separately.

The drive circuit section 6 includes a high voltage output section 7 and a voltage level conversion section 8. Specifically, the high-voltage output section 7 is provided between the power supply terminal + V and the ground terminal of the drive circuit section 6 and is a high-withstand-voltage P-channel MOS transistor 7a (corresponding to a high-withstand-voltage semiconductor switching element in the present invention: A high-breakdown-voltage N-channel MOS transistor 7b (corresponding to a high-breakdown-voltage semiconductor switching element in the present invention: hereinafter referred to as NMO).
(Referred to as an S transistor) are connected in series, and the PMOS transistor 7a and the NMOS transistor 7b have a push-pull configuration in which their common connection point is connected to the output terminal Q of the drive circuit unit 6. .

The voltage level converter 8 includes a voltage dividing circuit 8a of a resistive voltage dividing type comprising voltage dividing resistors R1 and R2 between a power supply terminal + V and a ground terminal, and a high withstand voltage type N channel M
An OS transistor 8b (corresponding to a high withstand voltage semiconductor switching element in the present invention; hereinafter, referred to as an NMOS transistor) is connected in series. When the NMOS transistor 8b is turned on, the output terminal of the voltage dividing circuit 8a ( A divided voltage signal is generated from a common connection point of the resistors R1 and R2) and is supplied to the PMOS transistor 7a as a gate signal. In this case, the voltage level of the divided signal is configured to be lower than the voltage of the power supply terminal + V by the gate threshold voltage of the PMOS transistor 7a or more.

The PMOS transistor 7a, NM
The OS transistors 7b and 8b are, for example, LDMOS
(Lateral Double-diffused MOS: Lateral double-diffused MOS
FET) which can obtain a sufficient withstand voltage. Further, the NM in the high voltage output unit 7
NM in OS transistor 7b and voltage level converter 8
The OS transistor 8b receives a clock signal CL07 output as a gate control signal from a gate control circuit (not shown).
And CL08 alternately turned on and off.

The first booster circuit 4 has the following configuration. That is, the first booster circuit 4 includes four diodes D11 to D14, capacitors C11 to C14, P-channel MOS transistors T11 and T12 (corresponding to a semiconductor switching element in the present invention, hereinafter referred to as a PMOS transistor), and N-channel MOS transistors T13, T
14 (corresponding to a semiconductor switching element in the present invention: hereinafter referred to as an NMOS transistor) constitute a charge pump circuit.

More specifically, the diodes D11 to D14 are connected in series between the input terminal 4a and the output terminal 4b of the first booster circuit 4 in the forward direction. The PMOS transistor T11 and the NMOS transistor T13 are connected in series between the input terminal 4a and the ground terminal to form a push-pull circuit 4c.
The S transistor T14 is connected in series between the input terminal 4a and the ground terminal to form a push-pull circuit 4d. Capacitors C11 to C13 function as pump capacitors and are set to the same capacitance Cx, respectively.
The capacitor C14 functions as a smoothing capacitor and has a larger capacity than the capacitors C11 to C13. These capacitors C11 to C14 are individually connected at one end to the cathodes of the corresponding diodes D11 to D14. The other end of each of the capacitors C11 and C13 is connected to the output terminal of the push-pull circuit 4d. The other end of the capacitor C12 is connected to the output terminal of the push-pull circuit 4c. The end is connected to the ground terminal.

The input terminal 4a of the first booster circuit 4 is
The battery 2 is connected to a positive terminal, and the negative terminal of the battery 2 is connected to a ground terminal. The PMOS transistor T in the push-pull circuit 4c
The NMOS transistor T13 and the NMOS transistor T13 are turned on / off by a clock signal CL11 from a clock control circuit (not shown), and the PMOS transistor T13 in the push-pull circuit 4d.
12 and the NMOS transistor T14 are turned on and off by a clock signal CL12 from the clock control circuit.

The second booster circuit 5 has the following configuration. That is, the second booster circuit 5 includes three diodes D21 to D23 and three capacitors C21 to C23, and high-breakdown-voltage P-channel MOS transistors T21 and T22 (corresponding to a high-breakdown-voltage semiconductor switching element according to the present invention: A charge pump circuit is constituted by a PMOS transistor) and high voltage N-channel MOS transistors T23 to T26 (corresponding to a high voltage semiconductor switching element in the present invention: hereinafter referred to as an NMOS transistor).

Specifically, the diodes D21 to D23 are serially connected in a forward direction between the input terminal 5a and the output terminal 5b of the second booster circuit 5. The PMOS transistor T21 and the NMOS transistor T24 are connected in series between the input terminal 5a and the ground terminal to form a push-pull circuit 5c.
The S transistor T26 is connected in series between the input terminal 5a and the ground terminal to form a push-pull circuit 5d.

The NMOS transistor T23 is connected to the PMO
The drain constitutes a voltage level conversion circuit 5e for turning on the S transistor T21. The drain is connected to the input terminal 5a via a series circuit of resistors R21 and R22, and the source is connected to the ground terminal. In this case, the common connection point of the resistors R21 and R22 is a PMOS transistor T21.
Connected to the gate. Note that this voltage level conversion circuit 5
e is a voltage of the level described below (first
When the NMOS transistor T23 is turned on in a state where the voltage stepped up by the step-up circuit 4 is applied, the voltage drop at the resistor R21 becomes equal to or higher than the gate threshold voltage level of the PMOS transistor T21. ing.

The NMOS transistor T25 is connected to the PMO
It constitutes a voltage level conversion circuit 5f for turning on the S transistor T22. The drain is connected to the input terminal 5a via a series circuit of resistors R23 and R24, and the source is connected to the ground terminal. In this case, the common connection point of the resistors R23 and R24 is a PMOS transistor T22.
Connected to the gate. Note that this voltage level conversion circuit 5
f is a voltage of the level described below (first
When the NMOS transistor T25 is turned on in a state where the voltage stepped up by the step-up circuit 4 is applied, the voltage drop at the resistor R23 becomes equal to or higher than the gate threshold voltage level of the PMOS transistor T22. ing.

The capacitors C21 and C22 function as pump capacitors and are set to have the same capacitance Cy, and the capacitor C23 functions as a smoothing capacitor and are set to have a larger capacity than the capacitors C21 and C22. Each of these capacitors C21 to C23 is individually connected to the cathode of the corresponding diode D21 to D23. The other end of the capacitor C21 is connected to the output terminal of the push-pull circuit 5d, the other end of the capacitor C22 is connected to the output terminal of the push-pull circuit 5c, and the other end of the capacitor C23 is grounded. Connected to terminal.

In this case, the second booster circuit 5 has an input terminal 5a connected to the output terminal 4b of the first booster circuit 4, and an output terminal connected to the power supply terminal + V of the drive circuit section 6.
Connected to. Further, each of the NMOS transistors T23 to T23
Reference numeral 26 is configured to be turned on and off by clock signals CL21 to CL24 from the clock control circuit (not shown).

The capacitance Cx of the capacitors C11 to C13, the capacitance Cy of the capacitors C21 and C22, the clock signal CL11,
CL12, frequency of CL21 to CL24 (clock frequency)
Is determined in consideration of the number of the capacitors, the output voltage and the output current from the second booster circuit 5, and the like.

Next, the operation of the circuit configuration of FIG. 1 will be described with reference to FIGS. FIG. 2 shows the clock signals CL11,
CL12 waveform and terminal voltage V of capacitors C11 to C14
FIG. 3 shows waveforms of clock signals CL21 to CL24 in the second booster circuit 5 and waveforms of terminal voltages V21 to V23 of capacitors C21 to C23.
Are the clock signals CL07 and CL08 in the drive circuit unit 6.
And the waveform of the output voltage Vz from the output terminal Q. In the following description, for convenience of explanation, the charge storage amounts of the capacitors C11 to C14 and C21 to C23 are set to zero in the initial state, and the forward voltage drops of the diodes D11 to D14 and D21 to D23 are ignored.

First, in the first booster circuit 4, when the output voltage Vo of the battery 2 is applied to one end of the capacitors C11 to C14 via the diodes D11 to D14, the clock signal CL12 is set to the "H" level. In response to the turning on of the NMOS transistor T14 in the push-pull circuit 4d, each of the capacitors C11 and C13
x × V0 [C] is charged. At this time, since the clock signal CL11 is at "L" level, the PMOS transistor T11 in the push-pull circuit 4c is turned on. Therefore, the capacitor C12 is not charged, and its charge storage amount remains zero.

From such a state, the clock signal CL1
1. After both CL12 have gone through the "L" level state,
When the clock signal CL11 is at "H" level and the clock signal CL
When the signal 12 goes to the “L” level, the push-pull circuit 4
Since the NMOS transistor T13 in c and the PMOS transistor T12 in the push-pull circuit 4d are turned on, the charges of the capacitors C11 and C13 are transferred to the capacitors C12 and C14 via the diodes D12 and D14, respectively. Thereafter, as the operation that the clock signals CL11 and CL12 alternately go to the “H” level as described above is repeated, the capacitors C11 to C1
2, capacitor C12 to capacitor C13, capacitor C1
Charges are sequentially transferred from 3 to the capacitor C14. As a result, as shown in FIG. 2, the terminal voltage V14 of the last-stage capacitor C14 is boosted to four times the output voltage V0 of the battery 2. Will be. The terminal voltage V14 thus boosted is applied to the input terminal 5a of the second booster circuit 5 through the output terminal 4b.

In the second booster circuit 5, the capacitor C
The first terminal is connected to one end of each of the first through the third through the diodes D21 through D23.
In the state where the output voltage V14 (= 4 × Vo) of the step-up circuit 4 is applied, as shown in FIG.
21 and CL24 are at "H" level, clock signals CL22 and CL
When the signal 23 goes to the "L" level, the NMOS transistor T26 in the push-pull circuit 5d is turned on by the clock signal CL24.
The charge of V14 [C] is charged. Further, the NMOS transistor T23 in the voltage level conversion circuit 5e is turned on by the clock signal CL21. At this time, the voltage level conversion circuit 5e is configured such that the voltage drop at the resistor R21 is equal to or higher than the gate threshold voltage level of the PMOS transistor T21 in the push-pull circuit 5c.
The PMOS transistor T21 is turned on in response to the turning on of the OS transistor T23. Therefore, the capacitor C22 is not charged, and its charge storage amount remains zero.

In this state, as shown in FIG. 3, when the clock signals CL21 and CL24 become "L" level and the clock signals CL22 and CL23 become "H" level, the NMOS transistor T24 in the push-pull circuit 5c Is turned on by the clock signal CL22, and in response to the NMOS transistor T25 in the voltage level conversion circuit 5f being turned on by the clock signal CL23, the PMOS transistor T22 in the push-pull circuit 5d is turned on. For this reason, the charge of the capacitor C21 is changed to the diode D22.
To the capacitor C22. Thereafter, in response to the clock signals CL21 to CL24 being output in the state shown in FIG.
2. Charges are sequentially transferred from the capacitor C22 to the capacitor C23.
23 is the output voltage V14 of the first booster circuit 4.
(Ie, 12 times the output voltage V0 of the battery 2). The terminal voltage V23 thus boosted is applied to the power supply terminal + V of the drive circuit section 6 through the output terminal 5b.

In FIG. 3, the timing of inverting the clock signal CL21 to "L" level to turn off the PMOS transistor T21 and the timing of inverting the clock signal CL22 to "H" level to turn on the NMOS transistor T24. , The timing for inverting the clock signal CL23 to "L" level to turn off the PMOS transistor T22, and the "H" level inversion of the clock signal CL24 for turning on the NMOS transistor T26. The delay time τ between the timings is to cope with a situation where the turning off of the PMOS transistors T21 and T22 is delayed due to a response delay in the resistors R21 to R24 in the voltage level conversion circuits 5e and 5f. To prevent a through current from flowing through the push-pull circuits 5c and 5d. It is configured to stop.

In the drive circuit section 6, the following operation is performed. That is, in the drive circuit section 6, the power supply terminal + V
On the other hand, from the state in which the voltage boosted through the first booster circuit 4 and the second booster circuit 5 is input, as shown in FIG. Control for setting to the “H” level is performed. Then, the NMOS transistor 8 in the voltage level conversion unit 8
Since the voltage dividing circuit 8a outputs a voltage dividing signal having a voltage level lower than the voltage of the power supply terminal + V by at least the gate threshold voltage of the PMOS transistor 7a in response to the turning on of the power supply terminal b, the high voltage output unit 7 PMOS transistor 7a is turned on. As a result, the voltage applied to the power supply terminal + V (the voltage obtained by boosting the output voltage V0 of the battery 2 by 12 times)
Is supplied to the EL element 1a via the PMOS transistor 7a and the output terminal Q.

Thereafter, as shown in FIG. 4, the clock signal CL08 is inverted to "L" level, and the clock signal CL07 is set to "H" after a predetermined delay time τ 'has elapsed.
Invert to level. Then, in response, the PMOS transistor 7a is turned off and the NMOS transistor 7b is turned on, so that a voltage at the ground potential level is output from the output terminal Q. As described above, the EL display panel 1 is driven in response to the PMOS transistors 7a and 7b in the high voltage output section 7 being turned on alternately. The delay time τ ′ is set to prevent a situation in which a through current flows through the high voltage output unit 7 due to a response delay of the PMOS transistor 7a due to the presence of the voltage dividing circuit 8a.

According to the configuration of this embodiment described above, the battery 2
In order to boost the output voltage of the driver IC 3 by about 12 times, it is only necessary to provide a total of seven capacitors, so that the required number of capacitors can be reduced. This can be realized, and the manufacturing cost can be reduced. Incidentally, in the conventional configuration, twelve capacitors are required to obtain a step-up ratio of about 12 times. Further, the PMOS transistors T21, T22 and NM in the second booster circuit 5, which require a high withstand voltage specification,
The OS transistors T23 to T26 are manufactured by the same semiconductor manufacturing process as the high breakdown voltage PMOS transistor 7a and the high breakdown voltage NMOS transistors 7b and 8b in the drive circuit section 6, so that the manufacturing process may be complicated. This can contribute to reduction of the manufacturing cost from this aspect as well.

(Second Embodiment) FIG. 5 shows a second embodiment of the present invention. Only the portions different from the first embodiment will be described below. That is, in the second embodiment, by providing the second booster circuits 5 and 9 in two stages after the first booster circuit 4, a larger booster ratio (3
(6 times) can be obtained. In this case, the second booster circuit 9
Has the same configuration as the second booster circuit 5. That is, the second booster circuit 9 includes three diodes D31 to D31.
D33, capacitors C31 to C33, high-breakdown-voltage P-channel MOS transistors T31 and T32 (corresponding to the high-breakdown-voltage semiconductor switching element in the present invention: hereinafter referred to as PMOS transistors) and high-breakdown-voltage N-channel MOS transistors T33 to T36. (Corresponding to a high breakdown voltage semiconductor switching element in the present invention: hereinafter referred to as an NMOS transistor) constitutes a charge pump circuit.

Specifically, the diodes D31 to D33 are serially connected in a forward direction between the input terminal 9a and the output terminal 9b of the second booster circuit 9. The PMOS transistor T31 and the NMOS transistor T34 are connected in series between the input terminal 9a and the ground terminal to form a push-pull circuit 9c.
The S transistor T36 is connected in series between the input terminal 9a and the ground terminal to form a push-pull circuit 9d.

The NMOS transistor T33 is connected to the PMO
It constitutes a voltage level conversion circuit 9e for turning on the S transistor T31. The drain is connected to the input terminal 9a via a series circuit of resistors R31 and R32, and the source is connected to the ground terminal. In this case, the common connection point of the resistors R31 and R32 is a PMOS transistor T31.
Connected to the gate. Note that this voltage level conversion circuit 9
e is input to the input terminal 9a at a voltage (second
When the NMOS transistor T33 is turned on in a state where the voltage stepped up by the step-up circuit 5 is applied, the voltage drop at the resistor R31 is equal to or higher than the gate threshold voltage level of the PMOS transistor T31. ing.

The NMOS transistor T35 is connected to the PMO
It constitutes a voltage level conversion circuit 9f for turning on the S transistor T32. The drain is connected to the input terminal 9a via a series circuit of resistors R33 and R34, and the source is connected to the ground terminal. In this case, the common connection point of the resistors R33 and R34 is a PMOS transistor T32
Connected to the gate. Note that this voltage level conversion circuit 9
f is a voltage of the level described below (second
When the NMOS transistor T35 is turned on in a state where the voltage boosted by the booster circuit 5 is applied, the voltage drop at the resistor R33 is equal to or higher than the gate threshold voltage level of the PMOS transistor T32. ing.

The capacitors C31 and C32 function as pump capacitors and are set to have the same capacitance. The capacitor C33 functions as a smoothing capacitor and are set to have a larger capacitance than the capacitors C31 and C32. These capacitors C31 to C33 are individually connected at one end to the cathodes of the corresponding diodes D31 to D33. The other end of the capacitor C31 is connected to the output terminal of the push-pull circuit 9d.
The other end of the capacitor 32 is connected to the output terminal of the push-pull circuit 9c, and the other end of the capacitor C33 is connected to the ground terminal.

The second booster circuit 9 has an input terminal 9a connected to the output terminal 5b of the second booster circuit 5, and an output terminal connected to the power supply terminal + V of the drive circuit section 6. Each of the NMOS transistors T33 to T36 receives a clock signal CL31 from a clock control circuit (not shown).
CL34 to ON / OFF.

In this embodiment configured as described above,
The second booster circuit 9 operates in the same manner as the operation of the second booster circuit 5 described in the first embodiment, whereby the terminal voltage V33 of the last-stage capacitor C33 becomes
The output voltage is boosted to three times the output voltage V23 of the second booster circuit 5, that is, 36 times the output voltage V0 of the battery 2.
That is, according to the configuration of the present embodiment, in order to boost the output voltage of the battery 2 to about 36 times, it is only necessary to provide a total of 10 capacitors, and the required number of capacitors can be greatly reduced. Will be able to

(Other Embodiments) The present invention is not limited to the above-described embodiment, but can be modified or expanded as follows. In the above embodiment, the first booster circuit 4, the second booster circuit 5 (and 9), the drive circuit section 6, and the like are configured as integrated circuits on the same semiconductor substrate. It may be configured to be integrated. Further, the first booster circuit 4 and the second booster circuit 5
A part or all of the capacitors C11 to C14, C21 to C23, and C31 to C33 in the charge pump circuit constituting (and 9) may be provided as external circuit elements.

The first booster circuit and the second booster circuit are provided by EL
Driver IC for driving display panel data electrodes
In addition, each of the first and second booster circuits may be shared by the respective driver ICs.

[Brief description of the drawings]

FIG. 1 is a diagram showing a circuit configuration of a first embodiment of the present invention.

FIG. 2 is a timing chart showing a voltage waveform of each part in a first booster circuit;

FIG. 3 is a timing chart showing a voltage waveform of each part in a second booster circuit;

FIG. 4 is a timing chart showing a voltage waveform of each part in the drive circuit unit.

FIG. 5 is a diagram showing a circuit configuration according to a second embodiment of the present invention with a part of the circuit configuration being omitted;

[Explanation of symbols]

1 is EL display panel (display device), 1a is EL
Element 2, battery (DC power supply), 3, 3 'driver I
C, 4 are a first booster circuit, 5 is a second booster circuit, 6 is a drive circuit section, 7a is a P-channel MOS transistor (high breakdown voltage semiconductor switching element), 8a and 8b are N-channel MOS transistors (high breakdown voltage semiconductor). Switching element), 9 is a second booster circuit, D11 to D14, D21 to D23,
D31 to D33 are diodes, C11 to C14, C21 to C23, C
31 to C33 are capacitors, T11 and T12 are P-channel MOS
Transistor (semiconductor switching element), T13, T14
Is an N-channel MOS transistor (semiconductor switching element), T21, T22, T31 and T32 are P-channel MOS transistors (high breakdown voltage semiconductor switching element), and T23 to
T26 and T33 to T36 denote P-channel MOS transistors (high-voltage semiconductor switching elements).

Continued on front page F term (reference) 5C080 AA06 DD22 DD27 FF03 JJ03 JJ04 5H730 AA07 AA15 AS04 BB02 BB57 BB86 DD04 DD32

Claims (6)

[Claims] A display device driving circuit configured to supply a high voltage output obtained by boosting a DC power supply voltage to a display device through a driving circuit unit including a high withstand voltage semiconductor switching element. A capacitor, and a charge pump circuit configured by a semiconductor switching element group for charging and discharging the capacitor, a first booster circuit that boosts and outputs the DC power supply voltage, a plurality of diodes and a capacitor, And a second booster circuit configured to form a charge pump circuit by a group of high-voltage semiconductor switching elements for charging and discharging the capacitor, and to boost the output voltage of the first booster circuit and provide the boosted output voltage to the drive circuit unit. A driving circuit for a display device, comprising: 2. The second booster circuit includes a plurality of stages of a charge pump circuit including a plurality of diodes and capacitors, and a group of high-voltage semiconductor switching elements for charging and discharging the capacitors. The driving circuit for a display device according to claim 1, wherein: 3. The first booster circuit and the second booster circuit, wherein all or a part of a charge pump circuit constituting the first booster circuit and the second booster circuit are integrated.
Or the display device driving circuit according to 2. 4. The drive circuit for a display device according to claim 3, wherein the first booster circuit and the second booster circuit include a capacitor in a charge pump circuit constituting them as an external circuit element. A driving circuit for a display device, characterized in that: 5. The drive circuit for a display device according to claim 3, wherein the first booster circuit and the second booster circuit are integrated on the same semiconductor substrate together with the drive circuit. A driving circuit for a display device, comprising: 6. The drive circuit for a display device according to claim 3, wherein the high breakdown voltage semiconductor switching element in the drive circuit section and the high breakdown voltage semiconductor switching element in the second booster circuit are the same. A drive circuit for a display device, which is formed by the semiconductor manufacturing process according to (1).