JP4974520B2 - Charge pump circuit, LCD driver IC, electronic equipment - Google Patents

Description

  The present invention relates to a charge pump circuit that generates a desired output voltage by boosting an input voltage, and an LCD driver IC and an electronic device including the charge pump circuit.

  FIG. 7 is a circuit diagram showing a conventional example of a charge pump circuit. This figure (a) shows the positive boost type (double boost) charge pump circuit, and this figure (b) shows the negative boost type (-1 times boost) charge pump circuit. .

  In each of the charge pump circuits 100 and 200 shown in FIGS. 7A and 7B, the switches 101 to 104 and 201 to 204 are periodically turned on / off at a predetermined timing, so that the input voltage Vin can be reduced. A desired output voltage Vout is generated.

  The positive boost operation of the charge pump circuit 100 will be described more specifically.

  First, when the switches 101 and 104 are turned on and the switches 102 and 103 are turned off, the input voltage Vin is applied to one end (point A) of the first capacitor 105 and the other end (point B) is grounded. A voltage GND is applied. Therefore, the first capacitor 105 is charged until the potential difference between both ends is substantially equal to the input voltage Vin.

  After the charging of the first capacitor 105 is completed, the transistors 101 and 104 are turned off and the switches 102 and 103 are turned on. By such switch control, the point B is raised from the ground voltage GND to the input voltage Vin. Here, since a potential difference equal to the input voltage Vin is given between the both ends of the first capacitor 105 by the previous charging, when the potential at the point B is raised to the input voltage Vin, the potential at the point A is accordingly increased. The potential is also raised to 2Vin (input voltage Vin + charge voltage Vin).

  At this time, since the point A is connected to the ground terminal via the switch 102 and the second capacitor 106, the second capacitor 106 is charged until the potential difference between both ends becomes approximately 2 Vin. As a result, as the output voltage Vout, a positive boosted voltage 2Vin obtained by positively boosting the input voltage Vin twice is extracted.

  Next, the negative boost operation of the charge pump circuit 200 will be described more specifically.

  First, when the switches 201 and 203 are turned on and the switches 202 and 204 are turned off, the input voltage Vin is applied to one end (point C) of the first capacitor 205 and the other end (point D) is grounded. A voltage GND is applied. Accordingly, the first capacitor 205 is charged until the potential difference between both ends is substantially equal to the input voltage Vin.

  After the charging of the first capacitor 205 is completed, the transistors 201 and 203 are turned off and the switches 202 and 204 are turned on. By such switch control, the point C is lowered from the input voltage Vin to the ground voltage GND. Here, since a potential difference equal to the input voltage Vin is given between the both ends of the first capacitor 205 by the previous charging, when the potential at the point C is lowered to the ground voltage GND, the potential at the point D is accordingly increased. The potential is also lowered to −Vin (ground voltage GND−charge voltage Vin).

  At this time, the point D is in conduction with the output terminal via the switch 202, so that the charge of the second capacitor 206 moves to the first capacitor 205. As a result, as the output voltage Vout, a negative boosted voltage -Vin obtained by negatively boosting the input voltage Vin at the same magnification is extracted.

  Conventionally, in many applications that require positive and negative internal voltages for driving (for example, liquid crystal display drivers and flash memories), the positive boost type charge pump as described above is used as means for generating positive and negative internal voltages. The circuit is configured to include both a circuit and a negative boost type charge pump circuit (see, for example, Patent Document 1).

  Other conventional techniques related to the present invention include a semiconductor integrated circuit device that prevents latch-up of a parasitic transistor (see Patent Document 2) and a back gate of a transistor that constitutes a pump cell and an input node. There has been disclosed and proposed a charge pump circuit (see Patent Document 3) that prevents a decrease in pump efficiency due to the back gate effect by connecting an auxiliary capacitor, and prevents latch-up and charge leakage.

  For example, in Patent Documents 4 to 5, various disclosures and proposals have been made regarding techniques for improving the rising characteristics of the charge pump circuit.

Japanese Patent Laid-Open No. 7-231647 JP-A-6-216323 JP 2000-173288 A JP 2004-208142 A JP-A-7-322606

  Certainly, with the charge pump circuits 100 and 200 having the above-described conventional configuration, it is possible to generate a desired output voltage Vout (2Vin or −Vin) by positively or negatively boosting the input voltage Vin. .

  However, in the charge pump circuits 100 and 200 having the above-described conventional configuration, only one positive and negative boosted voltage can be obtained by one circuit. Therefore, when both positive and negative boosted voltages are required, the above-described Patent Document 1 can be used. As in the prior art, both a positive boost type charge pump circuit and a negative boost type charge pump circuit must be provided, and as the number of external capacitors increases, the reduction in the scale of the device is hindered and the cost is reduced. The rise of was invited.

  Further, in the negative boost type charge pump circuit 200 having the above-described conventional configuration, when a field effect transistor is used as the switches 201 to 204, a parasitic diode of a transistor to which a negative voltage is applied causes a malfunction. There is a risk that the back gate voltage (substrate voltage) of the transistor cannot be lowered sufficiently, and the desired output voltage Vout cannot be generated.

  Further, in the charge pump circuits 100 and 200 having the above-described conventional configuration, the start-up characteristics (start-up time) are adjusted by appropriately adjusting the current supply capability of the field effect transistors used as the switches 101 to 104 and 201 to 204. Was decided. Therefore, the user cannot arbitrarily adjust the start-up characteristic.

  In view of the above problems, the present invention provides a charge pump circuit capable of generating both positive and negative boosted voltages while suppressing an increase in device scale, and an LCD driver IC and an electronic device including the charge pump circuit. For the purpose.

  In order to achieve the above object, a charge pump circuit according to the present invention includes a boost capacitor that is periodically charged and discharged; and when charging the boost capacitor, one end of the boost capacitor is used as an input voltage application end. Charging means for conducting and connecting the other end to the ground terminal; when outputting a positive voltage; a first discharge for connecting one end of the boost capacitor to the positive voltage output terminal and the other end to the input voltage application terminal And a second discharging means for connecting one end of the boost capacitor to the ground terminal and the other end to a negative voltage output terminal when outputting a negative voltage; and a first connected to the positive voltage output terminal An output capacitor; and a second output capacitor connected to the negative voltage output terminal; each time charging of the boost capacitor is completed, positive and negative voltage output by the first and second discharging means is generated. Exchange It has a structure in which repeated.

  Further, an LCD driver IC according to the present invention is an LCD driver IC for controlling driving of a liquid crystal display, and includes the charge pump circuit as means for generating a positive / negative driving voltage of the liquid crystal display. Yes.

  Further, an electronic device according to the present invention is an electronic device comprising a liquid crystal display which is a display means of the device, and an LCD driver IC which performs drive control of the liquid crystal display, and the LCD driver IC includes: The LCD driver IC is provided.

  With the charge pump circuit according to the present invention, it becomes possible to generate both positive and negative boosted voltages while suppressing an increase in the scale of the device. As a result, downsizing of LCD driver ICs and electronic devices equipped with the same, It is possible to contribute to lightening.

  In the following, a DC / DC converter that is mounted on an LCD [Liquid Crystal Display] driver IC of a digital (still / video) camera, converts a DC input voltage, and generates a drive voltage for a gate control unit and a source control unit. The case where the invention is applied will be described as an example.

  FIG. 1 is a block diagram showing an embodiment of a digital camera according to the present invention (particularly, a power supply system portion of an LCD driver IC). As shown in the figure, the digital camera of this embodiment includes a DC power supply 10 that is a device power supply, a TFT [Thin Film Transistor] liquid crystal display 20 (hereinafter referred to as LCD 20) that is a display means of the device, and a drive of the LCD 20. And an LCD driver IC 30 that performs control.

  Although not explicitly shown in the figure, the digital camera of the present embodiment has a CCD [Charge Coupled Devices] type as means for realizing the essential functions (imaging function, etc.) in addition to the above-described components. Naturally, it has a CMOS [Complementary Metal Oxide Semiconductor] type imaging device, an imaging unit such as an optical lens, an operation unit, a memory unit, and the like.

  The DC power source 10 is means for supplying power to each part of the apparatus, and may be a secondary battery such as a lithium ion battery, or an AC / DC converter that generates a DC voltage from a commercial AC voltage.

  The LCD 20 extends a plurality of source signal lines and gate signal lines in the vertical direction and the horizontal direction, and turns on / off an active element (field effect transistor) corresponding to each liquid crystal pixel provided at each intersection of both signal lines. It is set as the structure driven according to it.

  The LCD driver IC 30 includes a DC / DC converter 31, a gate control unit 32, and a source control unit 33.

  The DC / DC converter 31 is a means for generating various internal voltages (VDD2, Vref, VR, VS, VGH, VGL) by converting the power supply voltage VDD (+3 [V]) from the DC power supply 10. . The internal voltage VDD2 is a voltage (+6 [V]) obtained by boosting the power supply voltage VDD twice, and the reference voltage Vref is a bandgap compensation voltage that does not depend on the ambient temperature. The internal voltages VR and VS are constant voltages (+3.36 [V] and +5 [V]) generated based on the reference voltage Vref, and the former uses the drive voltages VGH and VGL of the gate control unit 32. It is used as a reference voltage when generating, and the latter is supplied to the source control unit 33 as the drive voltage VS of the source control unit 33.

  The gate control unit 32 and the source control unit 33 are means for generating a gate signal and a source signal for the LCD 30 based on a video signal from the outside of the IC and supplying the signals to the LCD 30.

  Note that the gate control unit 32 requires a positive drive voltage VGH (for example, +9 [V]) and a negative drive voltage VGL (for example, −6 [V]) when generating the gate signal of the LCD 30. Therefore, in the DC / DC converter 31 of this embodiment, it is possible to generate the positive and negative output voltages VGH and VGL from the single input voltage VDD as means for generating the drive voltages VGH and VGL of the gate controller 32. A positive / negative boost type charge pump circuit is used.

  FIG. 2 is a circuit diagram showing a configuration example of the charge pump circuit 31 a mounted on the DC / DC converter 31.

  As shown in this figure, the charge pump circuit 31a of this embodiment includes switches SW1a to SW1b, switches SW2a to SW2c, switches SW3a to SW3b, switches SW4a to SW4b, switches SW5a to SW5b, and boost capacitors Cc1 to Cc1. Cc2 and output capacitors Co1 to Co2 are configured to generate desired output voltages VGH and VGL from the internal voltage VR by periodically turning on and off each of the switches at a predetermined timing. It is said that.

  In the charge pump circuit 31a of the present embodiment, P-channel field effect transistors are used as the switches SW1a, SW2a-2b, and SW3a-SW3b, and the switches SW1b, SW2c, SW4a- N-channel field effect transistors are used as SW4b and switches SW5a to SW5b.

  Therefore, when describing the connection relationship between circuit elements in the internal configuration of the charge pump circuit 31a, the switches SW1a to SW1c, switches SW2a to SW2c, switches SW3a to SW3b, switches SW4a to SW4b, and switches SW5a to SW5b are described. This will be referred to as transistors SW1a to SW1c, transistors SW2a to SW2c, transistors SW3a to SW3b, transistors SW4a to SW4b, and transistors SW5a to SW5b, respectively.

  The drain of the transistor SW1a is connected to the application terminal for the internal voltage VR. The source of the transistor SW1a is connected to the external terminal T1a. The back gate of the transistor SW1a is connected to its own source.

  The drain of the transistor SW1b is connected to the external terminal T1b. The source of the transistor SW1b is grounded. The back gate of the transistor SW1b is connected to its own source.

  The drain of the transistor SW2a is connected to the external terminal T1a. The source of the transistor SW2a is connected to the external terminal T2a. The back gate of the transistor SW2a is connected to its own source. The transistor SW2a has a high breakdown voltage specification.

  The source of the transistor SW2b is connected to the application terminal for the internal voltage VR. The drain of the transistor SW2b is connected to the external terminal T1b. The back gate of the transistor SW2b is connected to its own source.

  The drain of the transistor SW2c is connected to the drain of the transistor SW3b and the source of the transistor SW5b. The source of the transistor SW2c is grounded. The back gate of the transistor SW2c is connected to its own source via the transistor SW5a.

  The drain of the transistor SW3a is connected to the external terminal T2a. The source of the transistor SW3a is connected to the external terminal T3. The back gate of the transistor SW3a is connected to its own source. The transistor SW3a has a high breakdown voltage specification.

  The source of the transistor SW3b is connected to the application terminal for the internal voltage VR. The back gate of the transistor SW3b is connected to its own source.

  The drain of the transistor SW4a is connected to the external terminal T2b. The source of the transistor SW4a is connected to the external terminal T4. The back gate of the transistor SW4a is connected to its own source. The transistor SW4a has a high breakdown voltage specification.

  The drain of the transistor SW4b is connected to the external terminal T2a. The source of the transistor SW4b is grounded. The back gate of the transistor SW4b is connected to the external terminal T4. The transistor SW4b has a high breakdown voltage specification.

  The source of the transistor SW5a is connected to the back gate of the transistor SW2c, and the drain of the transistor SW5a is connected to the source of the transistor SW2c. The back gate of the transistor SW5a is connected to its own source.

  The drain of the transistor SW5b is connected to the external terminal T2b. The back gate of the transistor SW5b is connected to the external terminal T4. The transistor SW5b has a high breakdown voltage specification.

  A boost capacitor Cc1 is externally connected between the external terminal T1a and the external terminal T1b.

  A boost capacitor Cc2 is externally connected between the external terminal T2a and the external terminal T2b.

  The external terminal T3 corresponds to the output terminal of the positive boost voltage VGH, is grounded via the output capacitor Co1, and is also connected to the positive voltage input terminal (not shown) of the gate controller 32.

  The external terminal T4 corresponds to the output terminal of the negative boost voltage VGL, is grounded via the output capacitor Co2, and is also connected to the negative voltage input terminal (not shown) of the gate controller 32.

  Each transistor is accompanied by a parasitic diode. In particular, the transistor SW2c is accompanied by a parasitic diode D1 whose back gate is an anode and whose source is a cathode.

  As can be seen from the above, the transistor SW1a is a switch that turns on / off the connection line between the application terminal of the internal voltage VR and one end of the capacitor Cc1. The transistor SW1b is a switch that turns on / off the connection line between the other end of the capacitor Cc1 and the ground end.

  The transistor SW2a is a switch that turns on / off a connection line between one end of the capacitor Cc1 and one end of the capacitor Cc2. The transistor SW2b is a switch that turns on / off the connection line between the other end of the capacitor Cc1 and the application end of the internal voltage VR. The transistor SW2c is a switch that turns on / off the connection line between the other end of the capacitor Cc2 and the ground end.

  The transistor SW3a is a switch that turns on / off a connection line between one end of the capacitor Cc2 and the external terminal T3 (positive voltage output terminal). The transistor SW3b is a switch that turns on / off the connection line between the other end of the capacitor Cc2 and the application end of the internal voltage VR.

  The transistor SW4a is a switch that turns on / off a connection line between the other end of the capacitor Cc2 and the external terminal T4 (negative voltage output terminal). The transistor SW4b is a switch that turns on / off the connection line between one end of the capacitor Cc2 and the ground end.

  The transistor SW5a is a switch that turns on / off the connection line between the back gate and the source of the transistor 2c. The transistor SW5b is a switch that turns on / off a connection line between the drain of the transistor SW2c and the other end of the capacitor Cc2 and the drain of the transistor SW4a.

  A gate control signal is applied from a control circuit (not shown) to each gate of the above-described transistors SW1a to SW1b, transistors SW2a to 2c, transistors SW3a to SW3b, transistors SW4a to SW4b, and transistors SW5a to SW5b. ing.

  The positive / negative voltage output operation of the charge pump circuit 31a having the above configuration will be specifically described with reference to FIG.

  FIG. 3 is a timing chart showing a waveform example of a gate control signal (ON / OFF signal of each switch) applied to each transistor. Note that the high-level potential and low-level potential of each gate signal are as shown at the right end of the figure.

  After the activation of the charge pump circuit 31a, first, in a period t1, the switches SW1a to SW1b are turned on and the switches SW2a to SW2c are turned off. By such switch control, the internal voltage VR is applied to one end (external terminal T1a) of the capacitor Cc1, and the ground voltage GND is applied to the other end (external terminal T1b). Accordingly, the capacitor Cc1 is charged until the potential difference between both ends becomes substantially the internal voltage VR. That is, the period t1 corresponds to the charging period of the capacitor Cc1.

  Note that in the period t1, the switches SW3a to SW3b, the switches SW4a to SW4b, and the switches SW5a to SW5b other than those described above are each turned on / off when the negative output voltage VGL is output from the external terminal T4 (FIG. 3). In the on / off state shown in FIG. However, immediately after the activation of the charge pump circuit 31a, no charge is accumulated in the capacitor Cc2, so that the negative voltage VGL is not output.

  After the charging of the capacitor Cc1 is completed, in the period t2, the switches SW1a to SW1b are turned off, and the switches SW2a to SW2c and the switches SW5a to 5b are turned on. On the other hand, the switches SW3a to SW3b and the switches SW4a to SW4b are turned off.

  By this switch control, the other end (external terminal T1b) of the capacitor Cc1 is connected to the application end of the internal voltage VR via the switch SW2b, and the potential is raised from the ground voltage GND to the internal voltage VR. Here, since a potential difference equal to the internal voltage VR is given between both ends of the capacitor Cc1 by the previous charging, when the potential of the external terminal T1b is raised to the internal voltage VR, the potential of the external terminal T1a is accordingly increased. Is also increased to 2VR (internal voltage VR + charge voltage VR). At this time, since the external terminal T1a is connected to the ground terminal via the switch SW2a, the capacitor Cc2, the switch SW5b, and the switch SW2c, the capacitor Cc2 is charged until the potential difference between both ends becomes approximately 2VR. Is done. That is, the period t2 corresponds to the charging period of the capacitor Cc2.

  After the charging of the capacitor Cc2 is completed, the switches SW1a to SW1b are turned on again and the switches SW2a to SW2c are turned off in the period t3. By such switch control, the capacitor Cc1 is charged until the potential difference at both ends becomes substantially the internal voltage VR, as in the above-described period t1.

  In the period t3, the switches SW3a to SW3b and the switch SW5b are turned on, and the switches SW4a to SW4b and the switch SW5a are turned off. By such switch control, the other end (external terminal T2b) of the capacitor Cc2 is connected to the application terminal of the internal voltage VR via the switch SW5b and the switch SW3b, and the potential is changed from the ground voltage GND to the internal voltage. Raised to VR. Here, since the potential difference 2VR is given between the both ends of the capacitor Cc2 by the previous charging, when the potential of the external terminal T2b is raised to the internal voltage VR, the potential of the external terminal T2a is 3VR (internal). Voltage VR + charge voltage 2VR). At this time, since the external terminal T2a is connected to the ground terminal via the switch SW3a and the capacitor Co1, the capacitor Co1 is charged until the potential difference between both ends becomes approximately 3 Vin. As a result, the positive boosted voltage 3VR obtained by positively boosting the internal voltage VR three times as the output voltage VGH is extracted from the external terminal T3.

  That is, the period t3 corresponds to the charging period of the capacitor Cc1, and also corresponds to the output period of the output voltage VGH (positive boosted voltage 3VR).

  After the output voltage VGH is drawn over the period t3, in the period t4, the switches SW1a to SW1b are turned off again, and the switches SW2a to SW2c and the switches SW5a to SW5b are turned on. On the other hand, the switches SW3a to SW3b and the switches SW4a to SW4b are turned off. Accordingly, the capacitor Cc2 is charged until the potential difference between both ends thereof is approximately 2VR, as in the above-described period t2. That is, the period t4 corresponds to the charging period of the capacitor Cc2.

  After the charging of the capacitor Cc2 is completed, the switches SW1a to SW1b are turned on again and the switches SW2a to SW2c are turned off in the period t5. By such switch control, the capacitor Cc1 is charged until the potential difference at both ends becomes substantially the internal voltage VR, as in the above-described period t1.

  In the period t5, the switches SW4a to SW4b are turned on, and the switches SW3a to SW3b and the switches SW5a to SW5b are turned off. By such switch control, one end (external terminal T2a) of the capacitor Cc2 is connected to the ground terminal via the switch SW4b, and the potential is lowered to the ground voltage GND. Here, since the potential difference 2VR is given between the both ends of the capacitor Cc2 by the previous charging, when the potential of the external terminal T2a is lowered to the ground voltage GND, the potential of the external terminal T2b is − The voltage is lowered to 2VR (ground voltage GND−charge voltage 2VR). At this time, since the external terminal T2b is in conduction with the external terminal T4 via the switch SW4a, the charge of the capacitor Co2 moves to the capacitor Cc2. As a result, a negative boosted voltage −2VR obtained by negatively boosting the internal voltage VR twice is extracted from the external terminal T4 as the output voltage VGL.

  That is, the period t5 corresponds to a charging period of the capacitor Cc1, and also corresponds to an output period of the output voltage VGL (negative boosted voltage −2VR).

  In the subsequent switch control, every time charging of the capacitor Cc2 is completed, the output periods of the output voltages VGH and VGL are alternately repeated, and the positive and negative output voltages VGH and VGL are drawn from the output terminals T3 and T4. .

  As described above, the charge pump circuit 31a of the present embodiment is a boost capacitor that is periodically charged and discharged (when multiple boosting is performed using a plurality of boost capacitors Cc1 to Cc2 as in the present embodiment). Indicates the final boost capacitor Cc2); and when charging the boost capacitor Cc2, one end (T2a) of the boost capacitor Cc2 is made conductive to the application terminal of the internal voltage VR via the boost capacitor Cc1, and the other end Charging means (switches SW2a to SW2b) for conducting (T2b) to the ground terminal; and when outputting the positive output voltage VGH, one end (T2a) of the boost capacitor Cc2 is conducted to the positive voltage output terminal (T3), First discharge means (switches SW3a to SW3b) for connecting the other end (T2b) to the application end of the internal voltage VR; and outputting a negative output voltage VGL The second discharging means (switches SW4a to SW4b) for connecting one end (T2a) of the boost capacitor Cc2 to the ground terminal and the other end (T2b) to the negative voltage output terminal T4; and the positive voltage output terminal T3. The first output capacitor Co1 connected to the second output capacitor Co2 connected to the negative voltage output terminal T4, and each time the charging of the boost capacitor Cc2 is completed, the first, second The output of positive and negative voltages VGH and VGL by the discharging means is alternately repeated.

  By adopting such a configuration, both positive and negative while suppressing the expansion of the device scale (increase in the number of external capacitors) compared to a configuration including both a positive boost charge pump circuit and a negative boost charge pump circuit. Output voltages VGH (3VR) and VGL (-2VR) can be generated, and as a result, the LCD driver IC 30 and the digital camera equipped with the output voltages can be made smaller and lighter.

  In the charge pump circuit 31a of the present embodiment, since the outputs of the positive and negative voltages VGH and VGL are alternately repeated, there is a possibility that the ripples are somewhat increased as compared with the case where the output voltage having the same polarity is generated each time. However, since the positive and negative voltages VGH and VGL are used when the gate control unit 32 generates the gate signal, there is a possibility that the logic (high level / low level) of the gate signal may be affected even if the ripple is slightly increased. Almost no.

  In the above description, the case where the logic transition timings of the gate signals are matched has been described as an example. However, FIG. 3 is merely a depiction for ease of explanation, and in general, input is performed. In order to avoid a ground short circuit at the voltage application terminal and the output voltage extraction terminal, as shown in FIG. 4, the gate signals are often inconsistent in logic transition timing.

  Next, functions of the switches SW5a to SW5b (parasitic operation avoidance function at the time of negative voltage output) will be described in detail with reference to FIG. 5 in addition to FIGS.

  FIG. 5 is a cross-sectional view showing the vertical structure of the charge pump circuit 31a. 5A shows a case where the switches SW5a to SW5b are provided, and FIG. 5B shows a case where the switches SW5a to SW5b are not provided for reference.

  Generally, when an N-channel field effect transistor is used as the switches SW4a to SW4b, the back gate potential needs to be lower than the channel potential. Therefore, in the charge pump circuit 31a of the present embodiment, as shown in FIGS. 5A and 5B, the P-type semiconductor substrate is connected to the negative voltage extraction terminal (external terminal T4), via the path i1. By pulling out the current, the back gate potential (that is, the substrate potential) of the switches SW4a to SW4b is lowered to the output voltage VGL (−2VR).

  Incidentally, when the charge pump circuit 31a is formed, if the other end (external terminal T2b) of the boost capacitor Cc2 is simply connected to either the ground terminal or the negative voltage output terminal, as shown in FIG. In addition, it is only necessary to provide the switches SW2c and SW4a between the external terminal T2b and the ground terminal and between the external terminal T2b and the negative voltage output terminal.

  However, when the configuration of FIG. 5B is adopted, the parasitic diode D1 associated with the switch SW2c is in a forward bias state when the output voltage VGL is output, and the current is drawn from the ground terminal via the path i2. turn into.

  As described above, when the current is drawn from the unintended ground terminal instead of from the P-type semiconductor substrate, the back gate potentials of the switches SW4a to SW4b cannot be lowered, and the output voltage VGL is negatively reduced to a desired value. There is a risk that the pressure cannot be increased.

  Therefore, in the charge pump circuit 31a of the present embodiment, the switch SW5a is connected between the back gate of the switch SW2c and the ground terminal in order to cut off the path i2, and the drain of the switch SW2c and the boost capacitor Cc2 are connected. The switch SW5b is connected between the other end of the switch and the drain of the switch SW4a.

  The switch SW5a is controlled to turn on the connection line between the back gate and the ground terminal of the switch SW2c only when charging the boost capacitor Cc2, and to turn off the connection line at other times.

  On the other hand, the switch SW5b is controlled to turn off the connection line connected to the drain of the switch SW2c only when outputting the negative output voltage VGL, and to turn on the connection line at other times.

  By providing such switches SW5a and SW5b, even when the parasitic diode D1 associated with the switch SW2c is in a forward bias state when the output voltage VGL is output, the path i2 is reliably cut off by the switches SW5a and SW5b. Therefore, an unintended current is not drawn from the ground terminal.

  Therefore, with the charge pump circuit 31a of the present embodiment, the current can be reliably extracted from the P-type semiconductor substrate via the path i1, so that the back gate potential (ie, substrate potential) of the switches SW4a to SW4b is sufficient. As a result, the output voltage VGL can be surely negatively boosted to the desired value (−2VR).

  Next, variable control of the start-up characteristic (start-up time) in the charge pump circuit 31a will be described in detail with reference to FIG.

  FIG. 6 is a diagram illustrating a relative relationship between the charging period of the boost capacitor Cc2 and the output periods of the output voltages VGH and VGL.

  As shown in the figure, in the charge pump circuit 31a of the present embodiment, a control circuit (not shown) that generates a gate signal of each switch has a charging period (t2, t4) of the boost capacitor Cc2 according to a predetermined control signal. ,... And the output period (t3,...) Of the output voltage VGH and the output period (t1, t5,...) Of the output voltage VGL are variably controlled.

  For example, as shown in FIG. 6B, as shown in FIG. 6A, the charging period of the boost capacitor Cc2 and the output periods of the output voltages VGH and VGL coincide with each other as shown in FIG. If the latter period is made shorter than the former period, the rise of the output voltages VGH and VGL can be moderated. Although not clearly shown in the figure, it is conceivable to perform the same variable control for the output periods of the output voltages VGH and VGL.

  Unlike the configuration in which the start-up characteristics are determined by appropriately adjusting the current supply capability of the field effect transistor used as each switch by adopting a configuration capable of performing such variable control, according to a predetermined control signal The start-up characteristics can be adjusted arbitrarily by the user. Therefore, it is possible to appropriately respond not only to the user's request that emphasizes the improvement of the startup speed, but also to the user's request that emphasizes the improvement of stability.

  In particular, in the configuration in which the outputs of the positive and negative voltages VGH and VGL are alternately repeated as in the charge pump circuit 31a of the present embodiment, it is important to improve the stability of the start-up characteristic, and therefore, from the charging period of the boost capacitor Cc2. Also, it is preferable to moderate the rise of the output voltages VGH and VGL by setting the output periods of the output voltages VGH and VGL short.

  In the above-described embodiment, the description has been given by taking as an example the configuration in which 3VR and -2VR are extracted as the output voltages VGH and VGL, respectively, but the configuration of the present invention is not limited to this, By slightly changing the circuit, such as increasing or decreasing the number of stages and changing the position of the output voltage extraction end, the boosting magnification differs from the above embodiment (double positive boost and equal negative boost, or quadruple positive boost and triple). The present invention can also be widely applied to charge pump circuits such as negative boosters.

  In addition, the configuration in which the switches SW5a and SW5b are provided in order to avoid the parasitic operation at the time of negative voltage output can naturally be applied to a charge pump circuit that performs only negative boost output, and the charging period of the boost capacitor The configuration for variably controlling the relative ratio between the output voltage period and the boost voltage output period is naturally applicable to a charge pump circuit that performs only one of the positive boost output and the negative boost output.

  The configuration of the present invention can be variously modified within the scope of the present invention in addition to the above embodiment.

  The present invention is a useful technique for reducing the size and weight of a charge pump circuit.

These are block diagrams which show one Embodiment of the digital camera which concerns on this invention. These are circuit diagrams showing an example of the configuration of the charge pump circuit 31a. These are timing charts showing a waveform example of a gate control signal applied to each transistor. These are timing charts showing another waveform example of the gate control signal applied to each transistor. These are sectional views showing the vertical structure of the charge pump circuit 31a. These are figures which show the relative relationship between the charging period of boost capacitor Cc2, and each output period of output voltage VGH and VGL. These are circuit diagrams showing a conventional example of a charge pump circuit.

Explanation of symbols

10 DC power supply 30 TFT liquid crystal display (LCD)
30 LCD driver IC
31 DC / DC converter 31a Positive / negative boost type charge pump circuit 32 Gate control unit 33 Source control unit SW1a switch (P-channel field effect transistor)
SW1b switch (N-channel field effect transistor)
SW2a switch (P-channel field effect transistor)
SW2b switch (P-channel field effect transistor)
SW2c switch (N-channel field effect transistor)
SW3a switch (P-channel field effect transistor)
SW3b switch (N-channel field effect transistor)
SW4a switch (N-channel field effect transistor)
SW4b switch (N-channel field effect transistor)
SW5a switch (N-channel field effect transistor)
SW5b switch (N-channel field effect transistor)
Cc1 to Cc2 Boost capacitor Co1 to Co2 Output capacitor T1a to T1b, T2a to T2b, T3, T4 External terminal

Claims (3)

With a 1x boost capacitor;
With a double boost capacitor;
A first switch for electrically connecting one end of the 1 × boost capacitor to an input voltage application end when charging the 1 × boost capacitor;
A second switch for electrically connecting the other end of the 1 × boost capacitor to the ground when charging the 1 × boost capacitor;
A third switch for electrically connecting the other end of the 1 × boost capacitor to the input voltage application end when charging the 2 × boost capacitor;
A fourth switch for electrically connecting one end of the double boost capacitor to one end of the single boost capacitor when charging the double boost capacitor;
A fifth switch for electrically connecting the other end of the double boost capacitor to a ground terminal when charging the double boost capacitor;
First discharging means for conducting one end of the double boosting capacitor to the positive voltage output end and outputting the other end to the input voltage application end when outputting a positive voltage;
Second discharging means for connecting one end of the double boosting capacitor to the ground terminal and outputting the other end to the negative voltage output terminal when outputting a negative voltage;
A first output capacitor connected to the positive voltage output;
A second output capacitor connected to the negative voltage output;
The charge pump circuit is characterized by alternately repeating positive and negative voltage output by the first and second discharging means each time the charging of the double boosting capacitor is completed.   2. An LCD driver IC for controlling driving of a liquid crystal display, comprising the charge pump circuit according to claim 1 as means for generating a positive / negative driving voltage of the liquid crystal display.   An electronic device comprising: a liquid crystal display that is a display means of the device; and an LCD driver IC that performs drive control of the liquid crystal display, wherein the LCD driver IC according to claim 2 is used as the LCD driver IC. An electronic device characterized by comprising.

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