JP2000012566A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JP2000012566A
JP2000012566A JP10177230A JP17723098A JP2000012566A JP 2000012566 A JP2000012566 A JP 2000012566A JP 10177230 A JP10177230 A JP 10177230A JP 17723098 A JP17723098 A JP 17723098A JP 2000012566 A JP2000012566 A JP 2000012566A
Authority
JP
Japan
Prior art keywords
semiconductor chip
resin
power mos
mos transistor
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10177230A
Other languages
Japanese (ja)
Inventor
Kohei Matsuda
公平 松田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Semiconductor Manufacturing Co Ltd
Kansai Nippon Electric Co Ltd
Original Assignee
Renesas Semiconductor Manufacturing Co Ltd
Kansai Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Semiconductor Manufacturing Co Ltd, Kansai Nippon Electric Co Ltd filed Critical Renesas Semiconductor Manufacturing Co Ltd
Priority to JP10177230A priority Critical patent/JP2000012566A/en
Publication of JP2000012566A publication Critical patent/JP2000012566A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To eliminate the reverse surface ohmic contact of the semiconductor chip by mounting a semiconductor chip having a bare high-concentration semiconductor layer on a reverse surface on the island of a lead frame via a conducting adhesive made of silver paste and then by resin encapsulating it. SOLUTION: A semiconductor chip 11 comprising a semiconductor substrate 8 which has a power MOS transistor formed on the reverse surface and a high- concentration layer 8a on the reverse surface is mounted on an island 3 via a conducting adhesive 12 made of silver paste, wherein the high-concentration layer 8a is exposed and has no electrode thereon. The bonding pad on the surface of the semiconductor chip 11 is connected to an inner lead 5 via a gold wire 4, and these are encapsulated with resin 6 and an outer lead is formed integrally with the inner lead 5 outside the resin 6. This can eliminate the reverse surface ohmic contact of the semiconductor chip 11 and can simplify manufacturing process.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、半導体装置に関
し、特にパワーＭＯＳトランジスタ機能を有する半導体
チップをリードフレーム上に搭載して樹脂封止した半導
体装置に関する。The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a semiconductor chip having a power MOS transistor function mounted on a lead frame and sealed with a resin.

【０００２】[0002]

【従来の技術】従来の樹脂封止型パワーＭＯＳトランジ
スタは図５に示すように、パワーＭＯＳトランジスタと
して機能する半導体チップ１をＡｇＰｂＳｎ半田からな
る導電性接着剤２を介してアイランド３上に搭載してい
る。半導体チップ１の表面のボンディングパッドは金線
４を介してインナーリード５に接続されている。これら
は樹脂６により封止され、樹脂６より外にインナーリー
ド５と一体的にアウターリード７を形成している。半導
体チップ１は、表面側にパワーＭＯＳトランジスタを形
成した半導体基板８の裏面に高濃度層８ａを含みその上
にＴｉＮｉＡｇやＣｒＮｉＡｇ等の多層の金属膜からな
る裏面電極９を形成してなる。2. Description of the Related Art As shown in FIG. 5, in a conventional resin-sealed power MOS transistor, a semiconductor chip 1 functioning as a power MOS transistor is mounted on an island 3 via a conductive adhesive 2 made of AgPbSn solder. ing. The bonding pads on the surface of the semiconductor chip 1 are connected to inner leads 5 via gold wires 4. These are sealed with the resin 6, and the outer lead 7 is formed integrally with the inner lead 5 outside the resin 6. The semiconductor chip 1 includes a high-concentration layer 8a on the back surface of a semiconductor substrate 8 on which a power MOS transistor is formed on the front side, and a back electrode 9 made of a multilayer metal film such as TiNiAg or CrNiAg is formed thereon.

【０００３】[0003]

【発明が解決しようとする課題】ところで、従来の樹脂
封止型パワーＭＯＳトランジスタは裏面電極としてＴｉ
ＮｉＡｇやＣｒＮｉＡｇ等の多層の金属膜を形成しなけ
ればならないため、オーミック工程での膜厚等の管理も
大変となり、また、導電性接着剤として半田を使用しな
ければならないため、オーミック工程での裏面電極の出
来栄えによっては半田付け性に問題が生じたり、また半
田独自の問題が発生することにより、ダイボンディング
不良も発生しやすかった。本発明は上記問題点に鑑みて
なされたものであり、チップの裏面オーミックを廃止ま
たは簡単な構成とすることにより、製造工程が簡単で安
価な半導体装置を提供することを目的とする。The conventional resin-encapsulated power MOS transistor uses a Ti as a back electrode.
Since it is necessary to form a multilayer metal film such as NiAg or CrNiAg, it is also difficult to control the film thickness in the ohmic process. Depending on the quality of the back electrode, a problem may occur in the solderability, or a solder-specific problem may occur, so that a die bonding failure is likely to occur. The present invention has been made in view of the above problems, and has as its object to provide an inexpensive semiconductor device with a simple manufacturing process by eliminating or simplifying the back surface ohmic of a chip.

【０００４】[0004]

【課題を解決するための手段】本発明の半導体装置は、
パワーＭＯＳトランジスタ機能を有する半導体チップを
導電性接着剤を介してリードフレームのアイランド上に
搭載して樹脂封止した半導体装置において、半導体チッ
プはその裏面側に高濃度半導体層を露出し、導電性接着
剤は銀ペーストであることを特徴とする。上記の半導体
装置のパワーＭＯＳトランジスタの耐圧は２００Ｖ以上
であることを特徴とする。本発明の半導体装置は、パワ
ーＭＯＳトランジスタ機能を有する半導体チップを導電
性接着剤を介してリードフレームのアイランド上に搭載
して樹脂封止した半導体装置において、半導体チップは
裏面側に高濃度半導体層とこの半導体層表面にオーミッ
ク接触させたアルミニウム膜とを有し、導電性接着剤は
銀ペーストであることを特徴とする。According to the present invention, there is provided a semiconductor device comprising:
In a semiconductor device in which a semiconductor chip having a power MOS transistor function is mounted on an island of a lead frame via a conductive adhesive and sealed with a resin, the semiconductor chip exposes a high-concentration semiconductor layer on the back side thereof, The adhesive is a silver paste. The semiconductor device is characterized in that the withstand voltage of the power MOS transistor is 200 V or more. The semiconductor device of the present invention is a semiconductor device in which a semiconductor chip having a power MOS transistor function is mounted on a lead frame island via a conductive adhesive and sealed with a resin. And an aluminum film in ohmic contact with the surface of the semiconductor layer, and the conductive adhesive is a silver paste.

【０００５】[0005]

【発明の実施の形態】以下に、本発明に基づき第１実施
例の樹脂封止型パワーＭＯＳトランジスタを図１及び図
２を参照して説明する。尚、図５と同一部分には同一符
号を付してある。図１において、パワーＭＯＳトランジ
スタとして機能する半導体チップ１１をＡｇペーストか
らなる導電性接着剤１２を介してアイランド３上に搭載
している。半導体チップ１１の表面のボンディングパッ
ドは金線４を介してインナーリード５に接続されてい
る。これらは樹脂６により封止され、樹脂６より外にイ
ンナーリード５と一体的にアウターリード７を形成して
いる。半導体チップ１１は、表面側にパワーＭＯＳトラ
ンジスタを形成した半導体基板８の裏面に高濃度層８ａ
を含みその層８ａを露出したままで、その上に裏面電極
を形成していない。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A resin-sealed power MOS transistor according to a first embodiment of the present invention will be described below with reference to FIGS. The same parts as those in FIG. 5 are denoted by the same reference numerals. In FIG. 1, a semiconductor chip 11 functioning as a power MOS transistor is mounted on an island 3 via a conductive adhesive 12 made of Ag paste. The bonding pads on the surface of the semiconductor chip 11 are connected to the inner leads 5 via the gold wires 4. These are sealed with the resin 6, and the outer lead 7 is formed integrally with the inner lead 5 outside the resin 6. The semiconductor chip 11 has a high-concentration layer 8a
And the back surface electrode is not formed thereon while the layer 8a is exposed.

【０００６】次に、上述の構成にて従来と同じ設計ルー
ルで耐圧を振らして製造した樹脂封止型パワーＭＯＳト
ランジスタのＯＮ抵抗を従来の樹脂封止型パワーＭＯＳ
トランジスタの面積１mm2 当りのＯＮ抵抗と比較する
と、図２に示すように、耐圧が１００Ｖでは１３０％、
２００Ｖで１１７％、４００Ｖで１０５％で、同じＯＮ
抵抗を得るために２００Ｖではチップ面積を１７％アッ
プする必要があるがコスト的には裏面オーミック工程の
省略で相殺できる。２００Ｖを超えると裏面オーミック
なしのほうが安価に製造できる。Next, the ON resistance of the resin-encapsulated power MOS transistor manufactured by applying the same design rule as in the prior art and applying a withstand voltage to the above configuration is used to reduce the ON resistance of the conventional resin-encapsulated power MOS transistor.
As compared with the ON resistance per 1 mm 2 of the transistor area, as shown in FIG.
117% at 200V, 105% at 400V, same ON
In order to obtain the resistance, it is necessary to increase the chip area by 17% at 200 V, but the cost can be offset by omitting the backside ohmic step. If it exceeds 200 V, it can be manufactured at lower cost without the backside ohmic.

【０００７】次に、請求項１記載の発明の適用がコスト
的に不利となる２００Ｖ以下のパワーＭＯＳトランジス
タに対し適用するのが好適な請求項３記載の発明の実施
の形態について、第２実施例の樹脂封止型パワーＭＯＳ
トランジスタを図３及び図４に示して説明する。尚、図
１と同一部分には同一符号を付してある。図３におい
て、パワーＭＯＳトランジスタとして機能する半導体チ
ップ２１をＡｇペーストからなる導電性接着剤１２を介
してアイランド３上に搭載している。半導体チップ２１
の表面のボンディングパッドは金線４を介してインナー
リード５に接続されている。これらは樹脂６により封止
され、樹脂６より外にインナーリード５と一体的にアウ
ターリード７を形成している。半導体チップ２１は、表
面側にパワーＭＯＳトランジスタを形成した半導体基板
８の裏面に高濃度層８ａを含み、その上にアルミニウム
からなる裏面電極２９を形成している。Next, a second embodiment of the invention according to claim 3, which is preferably applied to a power MOS transistor of 200 V or less, at which application of the invention of claim 1 is disadvantageous in terms of cost. Example of resin-sealed power MOS
The transistor is described with reference to FIGS. The same parts as those in FIG. 1 are denoted by the same reference numerals. In FIG. 3, a semiconductor chip 21 functioning as a power MOS transistor is mounted on the island 3 via a conductive adhesive 12 made of Ag paste. Semiconductor chip 21
Is connected to the inner lead 5 via the gold wire 4. These are sealed with the resin 6, and the outer lead 7 is formed integrally with the inner lead 5 outside the resin 6. The semiconductor chip 21 includes a high-concentration layer 8a on the back surface of a semiconductor substrate 8 on which a power MOS transistor is formed on the front surface side, and a back electrode 29 made of aluminum is formed thereon.

【０００８】次に、上述の構成にて従来と同じ設計ルー
ルで耐圧を振らして製造した樹脂封止型パワーＭＯＳト
ランジスタの面積１mm２ 当りのＯＮ抵抗を従来の樹脂
封止型パワーＭＯＳトランジスタのＯＮ抵抗と比較する
と、図４に示すように、従来と本実施例とで５％以内で
略同一のＯＮ抵抗を有しており、請求項１記載の発明の
適用がコスト的に不利となる２００Ｖ以下の樹脂封止型
パワーＭＯＳトランジスタに請求項３記載の発明を適用
するが有効であることが理解できる。勿論、請求項３記
載の発明を２００Ｖ以下の樹脂封止型パワーＭＯＳトラ
ンジスタに適用してもかまわない。Next, the ON resistance per 1 mm 2 of the area of the resin-encapsulated power MOS transistor manufactured by applying the above-described configuration and applying the withstand voltage according to the same design rule as the conventional one is reduced by the conventional resin-encapsulated power MOS transistor. As compared with the ON resistance, as shown in FIG. 4, the conventional and the present embodiment have substantially the same ON resistance within 5%, which makes application of the invention of claim 1 disadvantageous in cost. It can be understood that applying the invention of claim 3 to a resin-sealed power MOS transistor of 200 V or less is effective. Of course, the invention described in claim 3 may be applied to a resin-sealed power MOS transistor of 200 V or less.

【０００９】以上説明したように、耐圧が２００Ｖ以上
の樹脂封止型パワーＭＯＳトランジスタでは、半導体チ
ップの裏面電極を必要とせず、裏面に高濃度層を含む半
導体基板を直接、Ａｇペーストでアイランドに接着する
ことができ、また、耐圧が２００Ｖ以下の樹脂封止型パ
ワーＭＯＳトランジスタでは、半導体チップの裏面電極
を半導体基板の裏面に含む高濃度層上にアルミニウム膜
で形成し、Ａｇペーストでアイランドに接着することが
でき、従来と略同一のＯＮ抵抗の樹脂封止型パワーＭＯ
Ｓトランジスタを簡単な製造工程で安価に製造すること
ができる。As described above, a resin-sealed power MOS transistor having a withstand voltage of 200 V or more does not require a back electrode of a semiconductor chip, and a semiconductor substrate including a high concentration layer on the back surface is directly formed into an island with an Ag paste. In a resin-sealed power MOS transistor having a withstand voltage of 200 V or less, a back electrode of a semiconductor chip is formed of an aluminum film on a high-concentration layer including a back surface of a semiconductor substrate, and the island is formed with an Ag paste. Resin-sealed power MO that can be bonded and has approximately the same ON resistance as conventional
The S transistor can be manufactured at a low cost by a simple manufacturing process.

【００１０】[0010]

【発明の効果】本発明の半導体装置によれば、パワーＭ
ＯＳトランジスタの耐圧が２００Ｖ以上であれば裏面電
極を無しで、２００Ｖ以下であればアルミニウムの裏面
電極で半導体チップをＡｇペーストを介してアイランド
に搭載でき、簡単な製造工程で安価な半導体装置を供給
することが可能である。According to the semiconductor device of the present invention, the power M
If the withstand voltage of the OS transistor is 200 V or more, there is no back electrode. If the withstand voltage of the OS transistor is 200 V or less, the semiconductor chip can be mounted on the island via the Ag paste with the back electrode of aluminum, and an inexpensive semiconductor device can be supplied by a simple manufacturing process. It is possible to

【図面の簡単な説明】[Brief description of the drawings]

【図１】 本発明の第１実施例である樹脂封止型パワー
ＭＯＳトランジスタの概略構成を示す断面図。FIG. 1 is a sectional view showing a schematic configuration of a resin-sealed power MOS transistor according to a first embodiment of the present invention.

【図２】 従来及び図１に示す樹脂封止型パワーＭＯＳ
トランジスタの各耐圧におけるＯＮ抵抗の比較図。FIG. 2 shows a conventional and resin-sealed power MOS shown in FIG.
FIG. 5 is a comparison diagram of ON resistance at each withstand voltage of a transistor.

【図３】 本発明の第２実施例である樹脂封止型パワー
ＭＯＳトランジスタの概略構成を示す断面図。FIG. 3 is a sectional view showing a schematic configuration of a resin-sealed power MOS transistor according to a second embodiment of the present invention.

【図４】 従来及び図３に示す樹脂封止型パワーＭＯＳ
トランジスタの各耐圧におけるＯＮ抵抗の比較図。FIG. 4 shows a conventional resin-sealed power MOS shown in FIG. 3;
FIG. 5 is a comparison diagram of ON resistance at each withstand voltage of a transistor.

【図５】 従来の樹脂封止型パワーＭＯＳトランジスタ
の概略構成を示す断面図。FIG. 5 is a sectional view showing a schematic configuration of a conventional resin-sealed power MOS transistor.

【符号の説明】[Explanation of symbols]

１１，２１ 半導体チップ １２ 導電性接着剤（Ａｇペースト） １３ アイランド 11, 21 Semiconductor chip 12 Conductive adhesive (Ag paste) 13 Island

Claims (3)

【特許請求の範囲】[Claims] 【請求項１】パワーＭＯＳトランジスタ機能を有する半
導体チップを導電性接着剤を介してアイランド上に搭載
して樹脂封止した半導体装置において、 前記半導体チップはその裏面側に高濃度半導体層を露出
し、前記導電性接着剤は銀ペーストであることを特徴と
する半導体装置。In a semiconductor device in which a semiconductor chip having a power MOS transistor function is mounted on an island via a conductive adhesive and sealed with a resin, the semiconductor chip exposes a high-concentration semiconductor layer on the back surface side. The semiconductor device, wherein the conductive adhesive is a silver paste. 【請求項２】前記パワーＭＯＳトランジスタの耐圧が２
００Ｖ以上であることを特徴とする請求項１記載の半導
体装置。2. The power MOS transistor has a breakdown voltage of 2
2. The semiconductor device according to claim 1, wherein the voltage is 00 V or more. 【請求項３】パワーＭＯＳトランジスタ機能を有する半
導体チップを導電性接着剤を介してアイランド上に搭載
して樹脂封止した半導体装置において、 前記半導体チップは裏面側に高濃度半導体層とこの半導
体層表面にオーミック接触させたアルミニウム膜とを有
し、前記導電性接着剤は銀ペーストであることを特徴と
する半導体装置。3. A semiconductor device in which a semiconductor chip having a power MOS transistor function is mounted on an island via a conductive adhesive and sealed with a resin, wherein the semiconductor chip has a high-concentration semiconductor layer and a semiconductor layer on the back side. A semiconductor device having an aluminum film in ohmic contact with the surface, wherein the conductive adhesive is a silver paste.
JP10177230A 1998-06-24 1998-06-24 Semiconductor device Pending JP2000012566A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10177230A JP2000012566A (en) 1998-06-24 1998-06-24 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10177230A JP2000012566A (en) 1998-06-24 1998-06-24 Semiconductor device

Publications (1)

Publication Number Publication Date
JP2000012566A true JP2000012566A (en) 2000-01-14

Family

ID=16027437

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10177230A Pending JP2000012566A (en) 1998-06-24 1998-06-24 Semiconductor device

Country Status (1)

Country Link
JP (1) JP2000012566A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012049575A (en) * 2011-12-08 2012-03-08 Fuji Electric Co Ltd Semiconductor device
CN113257683A (en) * 2021-04-14 2021-08-13 深圳基本半导体有限公司 Bonding method of silicon carbide power device chip and lead frame

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012049575A (en) * 2011-12-08 2012-03-08 Fuji Electric Co Ltd Semiconductor device
CN113257683A (en) * 2021-04-14 2021-08-13 深圳基本半导体有限公司 Bonding method of silicon carbide power device chip and lead frame

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