JP2000010526A - Display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To dispense with a high-speed high-precision D/A converter and to reduce wiring quantity as well as power consumption, in converting digital data into analog voltage and supplying to each signal line. SOLUTION: This device is provided with a signal line driving circuit 3 which drives each signal line in a liquid crystal display, and with a voltage generating circuit which outputs four kinds of voltages and control signals. The signal line driving circuit 3 is provided with a shift register 11, latch circuit 12, register circuit 13, comparator 14, decoder circuit 15, and analog switch 16 for each signal line. One horizontal line period is divided into plural periods, a voltage range for supplying to the line is set for each divided period, and the voltage range is made selectable by the upper bits of digital pixel data; therefore, a high-speed and high-precision D/A converter becomes unnecessary, reducing power consumption as well as parts cost.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for converting digital pixel data input from the outside into an analog voltage and supplying the analog voltage to each signal line, for example, a signal line driving circuit of a liquid crystal display device. .

[0002]

2. Description of the Related Art One of the signal line driving methods of an active matrix type liquid crystal display device is a method called an analog sample and hold method. FIG. 13 is a diagram for explaining an outline of a conventional analog sample hold system. Digital pixel data D0 output from a computer or the like
Dn is converted to an analog pixel voltage by the D / A converter 101. An analog switch 102 composed of a MOS transistor is connected to each of the signal lines S1 to Sn, and these analog switches 102 are controlled to be turned on and off by output terminals of a shift register 103. Each analog switch 1
02 switches whether or not to supply the analog pixel voltage output from the D / A converter 101 to the signal lines S1 to Sn in accordance with the logic of the corresponding output terminal of the shift register 103.

In the conventional analog sample-and-hold system, a D / A converter 101 as shown in FIG. 13 is indispensable, and a multi-bit display requires the use of a multi-bit D / A converter. No. However, the multi-bit D / A converter has a problem that it is expensive and consumes much power.

Further, in order to increase the display resolution, D /
Video bus line VIDEO connected to A converter 101
Although it is necessary to increase the above data transmission speed, since a large number of analog switches 102 are connected to the video bus line VIDEO, the wiring resistance and the wiring capacity are large, and the data transmission speed is reduced due to the wiring delay. There are also problems.

[0005]

FIG. 14 is a schematic configuration diagram of a drive circuit in which the conventional analog sample-and-hold system is improved, and shows the configuration for one signal line. The register circuit 111 latches the digital pixel data D0 to D3 in synchronization with the output pulse of the shift register 112.
This latch data is latched by the latch circuit 113 in synchronization with the load signal LOAD. The decoder circuit 114
The output of the latch circuit 113 is decoded. An analog switch 115 corresponding to each output terminal of the decoder circuit 114
, And different voltages V0 to V15 are applied to one end of each analog switch 115, respectively.

FIG. 14 shows 4-bit digital pixel data D.
An example is shown in which 16 gradations are displayed using 0 to D3. One of the analog switches 115 is turned on in response to the output of the latch circuit 113, and the analog switch 115 is turned on.
Is supplied to the signal line S1.

As described above, the circuit shown in FIG. 14 includes a number of analog switches 11 corresponding to the number of bits of digital pixel data.
The analog switches 115 select different voltages. For this reason, when the number of gradations, that is, the number of bits of the digital pixel data D0 to Dn increases, a large number of analog switches 115 are required, and the number of voltage lines for supplying the reference voltage also increases. Will increase. For example, when the number of bits of digital pixel data is 6 bits, 64 analog switches and reference voltages are required, and when the number of bits is 8 bits, 256 analog switches are required.

SUMMARY OF THE INVENTION The present invention has been made in view of such a point, and an object of the present invention is to provide a high-speed and high-precision D / D converter for converting digital data into an analog voltage and supplying it to each signal line.
An object of the present invention is to provide a display control circuit which does not require an A-converter and requires less wiring and power consumption.

[0009]

In order to solve the above-mentioned problems, according to the first aspect of the present invention, signal lines and scanning lines are arranged vertically and horizontally, and a switching element is provided at the intersection of each signal line and scanning line. A pixel array section comprising a pixel electrode connected in parallel and a counter electrode facing the pixel electrode, and a signal line drive circuit for supplying an analog pixel voltage corresponding to digital pixel data to each signal line. In the apparatus, the signal line driving circuit includes: a voltage generating unit that outputs a plurality of voltages by switching a voltage range thereof in synchronization with each divided period obtained by dividing one horizontal line period into a plurality of divided periods; Voltage supply timing setting means for selecting a timing of supplying an analog pixel voltage to a signal line from the plurality of divided periods based on logic of a predetermined bit; Based on the logic of the bits other than said predetermined bit of le pixel data, by selecting a plurality of any of the voltage output from said voltage generating means, having a voltage supply means for supplying a corresponding signal line.

According to a third aspect of the present invention, there is provided a pixel array section in which signal lines and scanning lines are arranged vertically and horizontally, and a pixel electrode is disposed near an intersection of each signal line and scanning line, and a pixel array corresponding to digital pixel data. A signal line drive circuit that switches between a side analog pixel voltage and a negative side analog pixel voltage at a predetermined cycle and supplies the signal line to each signal line, wherein the signal line drive circuit includes one horizontal line period. A positive-side voltage generation unit that outputs a plurality of positive-side analog pixel voltages that are different for each divided period for each divided period, and differs for each divided period for each divided period obtained by dividing one horizontal line period into a plurality. Negative voltage generating means for outputting a plurality of negative analog pixel voltages; and a positive analog pixel voltage or the negative voltage on a signal line based on logic of a predetermined bit of the digital pixel data. Voltage supply timing setting means for selecting a timing for supplying a analog pixel voltage from the plurality of divided periods; and an output of the positive side voltage generation means based on a logic of a bit other than the predetermined bit of the digital pixel data. Positive voltage selecting means for selecting an arbitrary voltage; and a negative voltage selecting an arbitrary output voltage of the negative voltage generating means based on a logic of a bit other than the predetermined bit of the digital pixel data. Voltage selection means.

According to a sixth aspect of the present invention, there is provided a pixel array section in which signal lines and scanning lines are arranged in rows and columns, and a pixel electrode is arranged near an intersection of each signal line and scanning line, and a pixel array corresponding to digital pixel data. A signal line drive circuit that switches between a side analog pixel voltage and a negative side analog pixel voltage at a predetermined cycle and supplies the signal line to each signal line, wherein the signal line drive circuit includes one horizontal line period. A positive-side voltage generation unit that outputs a plurality of positive-side analog pixel voltages that are different for each divided period for each divided period, and differs for each divided period for each divided period obtained by dividing one horizontal line period into a plurality. Negative voltage generating means for outputting a plurality of negative analog pixel voltages; and a positive analog pixel voltage or the negative voltage on a signal line based on logic of a predetermined bit of the digital pixel data. Voltage supply timing setting means for selecting a timing for supplying a analog pixel voltage from the plurality of divided periods; and an output of the positive side voltage generation means based on a logic of a bit other than the predetermined bit of the digital pixel data. Positive voltage selecting means for selecting an arbitrary voltage; and a negative voltage selecting an arbitrary output voltage of the negative voltage generating means based on a logic of a bit other than the predetermined bit of the digital pixel data. Voltage selection means.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a display device according to the present invention will be specifically described with reference to the drawings. Hereinafter, a signal line driver circuit in an active matrix liquid crystal display device will be described as an example of a display device.

FIG. 1 is a block diagram showing a detailed configuration of a first embodiment of a signal line driving circuit, and FIG. 2 is a block diagram showing an entire configuration of a liquid crystal display device.

As shown in FIG. 2, in the liquid crystal display device, a signal line and a scanning line are arranged vertically and horizontally, and a pixel electrode connected to an intersection of each signal line and the scanning line via a pixel TFT, and a pixel electrode connected to the pixel electrode. A liquid crystal display unit 1 having a counter electrode to which a counter voltage of a predetermined level is applied, a scanning line driving circuit 2 for driving each scanning line, and a signal line driving circuit 3 for driving each signal line
And a voltage generating circuit 4 for outputting four types of voltages for driving signal lines and a control signal. The voltage generation circuit 4 corresponds to a voltage generation unit.

FIG. 1 shows the configuration of one signal line of the signal line driving circuit 3, and shows an example in which 16-gradation display is performed using 4-bit digital pixel data. Signal line drive circuit 3
Has a shift register 11, a latch circuit 12, a register circuit 13, a comparison circuit 14, a decoder circuit 15, and an analog switch 16 for each signal line. The comparison circuit 14 corresponds to voltage supply timing setting means, and the decoder circuit 15 and the analog switch 16 correspond to voltage supply means.

The latch circuit 12 latches digital pixel data D0 to D3 in synchronization with an output pulse of the shift register 11. At the end of one horizontal line period, the register circuit 13 simultaneously latches the output of the latch circuit 12, that is, the digital pixel data D0 to D3, based on the logic of the load signal LOAD. Of the digital pixel data D0 to D3 latched by the register circuit 13, the upper two bits D2,
D3 is input to the comparison circuit 14, and the lower two bits D0, D1
Is input to the decoder circuit 15.

The comparison circuit 14 includes a voltage generation circuit 4 described later.
The control signals QV0 and QV1 output from the CPU 2 are compared with the upper two bits D2 and D3 of the digital pixel data, and a signal COH indicating the comparison result is output. The decoder circuit 15 includes the comparison circuit 14
If the comparison results match, the decoding result of the lower two bits D0 and D1 of the digital pixel data is output.
More specifically, the decoder circuit 15 sets only one of the four output terminals to a high level based on the decoding result. On the other hand, if the comparison results by the comparison circuit 14 do not match, the decoder circuit 15 sets all outputs to low level. The output voltages Vr0 to Vr3 of the voltage generation circuit 4 are supplied to the analog switches 16, respectively.

FIG. 3 is a block diagram showing a detailed configuration of the voltage generating circuit 4. 3 includes a voltage selection circuit 21, a plurality of resistors R connected in series, and a counter circuit 22. The voltage selection circuit 21 outputs two types of voltages VH and VL (VH> VL) from among five types of voltages V0 to V4 in accordance with the output of the counter circuit 22, that is, (V
1, V0), (V2, V1), (V3, V2), (V4, V3)
Select one of

Between the selection voltages VH and VL, there are four equal resistance values.
Resistors R are connected in series, and a voltage V
r0 to Vr3 are output. The voltages Vr0 to Vr3 are equal to the voltages VH,
When VL is used, it is expressed by the following equations (1) to (4).

Vr0 = VL (1) Vr1 = (3/4) VL + (1/4) VH (2) Vr2 = (1/2) VL + (1/2) VH (3) Vr3 = (1) / 4) VL + (3/4) VH (4) FIG. 4 is a diagram showing the relationship between the output of the counter circuit 22 and the output voltage of the voltage selection circuit 21, and FIG. 5 is a diagram showing the output voltage of the voltage generation circuit 4. It is. Hereinafter, using these figures, FIG.
The operation of the signal line driving circuit 3 will be described. 4 and 5, one horizontal line period is defined as t0 to tB, and one horizontal line period is defined as four divided periods t0 to t1, t1 to t2, and t2.
1 to t3 and t3 to t4. Note that t4 to tB is a flyback period.

During the period from t0 to t1, the outputs QV0 and QV1 of the counter circuit 22 are (0, 0), and the output voltages VH and VL of the voltage selection circuit 21 are (V1, V0). The output voltage of the voltage generation circuit 4 during this period is V0 as shown in FIG.
= Vr0 <Vr1 <Vr2 <Vr3 <V1.

During the period from t1 to t2, the counter output
QV0 and QV1 are (1, 0), and selection voltages VH and VL are (V2, V
1) The output voltage of the voltage generation circuit 4 during this period is V1 = Vr0 <Vr1 <Vr2 <Vr3 as shown in FIG.
<V2.

During the period from t2 to t3, the counter output
QV0 and QV1 are (0, 1), and selection voltages VH and VL are (V3, V
2) The output voltage of the voltage generation circuit 4 during this period is V2 = Vr0 <Vr1 <Vr2 <Vr3 as shown in FIG.
<V3.

During the period from t3 to t4, the counter output
QV0 and QV1 are (1, 1), and selection voltages VH and VL are (V4, V
3) The output voltage of the voltage generation circuit 4 during this period is V3 = Vr0 <Vr1 <Vr2 <Vr3 as shown in FIG.
<V4.

During the period from t0 to t1, the counter outputs QV0 and QV1 are (0, 0). Therefore, when the upper two bits of the digital pixel data are (0, 0), the comparison circuit 14
Output goes high. Therefore, during the period from t0 to t1, a signal voltage is supplied to a signal line included in one horizontal line and corresponding to a pixel whose upper two bits of digital pixel data are (0, 0).

Specifically, the lower two bits of the digital pixel data
When the bit is (0, 0), the analog switch 16 in FIG. 1 is turned on, and the voltage Vr0 is supplied to the signal line. When the lower two bits are (0, 1), the voltage Vr1 becomes
When the lower two bits are (1, 0), the voltage Vr2 is supplied to the signal line, and when the lower two bits are (1, 1), the voltage Vr3 is supplied to the signal line.

Next, during the period from t1 to t2, the counter output
When QV0 and QV1 are (1, 0) and the upper two bits D2 and D3 of the digital pixel data are (1, 0), the comparison circuit 1
4 goes high. Therefore, during the period from t1 to t2, the signal voltage is supplied to the signal line corresponding to the pixel whose upper two bits D2 and D3 of the digital pixel data are (1, 0) included in one horizontal line.

Next, during the period from t2 to t3, the counter output
When QV0 and QV1 are (0, 1) and the upper two bits D2 and D3 of the digital pixel data are (0, 1), the comparison circuit 1
4 goes high. Therefore, during the period from t2 to t3, a signal voltage is supplied to a signal line corresponding to a pixel in which the upper two bits D2 and D3 of digital pixel data included in one horizontal line are (0, 1).

Next, during the period from t3 to t4, the counter output
When QV0 and QV1 are (1, 1) and the upper two bits D2 and D3 of the digital pixel data are (1, 1), the comparison circuit 1
4 goes high. Therefore, during the period from t3 to t4, the signal voltage is supplied to the signal line corresponding to the pixel whose upper two bits D2 and D3 of the digital pixel data are (1,1) included in one horizontal line.

As described above, in the first embodiment, one horizontal line period is divided into a plurality of periods, a voltage range to be supplied to the signal line is set for each divided period, and the upper bit D2 of the digital pixel data is set. , D3, the voltage range is selected by the lower bits D0, D1.
A multi-bit D / A converter is not required, so that power consumption can be reduced and component costs can be reduced. Also,
As compared with the case where reference voltages are provided by the number of gradations of digital pixel data as shown in FIG. 14, the amount of wiring can be reduced and the mounting area can be reduced.

In FIG. 4, the voltage difference between the voltages V0 and V1, the voltage difference between the voltages V1 and V2, the voltage difference between the voltages V2 and V3, and the voltage V
Although an example has been described in which the voltage difference between V3 and V4 is equal, these voltage differences need not necessarily be the same.

For example, FIG. 6 is a diagram showing an example in which the voltage differences between the voltages V0 to V4 are different. In this case, the nonlinear D
/ A conversion is possible, and the analog pixel voltage can be finely adjusted according to the characteristics of the liquid crystal, so that the display quality of the liquid crystal can be improved.

V0, V1, V2, and V3 of the voltage generation circuit 4 are set to 1
By switching between positive and negative every horizontal line period, the so-called H
Line inversion drive is possible, and if switching is performed for each frame, frame inversion drive becomes possible.

FIG. 7 shows digital pixel data D of 6 bits.
FIG. 9 is a block diagram of the signal line driving circuit 3 when inputting 0 to D5 and performing 64 gradation display. In the circuit of FIG. 7, one horizontal line period is divided into eight periods, the division period is selected by the upper three bits D3 to D5 of the digital pixel data, and the output from the voltage generation circuit 4 is performed by the remaining bits D0 to D2. One of the applied voltages Vr0 to Vr7 is selected. This eliminates the need for a high-accuracy and high-speed D / A converter as in FIG.

(Second Embodiment) In a second embodiment, a signal line is driven to be inverted.

FIG. 8 is a block diagram showing a schematic configuration of the second embodiment of the signal line drive circuit. As shown in FIG.
The signal line driving circuit 3a according to the second embodiment includes a positive voltage generating circuit 4a that outputs a positive analog pixel voltage for each of two signal lines corresponding to two adjacent pixels, and a negative analog signal. Negative voltage generating circuit 4 for outputting pixel voltage
b and a switching circuit 31 for selecting one of the outputs of the two voltage generating circuits 4a and 4b.

Here, the positive polarity is defined as a positive voltage with respect to the common electrode voltage of the liquid crystal panel, and the negative polarity is defined as a negative voltage.

The signal line driving circuit 3a in FIG. 8 drives each signal line by a so-called V-line inversion method in which the voltage polarity is inverted for each vertical line. In the V-line inversion method, as shown in FIG. 9, the polarity of the analog pixel voltage is switched for each line adjacent in the vertical direction (vertical direction).

For example, when the analog pixel voltage on the positive side is supplied to the signal line S1 in FIG.
Is supplied with a negative analog pixel voltage. In the next frame (screen), a negative analog pixel voltage is supplied to the signal line S1 in FIG. 9, and a positive analog pixel voltage is supplied to the adjacent signal line S2.

FIG. 10 is a block diagram showing a detailed configuration of the signal line drive circuit 3a, and shows a configuration for two signal lines corresponding to two adjacent pixels. In the switching circuit 31, two pairs (Q1, Q2) and (Q3, Q4) of a pair of an NMOS transistor and a PMOS transistor are provided. The source terminals of both transistors of each set are connected to corresponding signal lines, the polarity selection signal POL is applied to the gate terminals of both transistors Q1 and Q2 of one set, and the transistors Q3 and Q4 of the other set are connected. A polarity selection signal POLI is applied to the gate terminal.

The positive voltage generation circuit 4a has a shift register 11, a latch circuit 12, a register circuit 13, a comparison circuit 14, a decoder circuit 15, and an analog switch including PMOS transistors Q21 to Q24. Further, the negative voltage generation circuit 4b includes a shift register 11
, A latch circuit 12, a register circuit 13, a comparison circuit 14, a decoder circuit 15, and NMOS transistors Q11 to Q11.
Q14.

The NMOS transistors Q11 to Q14 correspond to negative voltage selection means, and the PMOS transistors Q21 to Q24 correspond to positive voltage selection means.

The source terminals of the NMOS transistors Q11 to Q14 forming the analog switch are connected to the NMOS transistors in the switching circuit 31.
NM is connected to the drain terminals of transistors Q1 and Q3.
The gate terminals of the OS transistors Q11 to Q14 are connected to the output terminal of the decoder circuit 15, and the NMOS transistors Q11 to Q14
Output voltages V10 to V13 of a voltage generation circuit 4 described later are applied to the drain terminal of Q14.

On the other hand, the source terminals of the PMOS transistors Q21 to Q24 forming the analog switch are connected to the drain terminals of the PMOS transistors Q2 to Q4 in the switching circuit 31, and the gate terminals of the PMOS transistors Q21 to Q24 are connected to the inverters IV1 to IV4. An output terminal of the PMOS transistor Q21 to Q24 is connected to an output terminal of the decoder circuit 15 via an IV4.
Is applied.

FIG. 11 is a block diagram showing a detailed configuration of the voltage generation circuit 4. As shown, the voltage generation circuit 4
It has a positive side voltage selection circuit 41, a negative side voltage selection circuit 42, a counter circuit 43, and a resistor R.

The positive voltage selection circuit 41 and the resistor R connected thereto correspond to positive voltage generating means, and the negative voltage selecting circuit 42 and the resistor R connected thereto correspond to negative voltage generating means. Further, the positive voltage selection circuit 41 corresponds to first voltage generation means, the resistor R connected to the positive voltage selection circuit 41 corresponds to first resistance division means, and the negative voltage selection circuit 4
2 corresponds to a second voltage generating means, and is a negative voltage selection circuit 4
The resistor R connected to 2 corresponds to a second resistor dividing unit.

The positive-side voltage selection circuit 41 includes a counter circuit 4
Based on the count value of 3, two voltages V0H and V0L are selected from the voltages V0 to V4, and voltages V00 to V03 obtained by dividing these voltages V0H and V0L by a resistor R are output. Similarly, the negative-side voltage selection circuit 42 selects two voltages V1H and V1L from the voltages -V0 to -V4 based on the count value of the counter circuit 43, and connects these voltages V1H and V1L with a resistor R. The divided voltages V10 to V13 are output.

FIG. 12 is a diagram showing the output voltage of the voltage generation circuit 4, wherein (a) shows the positive analog pixel voltage,
(B) shows the negative side analog pixel voltage. Hereinafter, the operation of the signal line driving circuit 3a according to the second embodiment shown in FIG. 10 will be described with reference to FIG. In FIG. 12, one horizontal line period is defined as t0 to t1, t1 to t2, t2 to t3, and t3 to t4.
Divided.

In the period from t0 to t1 in FIG. 12, the outputs QV0 and QV1 of the counter circuit 43 are (0, 0), and the voltage generation circuit 4 outputs positive signal voltages V00 to V03 (where V0 =
V00 <V01 <V02 <V03 <V1) and the negative signal voltage V10
-V13 (-V0 = V10>V11>V12>V13>-
V1) is output.

During this period, when the upper two bits of the digital pixel data are (0, 0), the comparison circuit 14 outputs a signal indicating that the comparison results match. The decoder circuit 15 decodes digital pixel data whose upper two bits are (0, 0), and based on the decoding result.
One of the NMOS transistors Q11 to Q14 is turned on.

For example, in FIG. 10, the polarity switching signal PO
When L is at a high level and POLI is at a low level, the NMOS transistor Q1 in the switching circuit 31 is turned on, and the drain voltage of the on-state NMOS transistor among the NMOS transistors Q11 to Q14 is supplied to the signal line S1. Is done. On the other hand, in the adjacent signal line S2, the PMOS transistor Q4 in the switching circuit 31 is turned on, and the PMOS transistors Q21 to Q24 are turned on.
Among them, the drain voltage of the PMOS transistor in the ON state is supplied to the signal line S2. That is, the signal lines S1 and S2 have opposite voltage polarities.

Next, during the period from t1 to t2 shown in FIG.
The outputs QV0 and QV1 of the counter become (1, 0), and the voltage generating circuit 4 outputs positive signal voltages V00 to V03 (where V1
= V00 <V01 <V02 <V03 <V2) and the negative signal voltage V1
0 to V13 (-V1 = V10>V11>V12>V13>-
V2) is output.

Next, during the period from t2 to t3, the outputs QV0 and QV1 of the counter become (0, 1), and the voltage generating circuit 4 outputs positive signal voltages V00 to V03 (where V2 ≦ V00 <). V0
1 <V02 <V03 <V3) and negative-side signal voltages V10 to V13 (where -V2 = V10>V11>V12>V13> -V3) are output.

Next, during the period from t3 to t4, the outputs QV0 and QV1 of the counter become (1, 0), and the voltage generation circuit 4 outputs positive signal voltages V00 to V03 (where V3 ≦ V00 <). V0
1 <V02 <V03 <V4) and negative signal voltages V10 to V13 (where -V3 = V10>V11>V12>V13> -V4) are output.

The polarity selection signals POL, POLI are provided for each frame.
Are reversed, the polarities of the signal lines S1 and S2 are reversed.

By the way, a 12.1 inch screen size XG
The size per pixel of the A panel substrate is about 80 × 240μm
² , the positive polarity voltage generation circuit 4 shown in FIG.
a, the negative polarity voltage generation circuit 4b, and the switching circuit 31
It is desirable to fit within a width of about 80 μm ² . Therefore, FIG.
As shown in (1), it is desirable to arrange the positive voltage generating circuit 4a, the negative voltage generating circuit 4b, and the switching circuit 31 in a line along the longitudinal direction of each signal line.

As described above, in the second embodiment, the switching circuit 31, the positive voltage generating circuit 4a, and the negative voltage generating circuit 4b are provided for every two signal lines corresponding to two adjacent pixels.
In each voltage generation circuit 4, one horizontal line period is divided into a plurality of periods, a voltage range to be supplied to the signal line is set for each divided period, and the display is performed by the upper bits of the digital pixel data. Since the division period and the voltage range to be performed are selected, the circuit scale can be reduced, the power consumption can be reduced, and the cost can be reduced, as in the first embodiment, as compared with the case where the digital pixel data is directly D / A converted. Becomes possible. Further, inversion driving can be performed without complicating the circuit configuration.

In the second embodiment, the voltage difference between the voltages output from the voltage generation circuit 4 does not need to be the same. There is no particular limitation on the number of bits of digital pixel data.

In the first and second embodiments, an example has been described in which one horizontal line period is divided into four periods, but the number of divisions is not limited to four. For example, when dividing one horizontal line period into n (n is an integer of 2 or more), (n + 1) types of voltages Vm (where m = 1 , 2, ..., n, (n + 1), and input Vm <Vm + 1)
It is only necessary to select two types of voltages from these voltages and divide the resistance.

In the second embodiment, an example in which the V line inversion drive is performed has been described. However, if the polarity selection signals POL and POLI are inverted every horizontal line period, dot inversion drive is performed.

[0061]

As described above in detail, according to the present invention, one horizontal line period is divided into a plurality of periods, the voltage range to be supplied to the signal line is set for each divided period, and the digital pixel period is set. Since the division period is set by a predetermined upper bit of data and a predetermined voltage in a selected voltage range is supplied to a signal line by other bits, a multi-bit D / A converter becomes unnecessary. Power consumption can be reduced and component costs can be reduced. Further, since there is no need to provide a large number of reference voltage lines, the amount of wiring can be reduced and the circuit scale can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a detailed configuration of a first embodiment of a signal line driving circuit.

FIG. 2 is a block diagram illustrating the overall configuration of a liquid crystal display device.

FIG. 3 is a block diagram showing a detailed configuration of a voltage generation circuit.

FIG. 4 is a diagram illustrating a relationship between an output of a counter circuit and an output voltage of a voltage selection circuit.

FIG. 5 is a diagram illustrating an output voltage of a voltage generation circuit.

FIG. 6 is a diagram illustrating an example in which a voltage difference between input voltages of a voltage generation circuit is not constant.

FIG. 7 is a block diagram of a signal line driver circuit for performing 64-gradation display.

FIG. 8 is a block diagram illustrating a schematic configuration of a signal line driving circuit according to a second embodiment;

FIG. 9 is a diagram illustrating V-line inversion driving.

FIG. 10 is a block diagram showing a detailed configuration of a second embodiment of the signal line driving circuit.

FIG. 11 is a block diagram showing a detailed configuration of a voltage generation circuit.

FIG. 12 is a diagram illustrating an output voltage of a voltage generation circuit.

FIG. 13 is a view for explaining an outline of a conventional analog sample hold system.

FIG. 14 is a schematic configuration diagram of a drive circuit in which a conventional analog sample-and-hold system is improved.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Liquid crystal display part 2 Scan line drive circuit 3 Signal line drive circuit 4 Voltage generation circuit 11 Shift register 12 Latch circuit 13 Register circuit 14 Comparison circuit 15 Decoder circuit 16 Analog switch 21 Voltage selection circuit 22 Counter circuit

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 2H093 NA16 NA32 NA33 NA53 NC03 NC13 NC21 NC22 NC23 NC25 NC26 NC27 NC34 ND06 ND39 ND49 ND54 5C006 AA16 AC04 AC27 AC28 AF42 AF44 AF51 AF71 BB14 BB16 BC03 BC13 BC16 BF03 BF04 BF11 BF11 BF11 BF04 BF27 BF32 BF34 BF43 FA42 FA47 FA52 FA56

Claims (9)

[Claims] 1. A pixel array in which signal lines and scanning lines are arranged in rows and columns, and each pixel line includes a pixel electrode connected to an intersection of each signal line and scanning line via a switching element, and a counter electrode facing the pixel electrode. And a signal line driving circuit that supplies an analog pixel voltage corresponding to digital pixel data to each signal line, wherein the signal line driving circuit is configured to divide one horizontal line period into a plurality. Voltage generating means for outputting a plurality of voltages by switching their voltage ranges in synchronization with a period; and a plurality of timings for supplying an analog pixel voltage to a signal line based on a logic of a predetermined bit in the digital pixel data. A voltage supply timing setting unit that selects from among the divided periods; and, based on a logic of a bit other than the predetermined bit of the digital pixel data, Select multiple arbitrary voltage outputted from the voltage generating unit, and voltage supply means for supplying a corresponding signal line, characterized in that it has a display device. 2. The voltage generation circuit according to claim 1, wherein said voltage generation means switches an arbitrary input voltage pair from a plurality of input voltages in synchronization with each of said divided periods. The display device according to claim 1, further comprising a voltage dividing circuit that outputs a plurality of voltages obtained by dividing a voltage between input voltages. 3. The voltage selection circuit according to claim 2, wherein the voltage selection circuit selects an input voltage pair having the closest level from the input voltages, and selects a different input voltage pair in each of the divided periods. Item 3. The display device according to Item 2. 4. The display device according to claim 3, wherein said voltage selection circuit sequentially selects said input voltage pair from a low level to a high level side of said input voltage. 5. The display device according to claim 1, wherein the polarity of the output voltage group of the voltage generation means with respect to the voltage applied to the counter voltage is switched in one horizontal line period or one frame period. 6. A pixel array section in which signal lines and scanning lines are arranged vertically and horizontally, and a pixel electrode is arranged near an intersection of each signal line and scanning line; and a positive analog pixel voltage corresponding to digital pixel data; A signal line driving circuit for switching the negative analog pixel voltage at a predetermined cycle and supplying the signal line to each signal line, wherein the signal line driving circuit divides one horizontal line period into a plurality. Positive voltage generating means for outputting a plurality of positive analog pixel voltages different for each divided period for each period; and a plurality of negative analog signals different for each divided period for each divided period obtained by dividing one horizontal line period into a plurality. Negative voltage generating means for outputting a pixel voltage; and a positive analog pixel voltage or the negative analog pixel voltage applied to a signal line based on a logic of a predetermined bit of the digital pixel data. Voltage supply timing setting means for selecting a supply timing from among the plurality of divided periods; and an arbitrary output voltage of the positive side voltage generation means based on a logic of a bit other than the predetermined bit of the digital pixel data. Positive voltage selecting means for selecting a voltage of the digital pixel data, and negative voltage selecting means for selecting an arbitrary voltage of the output voltage of the negative voltage generating means based on a logic of a bit other than the predetermined bit of the digital pixel data. A display device comprising: 7. The positive voltage selection means and the negative voltage selection means are alternately arranged to form a plurality of voltage selection means pairs, and the output of the positive voltage selection means of each of the voltage selection means pairs is The two adjacent signal lines are connected via p-ch transistors, respectively, and the output of the negative voltage selection means is connected to the two adjacent signal lines via n-ch transistors. The display device according to claim 6. 8. The p-ch transistor and the n-ch transistor connected to each of the signal lines alternately conduct in one frame cycle or one horizontal line period, and connect the two adjacent signal lines. 8. The display device according to claim 7, wherein transistors of the same conductivity type connected to each other are turned on alternately every one horizontal line period. 9. The positive-side voltage generating means includes: first voltage generating means for outputting a high-low reference voltage having a different voltage level for each of the divided periods; A first voltage divider for outputting a positive analog pixel voltage; a second voltage generator for outputting a high / low reference voltage having a different voltage level for each of the divided periods; 7. The display device according to claim 6, further comprising: a second voltage divider that divides the voltage between the high and low reference voltages and outputs the plurality of negative analog pixel voltages.