JPH09138670A - Driving circuit for liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a chip area by varying a level of a reference voltage with on/off operation of a pair of switch elements provided on both ends of a dividing resistor. SOLUTION: A resistor division means 20 of a staircase voltage generation part 2 generating a staircase voltage based on plural reference voltages Vr0-Vrk outputted from an optional reference power source part 7 divides between respective reference power sources of plural reference voltages Vr0-Vrk by plural dividing resistors. Then, staircase voltage level switch means 22 consisting of sets of a pair of switch elements are provided on respective both ends of plural dividing resistors, and switch the levels of the staircase voltages. Further, by a control signal controlling the operation of pairs of switch elements, one sides of pairs of switch elements provided on respective both ends are made a conductive state in a first period, and the staircase voltage is generated by making both sides of pairs of switch elements the conductive state in a second period.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display panel of an arbitrary display device such as a liquid crystal display device (usually LCD (Li
abbreviated as quid Crystal Display Device)] A liquid crystal display for supplying an analog drive voltage for displaying target image data to a selected pixel among a plurality of pixels constituting a liquid crystal display panel. The present invention relates to a drive circuit of a device or the like.

In particular, the present invention relates to a plurality of parallel first bus lines (generally called scan bus lines) for sequentially scanning the pixels and the first bus lines.
At a crossing point with a second bus line (generally called a data bus line) that is orthogonal to the bus line of FIG. 2 and supplies a drive voltage (grayscale voltage) of image data according to the gradation to be displayed. TFT connected to the pixel of the arranged liquid crystal cell
The present invention relates to an active matrix type liquid crystal display device for performing gradation display by writing image data into a pixel to be selected by utilizing on / off operation of a switching element such as (Thin Film Transistor).

An active matrix type liquid crystal display device in which each pixel is provided with a switching element as described above is a CR
It has a display quality not inferior to T (Cathode-Ray Tube) and can easily realize a thin and lightweight flat panel display.
It is expected that the device will be widely used as a display device. That is, with the diversification of information means and the development of the multimedia industry, there is a demand for an active matrix type liquid crystal display device having both rich expressive power and portability.

In other words, in the active matrix type liquid crystal display device, not only the portable information equipment such as the notebook type personal computer but also the multimedia information equipment can be used by making use of the above-mentioned characteristics of thinness and lightness. This is required, and as one of them, multi-gradation display capability of 64 gradations or more is required. Therefore, the liquid crystal display device of the above type requires a drive circuit suitable for multi-gradation display, which can generate as many gradation voltages as possible.

In order to meet the demand for such a driving circuit, it is required to increase the number of gradations in the integrated circuit (driver IC) of the driving circuit for driving the active matrix type liquid crystal display device. The multi-gradation of ICs leads to an increase in chip area, which leads to an increase in price.

[0006]

2. Description of the Related Art Here, first, a configuration of a liquid crystal display panel of an active matrix type liquid crystal display device having a high display quality among flat panel displays will be described with reference to FIG. FIG. 22 is a plan view showing a simplified panel configuration of a general liquid crystal display device. However, in FIG. 22, the configuration of the liquid crystal display panel 9 when performing multi-gradation display and color display is illustrated.

In the liquid crystal display panel shown in FIG. 22,
A first direction (eg, Y or row direction), and
Electrodes E11 to Enm for color display are arranged in a matrix in a second direction (for example, the X direction or the column direction) orthogonal to the first direction (n and m are arbitrary integers, here, E
Pixels having up to 36) are arranged. Pixels having electrodes E11 to Enm for color display are R
(Red: red), G (Green: green) and B (Blue:
It is composed of three types of pixels using color filters for each blue color. Each of these has a structure in which liquid crystal is sealed between a substrate to which switching elements T11 to T36 such as TFTs are connected and a substrate on which a common electrode is uniformly wound. Here, the former substrate is TFT
The substrate and the latter substrate are called a common substrate. FIG.
As shown in FIG. 5, on the TFT substrate, scan bus lines (also called scan bus lines) Y1 to Yn as first bus lines and data bus lines (also called signal bus lines) as second bus lines. X1
Xm intersects in a matrix, and the switching elements T11 to T11 are provided at respective positions of intersections of these two types of bus lines.
A plurality of TFTs as T36 are connected.

Further, in FIG. 22, the TFTs in the row selected by the scan bus line are turned on (on).
Thus, the video signal voltage applied to the data bus line is written in the electrode of each pixel. After that, by using the distributed capacitance of the data bus line to hold the charge, the written information is held until the next row is selected. Since the tilt of the liquid crystal molecules in the pixel is determined in accordance with the information held in this way, the amount of light transmission can be controlled according to the degree of the tilt, and gradation display is possible. Furthermore, when performing color display,
Light is mixed by using three kinds of R, G and B color filters.

Peripheral circuits for driving the liquid crystal display device,
That is, the drive circuit includes a data driver section connected to the data bus line side (sometimes simply referred to as a data driver) and a scan driver section connected to the scan bus line side (simply referred to as a scan driver). Sometimes there are). When an ON voltage for turning on the TFT is output from the scan driver unit, a voltage corresponding to the video signal is applied to the selected pixel through the data driver. The information written in the electrode of each selected pixel is held until the next row is selected, as described above. Since the tilt of the liquid crystal is determined according to the held information, the amount of light transmission can be controlled, and gradation display can be performed.

In a general liquid crystal display device, alternating current drive is required to prevent deterioration of the liquid crystal itself, and positive and negative voltages are applied with a common electrode potential as a reference in every constant period. Further, in order to suppress the flicker of the screen of the liquid crystal display panel caused by the fluctuation of the pixel potential due to the influence of the stray capacitance in the peripheral portion of the TFT, line inversion drive in the data bus line direction or the scan bus line direction is performed. . Further, in order to suppress the amplitude range of the data voltage supplied from the data driver section to the TFT substrate within 5 V, for example, the common inversion drive is performed in which the power source of the data driver section is a single 5 V power source. In this common inversion drive, the common voltage to be applied to the common electrode is changed according to the polarity inversion cycle.

Next, referring to FIGS. 23 to 26,
A conventional example of a drive circuit of an active matrix type liquid crystal display device using a switching element such as a TFT will be described. FIG. 23 is a circuit block diagram showing the configuration of a drive circuit of a conventional liquid crystal display device, FIG. 24 is a timing chart for explaining the operation of FIG. 23, and FIG. 25 is a configuration example of a conventional grayscale voltage generation unit. And FIG. 26 are circuit diagrams showing the relationship between the conventional grayscale voltage generating section and the analog switch section.

However, FIG. 23 shows a schematic configuration of a data driver section related to the present invention in the drive circuit of the liquid crystal display device. The operation of the conventional data driver unit shown in FIG. 23 is performed by a shift clock CLKD which is a timing signal given in synchronization with image data,
A digital display data signal (also called a video signal) RDATA (red) that represents image data for color display,
It is controlled by GDATA (green) and BDATA (blue), a start pulse SPD that determines the start of fetching these display data signals, and a latch pulse LP that determines the switching timing of the display data signal output. The various signals described above are generated by a control circuit unit (not shown here) or the like. In this control circuit section,
A horizontal synchronizing signal HSYNC indicating a horizontal scanning period when the image data is scanned in the direction of the data bus line and displayed is also generated. The configuration and operation of a conventional data driver unit will be described with reference to the timing chart of FIG. 24 together with the circuit block diagram of FIG.

Reference numeral 600 in FIG. 23 represents a shift register circuit section including a shift register. In the shift register circuit section 600, a start pulse SP indicating the start of fetching the display data signal for each line (one row)
D and the register advance clock CLKD are 1
When sent out from the control circuit or the like line by line, the data fetch signals S1 to S64 for sequentially writing the display data signal in the first digital memory 610 are generated. That is, the shift register circuit unit 6 is driven by the start pulse SPD which is one pulse in one horizontal scanning period.
The operation of the shift register in 00 starts. The display data signal RDA is generated by the data capture signals S1 to S64 generated inside the shift register of the data driver unit.
TA, GDATA, and BDATA are sequentially loaded into the first digital memory 610. Here, FIG.
As shown in, the display data signals RDATA, GDATA
And BDATA are video data for one line (for example, 640 video data) RE1 to RE64, respectively.
0 (red image data is represented as RE1 to RE640 in order to distinguish it from a resistor R1 and the like which will be described later), G1 to
G640, and B1-B640 are included.

When the shift register circuit section 600 finishes the data fetch of the data driver section itself, the data fetch signal SOUT (S) for the data driver of the next stage.
64) is output and the cascade operation is performed. Further, when the acquisition of the video data for one line is completed, the information in the first digital memory 610 is transferred to the second digital memory 620 by the latch pulse LP. The video data transferred to the second digital memory 620 is decoded pixel by pixel in the decoder 630. In addition,
The decoder 630 has a second digital memory 620.
It can also be built into.

Further, in accordance with the result of decoding by the decoder 630, the analog switch section 800 including a set of analog switches in the next stage has a plurality of voltages V0 to V0.
One of 63 (for example, for 64 gradations) is selected. These voltages V0 to V63 are created by dividing a plurality of types (for example, nine types) of reference power sources Vr0 to Vr8 input from the outside by the gradation voltage generating unit 200 including a plurality of dividing resistors. This gradation voltage generation unit 200
Has a function as a resistance array type analog / digital (D / A) converter composed of a plurality of divided resistors. Then, finally, the gradation voltage corresponding to the gradation data of the channels of the data driver [for example, 192 channels (ch)] is output from the analog switch unit 800.

FIG. 25 shows an example of the configuration of the gradation voltage generating section 200. By the resistor array including the plurality of resistors R1 to R64 provided in the gradation voltage generating unit 200,
Voltages V0 to V63 corresponding to 64 voltage levels are generated from nine types of reference power supplies Vr0 to Vr8 input from the outside. In this case, in order to select one corresponding to the data held in the second digital memory 620, 64 analog switches are provided for each channel at each output of the data driver unit, In the case of 192 channels (ch), 64 × 192 = 12288 analog switches are required.

FIG. 26 shows the relationship between the conventional gradation voltage generating section 200 and the analog switch section 800. FIG. 26 shows 6
This is a conventional example for realizing 4-gradation display, and the input reference power source is Vr0 to Vr8 9 as in FIG. 25 described above.
Kind. Here, using 64 resistors, Vr0
Between Vr1, between Vr1 and Vr2, between Vr2 and Vr3, ... V
Each of r7 and Vr8 is divided into eight equal parts. Here, for example, gradation voltages of voltages V0 to V63 are generated, and the voltage level selected by the decoder or the analog switch unit is output. Therefore, by using the grayscale voltage generation unit 200 and the analog switch unit 800 of FIG.
= 64 gradation display is possible.

[0018]

As described above, in the drive circuit of the conventional liquid crystal display device, the data driver unit corresponding to the output for multi-gradation display has the analog switch for selecting the gradation voltage. I need. Therefore, as the number of gradations to be displayed increases, there arises a problem that the chip area of the driver IC becomes large when the drive circuit including the data driver section is formed by the driver IC.

In other words, the conventional resistor array type D / A
In the multi-gradation display method using the converter, the number of gradations can be increased with a small number of reference power sources, but on the other hand, the number of switches such as analog switches for selecting the gradation voltage is required for the gradations. The chip area of
Further, as the number of reference power sources running inside the chip increases, there arises a problem that the chip area increases.

The present invention has been made in view of the above problems, and significantly reduces the number of analog switches and the like for selecting the gradation voltage required for each output of the data driver unit to reduce the chip area, and It is an object of the present invention to provide a drive circuit for a liquid crystal display device or the like that can reduce the chip area by reducing the number of wires of a reference power source running inside the chip as compared with the conventional case.

[0021]

FIG. 1 is a block diagram showing a first principle configuration of the present invention. Hereinafter, the same components as those described above will be denoted by the same reference numerals. As shown in the first principle diagram of FIG. 1, in the present invention, a plurality of first bus lines (for example, a scan) for scanning a plurality of pixels forming the liquid crystal display panel 9 are scanned. Bus line Y1
Yn) and a gradation voltage (for example, voltage V0, ... Vw, ... Vz) on which a step voltage for displaying predetermined image data is superimposed on the selected pixels on these first bus lines. The target is a drive circuit of the liquid crystal display device 1 in which a plurality of second bus lines (for example, data bus lines X1 to Xm) that are parallel to each other are arranged.

In order to solve the above-mentioned problems, the driving circuit according to the first principle of the present invention uses a staircase that generates the staircase voltage based on a plurality of reference power supplies Vr0 to Vrk output from an arbitrary reference power supply unit 7. The voltage generator 2 is provided. The staircase voltage generator 2 is provided at both ends of each of the plurality of reference resistors Vr0 to Vrk, and the resistance voltage dividing means 20 for dividing the reference power sources Vr0 to Vrk by the plurality of dividing resistors. A step voltage level switching unit 22 including a set of a pair of switch elements for switching the step voltage level is included. Further, in the first period, one of the pair of switch elements provided at both ends of each of the plurality of division resistors is brought into a conductive state by the control signal for controlling the operation of the pair of switch elements, and the second period is set. Then, the staircase voltage is generated by bringing both of the pair of switch elements into a conductive state.

Preferably, the drive circuit according to the first principle of the present invention includes a control circuit section 5 for controlling the timing of scanning a plurality of pixels and the timing of displaying image data on the selected pixels. The gradation voltage selecting section 8 selects the gradation voltage corresponding to the image data and supplies the gradation voltage to the second bus line by superimposing the step voltages generated by the step voltage generating section 2.

The control signal Scs generated by the control circuit section 5 causes the switch element in the staircase voltage level switching means 22 to be in a conductive state or a non-conductive state to switch the staircase voltage, and the staircase voltage. It is determined whether to enable the output of the. further,
In FIG. 1, the image data is decoded to generate image data signals St1 to Stm for each second bus line, and the display timing of the image data signal is finally determined based on the control signal Sct from the control circuit unit 5. A display data signal timing setting unit 6 for setting is provided.

Further, in FIG. 1, a scan driver unit 10 for supplying a voltage for scanning a pixel is provided for each line of the first bus line. The scanning timing of each line by the scan driver unit 10 is determined by the control signal Scy from the control circuit unit 5. More preferably, the drive circuit according to the first principle of the present invention includes the control circuit unit 5 and the grayscale voltage selection unit 8 described above.
In addition to the above, a timing control unit is provided for controlling the timing of switching the staircase voltage by setting the switch element in the staircase voltage level switching means 22 to the conducting state or the non-conducting state. The timing control unit has a function of generating a signal for controlling the timing of switching the staircase voltage based on a control signal from the control circuit unit 5 for determining whether to enable the output of the staircase voltage. Have.

More preferably, in the drive circuit according to the first principle of the present invention, an output buffer section including a plurality of buffer amplifiers is provided between the step voltage generation section 2 and the gradation voltage selection section 8. There is. More preferably, in the drive circuit according to the first principle of the present invention, the final stage buffer section including a plurality of buffer amplifiers is provided at the final stage on the output side of the gradation voltage selection section 8.

FIG. 2 is a block diagram showing the second principle configuration of the present invention. The configurations of the control circuit unit 5, the display data signal timing setting unit 6, the reference voltage selection control unit 7, the gradation voltage selection unit 8, and the scan driver unit 10 in the drive circuit of FIG. 2 are the same as the configurations of FIG. 1 described above. Therefore, the description thereof will be omitted here. As shown in FIG. 2, the drive circuit according to the second principle of the present invention includes a plurality of reference power supplies Vr0 to Vr output from an arbitrary reference power supply unit 7.
Based on k, a reference voltage generator 3 is provided for generating a plurality of reference voltages according to the types of the gradation voltages. The reference voltage generator 3 divides each of the plurality of reference power sources Vr0 to Vrk into a plurality of dividing resistors for taking out a plurality of reference voltages, and a plurality of dividing resistors. And a reference voltage level changing unit 33 including a plurality of switch elements that are connected to each other and change the level of the reference voltage extracted from each of the plurality of divided resistors. Further, the staircase voltage is generated by combining the plurality of dividing resistors and the plurality of switch elements with a control signal Scp for controlling the operation of the plurality of switch elements.

Preferably, the drive circuit according to the second principle of the present invention includes a resistor array for dividing the plurality of digital output voltages from the reference voltage level changing means 33 to generate the gray scale voltage. A D / A converter section 38 is provided. Further, the reference voltage level changing means 33 and D
The input buffer unit 35 is provided between the A / A converter unit 38 and the A / A converter unit 38 in order to prevent the voltage levels of the voltages V0 to Vz from varying due to the on / off operation of the plurality of switch elements in the reference voltage level changing unit 33. Can be provided.

Further, preferably, in the drive circuit according to the second principle of the present invention, the reference voltage generating section 3 is formed inside the integrated circuit.

[0030]

3 and 4 show a first embodiment of the present invention.
3 is a circuit diagram (No. 1 and No. 2) showing a simplified staircase voltage generation circuit for explaining the principle of FIG. In the staircase voltage generator shown in FIG. 3, in order to simplify the explanation,
Two reference power sources of the reference power source unit 7 (first reference power source Vr0
A case where 16 voltage levels (voltages V0 to V15) are generated from the second reference power supply Vr1) will be described as an example. Between the first reference power supply Vr0 and the second reference power supply Vr1,
The voltage is divided by the eight dividing resistors forming the resistance voltage dividing means 20, that is, the resistors R1 to R8 for voltage division. Further, switch elements (lower switch elements 2d-1 to 2d-8 and upper switch elements) having the same resistance value in the ON state (hereinafter abbreviated as ON resistance value) are provided at both ends of each resistor. 2u-1 to 2u-8) are connected to each other in pairs, and a staircase voltage level switching means 22 is formed by a set of these paired switch elements. One terminals of the pair of switch elements are connected to each other and are in a short circuit state.

As shown in the simplified equivalent circuit of FIG.
The operation of the pair of switch elements consists of two periods (phases), and in the first phase, only the switch elements in the lower stage of the switch elements provided at both ends of each resistor are in the ON state (in the upper stage). The switch element is in the off state), and the voltages V0, V2, V4 divided by the resistors are
V6, V8, V10, V12, and V14 are output. On the other hand, in the second phase, both the upper switch element and the lower switch element in the switch elements provided at both ends of each resistor are turned on, and the voltage divided by each resistor is switched to the switch element. Voltage V1, V3, V5, V7, V in the state of being further divided by the ON resistance value of
9, V11, V13, and V15 are output. Here, if the voltage level of the output voltage output from the lower stage of an arbitrary resistor is V _N (single output) and the voltage level of the output voltage output from the upper stage of the same resistor is V _{N + 2} , 1
The voltage level of the output voltage in the phase is represented by V _N ,
The voltage level of the output voltage in the second phase is (V _N + V
_{N + 2} ) / 2 (partial pressure output) (where N is an arbitrary integer).

In the drive circuit according to the first principle of the present invention,
By switching the above two phases within one horizontal period, it becomes possible to easily generate the staircase voltage. By utilizing the gradation voltage on which the staircase voltage is superimposed and the distributed capacitance of the data bus line, the kind of gradation voltage supplied to the gradation voltage selection unit 8 including a plurality of analog switches is Cut in half.

In other words, according to the drive circuit according to the first principle of the present invention, the staircase voltage can be generated by switching the two phases of the voltage division by the resistance and the voltage division by the switch element. The voltage generator is provided in the data driver. Therefore, the number of the grayscale voltage selecting analog switches for each output of the data driver unit is about half that of the conventional one, so that the chip area of the driver IC can be reduced.

5 to 7 are diagrams showing the configuration and operation of the reference voltage generator 3 for explaining the second principle of the present invention. More specifically, FIG. 5 is a circuit diagram showing an embodiment of the invention according to the second principle of the present invention, and FIG.
FIG. 7 is a circuit diagram showing another embodiment of the invention according to the second principle of the present invention, and FIG. 7 is a timing chart for explaining the operation of FIG.

In the drive circuit according to the second principle of the present invention,
In the input section of the gradation voltage generating section (see FIG. 23, for example), the reference voltage level is changed by combining a plurality of different resistors and switches. When the level of the reference voltage is changed, it is necessary to use the distributed capacitance of the data bus line as the voltage holding means. That is, here, different voltage values are created by changing the voltage level of the reference power supply input to the data driver unit by combining a plurality of different resistors and a plurality of switch elements. Further, in the drive circuit according to the second principle of the present invention, a reference voltage created based on a combination of a plurality of different resistors and switches and a distributed capacitance of the data bus line is used as a resistor array type D / A converter. By combining them, multi-tone display can be realized.

In the example of the reference voltage generator 3 shown in FIG. 5, different resistance values r, 1 are provided between the respective potentials of the reference power supplies Vr0, Vr1, Vr2 and Vr3 to be input.
Two resistors (resistors R1-1 and R1-
2, R2-1 and R2-2, and R3-1 and R3-2) and two switch elements (switch element 31
-1 and 31-2, 32-1 and 32-2, and 33-1 and 33-2) to create two voltage levels from between the potentials of the reference power source. The resistors R1-1 to R3-2 are the dividing resistance means 3
0, and the switch elements 31-1 to 33-2 form the reference voltage level switching means 33. Further, in order to prevent the ON / OFF operation of the switch elements 31-1 to 33-2 from affecting the level change of the gradation voltage, one terminal of the switch elements 31-1 to 33-2 is Buffer amplifiers 35-1 to 35 in units of two switch elements
-3. These buffer amplifiers 35-
1-35-3 form the input buffer unit 35.

In the reference voltage generating section of FIG. 5 described above, the ratio of the resistance values of the two dividing resistors between the reference power sources is set to 1:15. This reference voltage generating section will be described later. 21 shows a configuration example when used in the twenty-first embodiment. On the other hand, in the example of the reference voltage generator 3 shown in FIG. 6, four resistors (resistors R1-1 and R1) having resistance values r, r, r and 29r are provided between the respective potentials of the input reference power source. ~ R1-
4 and R2-1 to R2-4) and four pairs of switch elements (switch elements 31-1 to 31-4 and 32-1).
32-4) and partial pressure. With such a configuration, four types of voltage levels can be created between the potentials of the reference power source. Furthermore, by changing the resistance ratio in accordance with the number of gradations and the number of input reference power supplies, it is possible to create many types of voltage levels using a small number of reference power supplies.

Further, as shown in the timing chart of FIG. 7, the control signal TP (corresponding to the control signal Scp of FIG. 2) causes the switch elements 31-1 to 33-1 and 31-2 to 33- of FIG. 2 simultaneously turns on and off. The voltage V is applied while the switch elements 31-1 to 33-1 are on (the switch elements 31-2 to 33-2 are off).
The voltage levels of r0, Vr1, and Vr2 are VR0, V
R1 and VR2, and switch elements 31-2 to 3-3
During a period in which 3-2 is on (switch elements 31-1 to 33-1 are off), a voltage level (ΔVR) corresponding to a resistance ratio rises, and each voltage level has ΔV.
Voltage level with R added, VR0 + ΔVR, VR1
+ ΔVR, VR2 + ΔVR. It is also possible to easily change the voltage level depending on the resistance ratio.

Thus, in the drive circuit of the liquid crystal display device or the like of the present invention, the gradation voltage can be generated at the input section of the data driver section by changing the level of the reference voltage using a small number of reference power sources. , The number of analog switches for selecting the grayscale voltage required for each output of the data driver unit is greatly reduced to reduce the chip area, and the number of wires of the reference power source that runs inside the chip is made smaller than before. It becomes possible to reduce the area.

[0040]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The construction and operation of a preferred embodiment of the present invention will be described below with reference to FIGS. FIG. 8 is a circuit block diagram showing the configuration of the first embodiment of the present invention.
However, here, of the drive circuit of the liquid crystal display device, a schematic configuration of a data driver unit related to the present invention will be shown. Further, in FIG. 8, a data driver unit with 64 gradations is illustrated.

The operation of the data driver section shown in FIG. 8 is as follows: a shift clock CLKD which is a timing signal given in synchronization with image data, and a digital display data signal (also called a video signal) RDATA representing image data for color display. (Red), GDATA (green) and B
DATA (blue), a start pulse SPD that determines the start of fetching these display data signals, a latch pulse LP that determines the switching timing of the display data signal output,
It is controlled by an output enable control signal AP that controls the enable of the output of the staircase voltage, a staircase voltage switching signal BP that controls the timing of switching the staircase voltage, and the like. The various signals described above are generated by the control circuit unit 5 (FIG. 1). The control circuit unit 5 also generates a horizontal synchronizing signal HSYNC indicating a horizontal scanning period when the image data is scanned in the direction of the data bus line and displayed.

The shift register circuit section 60 in FIG.
The configurations of the first digital memory 61, the second digital memory 62, and the analog switch section 80 are respectively the shift register circuit section 600 and the first digital memory section shown in FIG.
Digital memory 610, second digital memory 6
20 and the configuration of the analog switch unit 800 are almost the same. More specifically, in the shift register circuit unit 60 of FIG. 8, the start pulse SPD indicating the start of fetching the display data signal for each line and the clock CLKD for register advancement are controlled for each line by a control circuit or the like. , The data fetch signals S1 to S64 for sequentially writing the display data signals in the first digital memory 61 are generated. That is, a start pulse SP consisting of one pulse in one horizontal scanning period
The operation of the shift register in the shift register circuit unit 60 is started by D. Data capture signals S1 to S6 generated inside the shift register of the data driver unit
4, the display data signals RDATA, GDATA and BDATA are sequentially fetched into the first digital memory 61.

When the shift register circuit section 60 completes the data fetch of the data driver section itself, the data fetch signal SOUT (S6 for the data driver of the next stage.
4) is output and the cascade operation is performed. Further, when the capture of the video data for one line is completed, the information in the first digital memory 61 is changed to the second information by the latch pulse LP.
Of the digital memory 62. The video data transferred to the second digital memory 62 is decoded pixel by pixel in the decoder and staircase voltage controller 63. The decoder and staircase voltage controller 63 also has a function of controlling the output of staircase voltage.

Further, the decoder and staircase voltage controller 6
In accordance with the result decoded by 3, the analog switch unit 80, which is a set of analog switches in the next stage, outputs one of a plurality of voltages V0 to V63 (for example, in the case of 64 gradations).
Choose one. These voltages V0 to V63 are obtained by converting four types of reference power sources Vr0 to Vr4 input from the outside into the time division resistance voltage dividing unit 2 having the function of the staircase voltage generating unit 2 (FIG. 1).
It is created by dividing by 3. in this case,
The number of analog switches required for the analog switch unit 80 is 32 × 192 = 6144, which is half the conventional one (see FIG. 23).

FIG. 9 is a circuit diagram showing an example of the configuration of the time division resistance voltage dividing section provided in the reference power source input section. Between each of the input terminals of the external reference power supplies Vr0 to Vr4, eight resistor arrays (resistors R1 to R8 and R9 to R32) are formed, and two (pair) switch elements ( Switch elements 2d-1 to 2d-32 and 2u
-1 to 2u-32) are provided. The pair of switch elements have approximately the same on-resistance, and one terminal of the pair of switch elements is short-circuited with each other. The output voltage extracted from these switch elements is supplied to the analog switch section 80 as a gradation voltage. The staircase voltage switching signal BP input from the outside is the switching elements 2u-1 to 2u-3 connected to the upper stage of each resistor.
2 is controlled. The switch elements 2d-1 to 2d-32 connected to the lower stage of each resistor are always on.

10 and 11 are timing charts (No. 1 and No. 2) for explaining the operation of FIG.
It is. The operation of the shift register in the data driver unit is started by SPD consisting of one pulse in one horizontal period.
Data capture signal S1 generated inside the shift register
Through S64, the display data signals RDATA, GDATA and BDATA including the video data for color display are loaded into the first digital memory 61. When the data acquisition of the data driver unit itself is completed, SOUT for the next-stage driver is output and the cascade operation is performed. 1
When the data acquisition for the line is completed, the information in the first digital memory 61 is transferred to the second digital memory 62 at once by the latch pulse LP.

One horizontal period is divided into two phases,
Switching between the first phase and the second phase is performed by the staircase voltage switching signal BP. In the second phase, both the upper switch element and the lower switch element of the reference voltage input section are turned on, and the voltage divided by the on resistance of the switch element is output from the data driver section. When the first phase is selected depending on the value of the lower 1 bit of the video data held in the second digital memory 62, and the first phase is selected (lower 1 When the bit value is "0" or "L"), the output of the staircase voltage is opened by the output enable control signal AP while the staircase voltage of the first stage is being output. When the second phase is selected (the value of the lower 1 bit is “1” or “H”), the output enable control signal AP becomes invalid, the staircase voltage of the first stage is output, and then the second stage The staircase voltage of is output. Since the method using the distributed capacitance of the data bus line described above can be used by the step voltage control procedure as described above, 6
It is possible to output four gradations.

FIG. 12 is a circuit block diagram showing the configuration of the second embodiment of the present invention. The configuration of the data driver unit of FIG. 12 is almost the same as the configuration of the first embodiment (FIG. 8), but differs from the first embodiment in that the staircase voltage switching signal BP is internally generated. In FIG. 12, by utilizing the fall of the output enable control signal AP,
It is shown that the timing for switching between the two phases can be set without the need for the staircase voltage switching signal BP supplied as an input signal from the outside. In the configuration of the second embodiment, in the first embodiment of FIG. 8, the internal timing control unit 64 outputs the staircase voltage switching signal from each signal of the latch pulse LP and the output enable control signal AP inside the data driver unit. I try to create a BP.

13 and 14 are timing charts (No. 1 and No. 2) for explaining the operation of FIG. The basic operation of the second embodiment shown in FIGS. 13 and 14 is almost the same as that of the first embodiment shown in FIG. 8, but the timing of switching between the two phases is controlled by the fall of the output enable control signal AP. The points are different.

FIG. 15 is a circuit diagram showing an example of the structure of the timing control section of FIG. 12, and FIG. 16 is a timing chart for explaining the operation of FIG. In FIG. 15, a specific circuit configuration example of the timing control unit 64 that generates the staircase voltage switching signal BP is illustrated. Here, the latch pulse LP and the output enable control signal AP
The output of the SR latch circuit section 65 which receives the input is used as the D input (D) of the D-flip-flop 67. Furthermore, N
An output obtained as a result of taking the negative logical sum (NOR) of the latch pulse LP and the output enable control signal AP by the OR circuit element 66 is used as the clock input (CK) of the D-flip-flop 67. Further, in the D-flip-flop 67, the output of the SR latch circuit section 65 is latched by the clock input, and the output is output as the staircase voltage switching signal B.
As P, it is supplied to the time division resistance voltage dividing unit 23.

As is clear from the configuration of the timing chart of FIG. 16, the timing control section 64 of FIG.
The staircase voltage switching signal BP that switches between the two phases is easily created. By generating the staircase voltage switching signal BP by the above method, the drive circuit of the present invention can be realized with the same number of signals as the conventional one. FIG.
FIG. 6 is a circuit block diagram showing a configuration of a third exemplary embodiment of the present invention. Here, in the above-described first embodiment of FIG. 8, the output buffer section 40 including a plurality of operational amplifiers is provided while the time division resistance voltage dividing section 23 provided in the reference power supply input section is connected to the analog switch section 80. Is provided. Since the output buffer section 40 is connected to each of the 32 output voltages, the output resistance at the time of voltage division due to the resistance and the switch element cannot be seen from the output side of the data driver section. The drive circuit of the embodiment is advantageous when driving a liquid crystal display panel having a relatively large capacity.

FIG. 18 is a circuit block diagram showing the structure of the fourth embodiment of the present invention. The fourth embodiment of FIG. 18 shows an example in which the configuration including the output buffer unit 40 of the third embodiment of FIG. 17 is applied to the second embodiment of FIG. FIG. 19 is a circuit block diagram showing the configuration of the fifth embodiment of the present invention. In the fifth embodiment of FIG. 19, the above-described FIG.
In the first embodiment, the final stage buffer unit 41 including a plurality of operational amplifiers is provided on the output side of the final stage of the data driver unit via the plurality of analog switches. Since the operational amplifier in the final stage buffer unit 41 is provided on each output side of the final stage of the data driver unit, the operational amplifier in the final stage buffer unit 41 is more than in the third embodiment of FIG. 17 and the fourth embodiment of FIG. It is possible to increase the driving capacity of the liquid crystal display device and to drive a liquid crystal display panel having a large capacity.

FIG. 20 is a circuit block diagram showing the structure of the sixth embodiment of the present invention. The sixth embodiment of FIG. 20 shows an example in which the configuration including the final stage buffer unit 41 of the fifth embodiment of FIG. 19 is applied to the second embodiment of FIG. FIG. 21 is a circuit block diagram showing the configuration of the seventh embodiment of the present invention. Here, an embodiment according to the second principle of the invention is illustrated. The drive circuit in FIG. 21 incorporates the constituent circuit according to the second principle of the present invention.
It is a configuration example of a 4-gradation data driver section, and is an embodiment in which a reference voltage generating section 3 based on the second principle of the present invention, an input buffer section 35, and a resistor array type D / A converter section 38 are combined. An example is shown.

In FIG. 21, the input reference power source Vr
The voltage levels of 0 to Vr4 are changed by the plurality of resistors R1-1 to R5-2 and the switch elements 31-1 to 35-2 of the reference voltage creating unit 2, respectively. In the seventh embodiment of FIG. 21, two reference voltages (2
One voltage level) is illustrated. Further, these reference voltages are applied to a plurality of resistors 38-0 to 38-.
Since the resistors are divided by the resistor array type D / A converter 38 composed of 31, the voltages V0 to V31 also have two voltage levels. That is, here, 32 × 2 = 6
4 voltage levels are created, and the gradation voltage is selected and output under the control of the decoder and the staircase voltage controller 63. In this case, the resistance value of the resistor used for the reference voltage generating unit 3 is a resistance value r that takes an intermediate value between the reference voltages V0, V1, ... V31, that is, the reference power sources Vr0 to Vr5.
It suffices to set the resistance value so as to divide the space into 16 equal parts.

So far, the specific construction of the present invention has been described with reference to the embodiments in which the drive circuit of the present invention is applied to a liquid crystal display device. However, the drive circuit of the present invention is not necessarily limited to a liquid crystal display device, and is also applied to any other display device that performs gradation display by a gradation voltage, for example, a plasma display device (PDP). It goes without saying that it can be done.

[0056]

As described above, according to the drive circuit of the liquid crystal display device of the present invention, firstly, the level of the reference voltage is turned on / off by the pair of switch elements provided at both ends of the dividing resistor. Can be changed, so that it becomes possible to create the gradation voltage using a small number of reference power sources. As a result, the number of analog switches and the like for selecting the gradation voltage required for each output of the data driver unit can be significantly reduced to reduce the chip area, which greatly contributes to the cost reduction of the liquid crystal display device.

Further, according to the drive circuit of the liquid crystal display device of the present invention, secondly, the on / off operation of the pair of switch elements can be easily controlled by the control signal from the existing control circuit section. Therefore, the drive circuit of the present invention can be realized without adding an extra circuit or complicating the circuit configuration of the data driver section. Further, according to the drive circuit of the liquid crystal display device of the present invention,
In addition, since the timing of switching the on / off operation of the pair of switch elements can be created from the internal control signal, it is possible to reduce the wiring of the control signal taken in from the outside. As a result, the chip area of the driver IC can be further reduced.

Further, according to the drive circuit of the liquid crystal display device of the present invention, fourthly, since the output buffer section including a plurality of operational amplifiers is connected to each of the reference voltage output sides,
The output resistance due to the division resistance and the switch element cannot be seen from the output side of the data driver section, which is advantageous when driving a liquid crystal display panel having a relatively large capacity. Further, according to the driving circuit of the liquid crystal display device of the present invention,
In addition, since the final stage buffer section composed of a plurality of operational amplifiers is provided on each output side of the final stage of the data driver section,
The drive capability of the data driver section can be remarkably increased, and a liquid crystal display panel having a relatively large capacity can be driven.

Further, according to the drive circuit of the liquid crystal display device of the present invention, sixthly, the level of the reference voltage is changed by combining a plurality of different resistors and switches in the input part of the reference power source. Therefore, it is possible to generate the gradation voltage using a small number of reference power sources.
As a result, the number of analog switches and the like for selecting the gradation voltage required for each output of the data driver unit can be significantly reduced to reduce the chip area, which greatly contributes to the cost reduction of the liquid crystal display device.

Further, according to the drive circuit of the liquid crystal display device of the present invention, seventhly, a reference voltage generated based on a combination of a plurality of different resistors and switches and a distributed capacitance of the data bus line is used as a resistor. By combining with an array type D / A converter, multi-gradation display can be realized without complicating the circuit configuration. further,
Eighthly, according to the drive circuit of the liquid crystal display device of the present invention, since the reference voltage generating section including the plurality of different resistors and the switch elements is formed inside the driver IC, it is possible to reduce Possible signal propagation delays and the like are avoided.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first principle configuration of the present invention.

FIG. 2 is a block diagram showing a second principle configuration of the present invention.

FIG. 3 is a circuit diagram (No. 1) showing a simplified step voltage generation unit for explaining the first principle of the present invention.

FIG. 4 is a circuit diagram (No. 2) showing a simplified staircase voltage generator for explaining the first principle of the present invention.

FIG. 5 is a circuit diagram showing an embodiment of the invention according to the second principle of the present invention.

FIG. 6 is a circuit diagram showing another embodiment of the invention according to the second principle of the present invention.

FIG. 7 is a timing chart for explaining the operation of FIG.

FIG. 8 is a circuit block diagram showing a configuration of a first exemplary embodiment of the present invention.

9 is a circuit diagram showing a configuration example of a time division resistance voltage dividing unit in FIG.

FIG. 10 is a timing chart (No. 1) for explaining the operation of FIG.

FIG. 11 is a timing chart (No. 2) for explaining the operation of FIG.

FIG. 12 is a circuit block diagram showing a configuration of a second exemplary embodiment of the present invention.

FIG. 13 is a timing chart (No. 1) for explaining the operation of FIG.

FIG. 14 is a timing chart (No. 2) for explaining the operation of FIG.

15 is a circuit diagram showing a configuration example of the timing control section in FIG.

16 is a timing chart for explaining the operation of FIG.

FIG. 17 is a circuit block diagram showing a configuration of a third exemplary embodiment of the present invention.

FIG. 18 is a circuit block diagram showing a configuration of a fourth exemplary embodiment of the present invention.

FIG. 19 is a circuit block diagram showing a configuration of a fifth exemplary embodiment of the present invention.

FIG. 20 is a circuit block diagram showing a configuration of a sixth exemplary embodiment of the present invention.

FIG. 21 is a circuit block diagram showing a configuration of a seventh exemplary embodiment of the present invention.

FIG. 22 is a plan view showing a simplified panel configuration of a general liquid crystal display device.

FIG. 23 is a circuit block diagram showing a configuration of a drive circuit of a conventional liquid crystal display device.

FIG. 24 is a timing chart for explaining the operation of FIG. 23.

FIG. 25 is a circuit diagram showing a configuration example of a conventional gradation voltage generating section.

FIG. 26 is a circuit diagram showing a relationship between a conventional grayscale voltage generation section and an analog switch section.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Liquid crystal display device 2 ... Staircase voltage generation unit 3 ... Reference voltage generation unit 5 ... Control circuit unit 6 ... Display data signal timing setting unit 7 ... Reference power supply unit 8 ... Gradation voltage selection unit 9 ... Liquid crystal display panel 10 ... Scan Driver unit 20 ... Resistance voltage dividing unit 22 ... Staircase voltage level switching unit 23 ... Time division resistance voltage dividing unit 30 ... Division resistance unit 33 ... Reference voltage level switching unit 35 ... Input buffer unit 38 ... D / A converter unit 40 ... Output Buffer unit 41 ... Final stage buffer unit 60 ... Shift register circuit unit 61 ... First digital memory 62 ... Second digital memory 63 ... Decoder and step voltage control unit 64 ... Timing control unit 80 ... Analog switch unit T11 to Tnm ... Switching elements X1 to Xm ... Data bus lines Y1 to Yn ... Scan bus lines

Claims (8)

[Claims] 1. A plurality of first bus lines for scanning the pixels for a plurality of pixels constituting a liquid crystal display panel (9) of a liquid crystal display device, and selection on the first bus lines. A drive circuit of a liquid crystal display device, in which a plurality of second bus lines for supplying a gradation voltage in which a staircase voltage is superimposed for displaying predetermined image data on the selected pixel are arranged. The step voltage generator (2) generates the step voltage based on a plurality of reference power supplies (Vr0 to Vrk) output from the section (7), and the step voltage generator (2) includes the step voltage generator (2). A resistance voltage dividing means (20) for dividing the reference power sources (Vr0 to Vrk) between the reference power sources by a plurality of divided resistors.
And a staircase voltage level switching means (22) which is provided at both ends of each of the plurality of division resistors and which is composed of a pair of switch elements for switching the level of the staircase voltage. By the control signal for controlling, one of the pair of switch elements provided at both ends of each of the plurality of divided resistors is made conductive in the first period, and both of the pair of switch elements are brought into the conductive state in the second period. A driving circuit for a liquid crystal display device, wherein the step voltage is generated by bringing the device into a conductive state. 2. The drive circuit further includes a control circuit unit (5) for controlling the timing of scanning the pixel and the timing of displaying image data on the selected pixel, and the staircase voltage generating unit. And a gradation voltage selecting unit (8) for selecting the gradation voltage corresponding to the image data and supplying the selected gradation voltage to the second bus line by superimposing the staircase voltage generated in (2). , The control signal generated by the control circuit unit (5)
The timing of switching the staircase voltage by setting the switch element in the staircase voltage level switching means (22) to the conducting state or the non-conducting state, and whether to enable the output of the staircase voltage are determined. The drive circuit according to claim 1. 3. The control circuit unit (5), wherein the drive circuit further controls the timing of scanning the pixel and the timing of displaying image data on the selected pixel.
And a gradation voltage selecting unit (which selects the gradation voltage corresponding to the image data and supplies the gradation voltage corresponding to the image data to the second bus line by superimposing the step voltage generated by the step voltage generating unit (2) ( 8) and a timing control unit (6) for controlling the timing of switching the staircase voltage by setting the switch element in the staircase voltage level switching means (1) to a conducting state or a non-conducting state.
4), the timing control unit (64) is configured to output the staircase voltage based on a control signal from the control circuit unit (5) for determining whether to enable the output of the staircase voltage. The signal for controlling the timing of switching the voltage is generated.
The driving circuit as described. 4. The output buffer section (40) comprising a plurality of buffer amplifiers is provided between the staircase voltage generating section (2) and the gradation voltage selecting section (8). Drive circuit. 5. The drive circuit according to claim 2, wherein a final stage buffer section (41) including a plurality of buffer amplifiers is provided at the final stage on the output side of the gradation voltage selection section (8). 6. A plurality of pixels constituting a liquid crystal display panel (9) of a liquid crystal display device, a plurality of first bus lines for scanning the pixels, and selection on the first bus lines. A drive circuit of a liquid crystal display device, in which a plurality of second bus lines for supplying a gradation voltage in which a staircase voltage is superimposed for displaying predetermined image data on the selected pixel are arranged. The reference voltage generator (3) is provided for generating a plurality of reference voltages according to the type of the gradation voltage based on a plurality of reference power supplies (Vr0 to Vrk) output from the unit (7). The voltage generator (3) divides each of the plurality of reference power supplies (Vr0 to Vrk) to obtain a plurality of reference voltages, and a dividing resistor means (30) including a plurality of dividing resistors, It is connected to each of a plurality of dividing resistors, A reference voltage level changing means (33) including a plurality of switch elements for changing the levels of reference voltages respectively taken out from the plurality of division resistors, and the plurality of the plurality of switch elements are controlled by a control signal for controlling the operation of the plurality of switch elements. A drive circuit for a liquid crystal display device, wherein the step voltage is generated by combining the division resistance of 1. and the plurality of switch elements. 7. The digital / analog converter, wherein the drive circuit further includes a resistor array for dividing the plurality of digital output voltages from the reference voltage level changing means (33) to generate the grayscale voltage. A drive circuit according to claim 6, comprising a section (38). 8. The drive circuit according to claim 6, wherein the reference voltage generator (3) is formed inside an integrated circuit.