IT1392913B1 - Metodo per implementare variazioni di funzionalita' di un layout di progetto di un dispositivo integrato, in particolare un sistema su singolo chip o system-on-chip mediante celle di riempimento programmabili tramite maschera - Google Patents

Metodo per implementare variazioni di funzionalita' di un layout di progetto di un dispositivo integrato, in particolare un sistema su singolo chip o system-on-chip mediante celle di riempimento programmabili tramite maschera

Info

Publication number
IT1392913B1
IT1392913B1 ITMI2008A002358A ITMI20082358A IT1392913B1 IT 1392913 B1 IT1392913 B1 IT 1392913B1 IT MI2008A002358 A ITMI2008A002358 A IT MI2008A002358A IT MI20082358 A ITMI20082358 A IT MI20082358A IT 1392913 B1 IT1392913 B1 IT 1392913B1
Authority
IT
Italy
Prior art keywords
chip
mask
functionality
integrated device
single chip
Prior art date
Application number
ITMI2008A002358A
Other languages
English (en)
Inventor
Valentina Nardone
Luca Ciccarelli
Lorenzo Cali
Stefania Stucchi
Original Assignee
St Microelectronics Srl
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by St Microelectronics Srl filed Critical St Microelectronics Srl
Priority to ITMI2008A002358A priority Critical patent/IT1392913B1/it
Priority to US12/648,953 priority patent/US8214774B2/en
Publication of ITMI20082358A1 publication Critical patent/ITMI20082358A1/it
Application granted granted Critical
Publication of IT1392913B1 publication Critical patent/IT1392913B1/it

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
ITMI2008A002358A 2008-12-30 2008-12-30 Metodo per implementare variazioni di funzionalita' di un layout di progetto di un dispositivo integrato, in particolare un sistema su singolo chip o system-on-chip mediante celle di riempimento programmabili tramite maschera IT1392913B1 (it)

Priority Applications (2)

Application Number Priority Date Filing Date Title
ITMI2008A002358A IT1392913B1 (it) 2008-12-30 2008-12-30 Metodo per implementare variazioni di funzionalita' di un layout di progetto di un dispositivo integrato, in particolare un sistema su singolo chip o system-on-chip mediante celle di riempimento programmabili tramite maschera
US12/648,953 US8214774B2 (en) 2008-12-30 2009-12-29 Method for implementing functional changes into a design layout of an integrated device, in particular a system-on-chip, by means of mask programmable filling cells

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
ITMI2008A002358A IT1392913B1 (it) 2008-12-30 2008-12-30 Metodo per implementare variazioni di funzionalita' di un layout di progetto di un dispositivo integrato, in particolare un sistema su singolo chip o system-on-chip mediante celle di riempimento programmabili tramite maschera

Publications (2)

Publication Number Publication Date
ITMI20082358A1 ITMI20082358A1 (it) 2010-06-30
IT1392913B1 true IT1392913B1 (it) 2012-04-02

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
ITMI2008A002358A IT1392913B1 (it) 2008-12-30 2008-12-30 Metodo per implementare variazioni di funzionalita' di un layout di progetto di un dispositivo integrato, in particolare un sistema su singolo chip o system-on-chip mediante celle di riempimento programmabili tramite maschera

Country Status (2)

Country Link
US (1) US8214774B2 (it)
IT (1) IT1392913B1 (it)

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US8826195B2 (en) 2012-06-05 2014-09-02 Taiwan Semiconductor Manufacturing Co., Ltd. Layout modification method and system
US9232176B2 (en) 2013-03-04 2016-01-05 Janus Technologies, Inc. Method and apparatus for securing computer video and audio subsystems
US9424443B2 (en) 2013-08-20 2016-08-23 Janus Technologies, Inc. Method and apparatus for securing computer mass storage data
US9231921B2 (en) 2013-08-20 2016-01-05 Janus Technologies, Inc. System and architecture for secure computer devices
US9384150B2 (en) 2013-08-20 2016-07-05 Janus Technologies, Inc. Method and apparatus for performing transparent mass storage backups and snapshots
US11210432B2 (en) 2013-08-20 2021-12-28 Janus Technologies, Inc. Method and apparatus for selectively snooping and capturing data for secure computer interfaces
US9215250B2 (en) 2013-08-20 2015-12-15 Janus Technologies, Inc. System and method for remotely managing security and configuration of compute devices
US9076003B2 (en) 2013-08-20 2015-07-07 Janus Technologies, Inc. Method and apparatus for transparently encrypting and decrypting computer interface data
US9684805B2 (en) 2013-08-20 2017-06-20 Janus Technologies, Inc. Method and apparatus for securing computer interfaces
US9563736B2 (en) 2014-02-21 2017-02-07 International Business Machines Corporation Placement aware functional engineering change order extraction
US10162925B2 (en) * 2015-09-18 2018-12-25 Taiwan Semiconductor Manufacturing Co., Ltd. Cell layout of semiconductor device
CN105550445B (zh) * 2015-12-12 2018-08-21 中国航空工业集团公司西安航空计算技术研究所 一种基于编解码芯片的虚拟验证方法
US9953121B2 (en) * 2016-05-03 2018-04-24 International Business Machines Corporation Accommodating engineering change orders in integrated circuit design
US10127340B2 (en) * 2016-09-30 2018-11-13 Taiwan Semiconductor Manufacturing Company, Ltd. Standard cell layout, semiconductor device having engineering change order (ECO) cells and method
US9892966B1 (en) 2016-12-14 2018-02-13 Nxp B.V. Metal only post-mask ECO for integrated circuit
US10830818B2 (en) 2017-09-25 2020-11-10 International Business Machines Corporation Ensuring completeness of interface signal checking in functional verification
US11301614B1 (en) * 2019-12-31 2022-04-12 Synopsys, Inc. Feasibility analysis of engineering change orders
KR20220134325A (ko) 2021-03-26 2022-10-05 삼성전자주식회사 표준 셀 및 필러 셀을 포함하는 집적 회로
US11775730B2 (en) 2021-08-16 2023-10-03 International Business Machines Corporation Hierarchical large block synthesis (HLBS) filling

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Also Published As

Publication number Publication date
US20100201400A1 (en) 2010-08-12
ITMI20082358A1 (it) 2010-06-30
US8214774B2 (en) 2012-07-03

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