IT1258856B - APPARATUS AND METHOD FOR THE PROTECTION OF MEMORIES FROM SPURY WRITINGS. - Google Patents

APPARATUS AND METHOD FOR THE PROTECTION OF MEMORIES FROM SPURY WRITINGS.

Info

Publication number
IT1258856B
IT1258856B ITRM920707A ITRM920707A IT1258856B IT 1258856 B IT1258856 B IT 1258856B IT RM920707 A ITRM920707 A IT RM920707A IT RM920707 A ITRM920707 A IT RM920707A IT 1258856 B IT1258856 B IT 1258856B
Authority
IT
Italy
Prior art keywords
signal
protection
generation
memory device
spury
Prior art date
Application number
ITRM920707A
Other languages
Italian (it)
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Publication of ITRM920707A0 publication Critical patent/ITRM920707A0/en
Publication of ITRM920707A1 publication Critical patent/ITRM920707A1/en
Application granted granted Critical
Publication of IT1258856B publication Critical patent/IT1258856B/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/88—Masking faults in memories by using spares or by reconfiguring with partially good memories
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/004—Error avoidance
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/24—Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0796—Safety measures, i.e. ensuring safe condition in the event of error, e.g. for controlling element

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Mobile Radio Communication Systems (AREA)

Abstract

Oggetto dell'invenzione è un apparecchio di protezione dalla scrittura. L'apparecchio di protezione dalla scrittura collega un dispositivo (121) di alimentazione di dati ad un ingresso di dati di un dispositivo di memoria (127). Il dispositivo di protezione della memoria genera un primo segnale (211) che provoca lo scatto della generazione di un secondo segnale (215). Il secondo segnale (215) è attivo per un primo tempo predeterminato e viene applicato all'ingresso del dispositivo di memoria (127). In qualsiasi momento nel corso di questo primo predeterminato intervallo di tempo, può essere generato un terzo segnale (209). Il terzo segnale (209) disattiva il secondo segnale. Questo terzo segnale (209) può essere fatto scattare da numerosi eventi che comprendono la generazione di un segnale di lettura, la generazione di un segnale di selezione di chip oppure la indicazione del fatto che si è verificato il termine dei dati che debbono essere scritti nel dispositivo di me-moria (127).The object of the invention is a write protection device. The write-protection apparatus connects a data supply device (121) to a data input of a memory device (127). The memory protection device generates a first signal (211) which triggers the tripping of the generation of a second signal (215). The second signal (215) is active for a predetermined first time and is applied to the input of the memory device (127). At any time during this first predetermined time interval, a third signal (209) can be generated. The third signal (209) deactivates the second signal. This third signal (209) can be triggered by numerous events which include the generation of a read signal, the generation of a chip selection signal or the indication that the end of the data that must be written in the memory device (127).

ITRM920707A 1991-10-01 1992-09-28 APPARATUS AND METHOD FOR THE PROTECTION OF MEMORIES FROM SPURY WRITINGS. IT1258856B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US76989691A 1991-10-01 1991-10-01

Publications (3)

Publication Number Publication Date
ITRM920707A0 ITRM920707A0 (en) 1992-09-28
ITRM920707A1 ITRM920707A1 (en) 1994-03-28
IT1258856B true IT1258856B (en) 1996-03-01

Family

ID=25086828

Family Applications (1)

Application Number Title Priority Date Filing Date
ITRM920707A IT1258856B (en) 1991-10-01 1992-09-28 APPARATUS AND METHOD FOR THE PROTECTION OF MEMORIES FROM SPURY WRITINGS.

Country Status (5)

Country Link
CA (1) CA2097308A1 (en)
FR (1) FR2681965A1 (en)
IT (1) IT1258856B (en)
MX (1) MX9205634A (en)
WO (1) WO1993007565A1 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6026293A (en) * 1996-09-05 2000-02-15 Ericsson Inc. System for preventing electronic memory tampering
JP4154006B2 (en) * 1996-12-25 2008-09-24 富士通株式会社 Semiconductor memory device
GB2356952B (en) * 1996-12-25 2001-07-25 Fujitsu Ltd Semiconductor memory device

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4245344A (en) * 1979-04-02 1981-01-13 Rockwell International Corporation Processing system with dual buses
US4493031A (en) * 1982-08-25 1985-01-08 At&T Bell Laboratories Memory write protection using timers
JPS6124091A (en) * 1984-07-12 1986-02-01 Nec Corp Memory circuit
US4742469A (en) * 1985-10-31 1988-05-03 F.M.E. Corporation Electronic meter circuitry
US4816654A (en) * 1986-05-16 1989-03-28 American Telephone And Telegraph Company Improved security system for a portable data carrier
US4843385A (en) * 1986-07-02 1989-06-27 Motorola, Inc. Electronic lock system for a two-way radio
FR2608803B1 (en) * 1986-12-19 1991-10-25 Eurotechnique Sa DEVICE FOR PROTECTING AN ERASABLE AND REPROGRAMMABLE DEAD MEMORY
US5001670A (en) * 1987-02-06 1991-03-19 Tektronix, Inc. Nonvolatile memory protection
JPS63271679A (en) * 1987-04-30 1988-11-09 Toshiba Corp Data writing system
US4860341A (en) * 1987-06-02 1989-08-22 Motorola, Inc. Radiotelephone credit card call approval synchronization
US4970692A (en) * 1987-09-01 1990-11-13 Waferscale Integration, Inc. Circuit for controlling a flash EEPROM having three distinct modes of operation by allowing multiple functionality of a single pin
JPH0648838B2 (en) * 1988-07-18 1994-06-22 株式会社田村電機製作所 Public telephone
FI86922C (en) * 1990-01-05 1992-10-26 Raha Automaattiyhdistys FOERFARANDE OCH ANORDNING FOER KONTROLLERING AV INSKRIVNING I ETT MINNE

Also Published As

Publication number Publication date
ITRM920707A1 (en) 1994-03-28
WO1993007565A1 (en) 1993-04-15
CA2097308A1 (en) 1993-04-02
ITRM920707A0 (en) 1992-09-28
FR2681965A1 (en) 1993-04-02
MX9205634A (en) 1993-04-01

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Legal Events

Date Code Title Description
0001 Granted