FR2681965A1 - MEMORY WRITE PROTECTION METHOD AND APPARATUS. - Google Patents

Abstract

A write protection apparatus is disclosed. The write protection apparatus couples a data supplying device (121) to the data input of a memory device (127). The memory protection device generates a first signal (211) which triggers generation of a second signal (215). The second signal (215) is active for a first predetermined time and is coupled to the input of the memory device (127). At any time during this first predetermined time, a third signal (209) may be generated. The third signal (209) inactivates the second signal. This third signal (209) may be triggered by numerous events including: generation of a read signal, generation of a chip select signal, or indication that the end of the data to be written to the memory device (127) has occurred.

Description

 The present invention relates generally to the infrastructure of microcomputer systems and, more specifically, access to the memory device contained within a microcomputer system. More particularly, it relates to a method and an apparatus for writing to memory protection.

 Typically, a microcomputer system contains a memory, a data bus, a microprocessor and peripheral devices. The memory contains a data bus input, an address bus input, a chip or box selection input, and a write validation input. From a general point of view, in microcomputing, there are three systems for writing data to an external memory.

 According to a first system, a control device is used to create the address on the address bus. The chip selection and write validation lines are directly connected between the control device and the memory device. During power-up or during data transfer, it may happen that the write enable signal is activated for too long or is triggered incorrectly. This can lead to the writing of spurious data in the memory device and alter the data contained in the memory, which can seriously affect the functioning of the microcomputer system. In addition, the controller can execute the error code during a write cycle, which produces unpredictable results inside the memory device.

 According to the second system, an attempt is made to protect the memory from corrupted data. The controller triggers a logic device, which creates the write enable signal for the memory device for a predetermined period of time. This predetermined duration is typically fixed at the time necessary to write the largest possible block of data to the memory device, so that it does not limit the amount of data which is written to the storage location of the memory device. This system leaves the possibility of corrupted data being written to the memory device in the event that data blocks, smaller than the largest possible data block, are written to the memory device or an enable signal write is triggered incorrectly. Again, the controller can execute the error code during a write cycle and cause unpredictable results inside the memory device.

 The third system has a protection device built into the memory. The memory requests the controller to write a byte of data to three specific addresses before writing the desired data to the memory device. This form of implementation is discussed in the technical data sheets X28C64, of XICOR Data Book, 2nd edition, 1990. Once the sequence of three bytes has been written to the appropriate addresses, the page writing window opens, which authorizes the control device to write between 1 and 64 bytes of data in the memory device. This protection device protects the memory against an erroneous triggering, but allows a possible alteration of the memory device during this invariable page writing window. Again, the controller can execute the error code during a write cycle and produce unpredictable results inside the memory device.

 There is therefore a need for a data protection device capable of adaptation, which varies the duration of the write validation signal as a function of the size of the data block to be written in the memory device or of the activity monitored. inside the control device, and which eliminates the erroneous triggering of the write validation signal.

 The invention provides a write protection device intended to protect a memory device from receiving corrupted data during the writing of a data block to the memory device from a supply device. of data. The memory device has a write validation input and a data input. The write protection device couples the data supply device to the data input of the memory device. The memory protection device produces a first signal which triggers the production of a second signal. The second signal is active for a first predetermined duration and is applied to the input of the memory device, which allows the data supply device to write data to the memory device during this first predetermined duration. A third signal can be produced to invalidate said second signal.

 The invention also relates to a memory write protection method.

The following description, intended to illustrate the invention, aims to give a better understanding of its characteristics and advantages; it is based on the appended drawings, among which:
Figure 1 is a block diagram of a radiotelephone telecommunications system which can employ the invention;
Figure 2 is a circuit diagram of the invention;
Figure 3 is a timing diagram of the invention; and
Figure 4 is a flowchart showing the method according to the invention.

 The invention provides a microcomputer system incorporated in a digital radiotelephone, for example the "Japan Digital Cellular Telephone" digital cellular radiotelephone. In the preferred embodiment, a programmable read-only memory, or PROM, electronically erasable, that is to say an EEPROM, is used as a memory device in the radiotelephone to store the permanent information necessary for the operation of the radiotelephone, even if the The invention can be used to protect any type of non-volatile or non-volatile memory device. Data blocks of various sizes are written to the EEPROM from different devices. In the past, it has been observed, when returning radiotelephones to the maintenance service, that the EEPROM contained altered data which invalidated or affected the operation of the radiotelephone. Thanks to the implementation of the invention, the writing of corrupted data in the EEPROM is minimized. In essence, the invention provides a method and apparatus for writing data blocks to the EEPROM without altering the data stored inside the memory device.

 Figure 1 is a block diagram of a radiotelephone telecommunication system. Within this system, there is a fixed site transceiver 103 which sends radio frequency (RF) signals to mobile or portable telephones located in the geographic area served by the fixed site transceiver 103 and which receives some. The radiotelephone 101 is one of the radiotelephones served by the fixed site transceiver 103.

 On reception of radio frequency signals, the antennas 105 and 107 of the radiotelephone convert the radio frequency signals into electric radio frequency signals, which are respectively transmitted to receivers 111 and 113. Receivers 111 and 113 convert the electric frequency signals radio in usable data, intended for use by other parts of the radiotelephone 101. When transmitting radio frequency signals, the microprocessor 121 applies data to the input of the transmitter 109. The transmitter accepts the data and converts them into electric radio frequency signals and transmits them via antenna 105, which converts its radio frequency signals and transmits them to the fixed site transceiver 103. For the radiotelephone 101 to function properly , many parameters must be stored in a permanent memory 127. This permanent memory is EEPRO M 127. Access to the EEPROM 127 is made via the microprocessor 121.

 During initial factory programming of the radiotelephone, the EEPROM 127 is programmed using essential functional parameters, which include: received signal strength information (RSSI), identification information and power level information.

RSSI information is required to calibrate the strengths of the signals being received. The calibrated intensities of the received signals are used to select the appropriate fixed site transceiver 103. The intensity of the current received signal which is reconstructed from receivers 111 and 113 is used in reference to the RSSI value stored in the EEPROM 127. If the values
RSSIs are altered, an incorrect fixed site transceiver can then be selected, which results in a reduction in the performance of the radiotelephone 101.

 The identification information contains a unique serial number and telephone number. This information is stored in EEPROM 127 during the initial programming procedure. This information must be protected to ensure the integrity of the telecommunications system. If the serial number changes or changes, the phone can then be identified as someone else's, or phone calls can be made and assigned to someone else's phone bill.

The power level table is loaded at the factory in EEPROM 127. The output power levels are measured for a given input, because the output power fluctuates from one radiotelephone to another according to the variations of the components and hybrid elements. Transmit power is tuned to meet FCC (Federal
Communications Commission), or equivalent Japanese specifications, on five predetermined levels. The information necessary to drive the power amplifier to the desired output level is stored in the EEPROM 127 and is extracted each time the power amplifier is to be tuned to a predetermined output power level. If this information is altered, the power amplifier contained in the transmitter 109 will not function within the specifications and this may cause serious performance problems for the radiotelephone 101. Once this information has been loaded into the EEPROM 127, the radiotelephone 101 is ready to operate.

 When the radiotelephone 101 is in service, provision is made to store in the EEPROM 127 certain specific user data and various parameters in order to facilitate repairs when the telephone is returned to the supplier. First of all, a clock is used to memorize the elapsed time of use of the radiotelephone from the start. So that the radiotelephone 101 maintains the operation of the counter, it stores the counter in the EEPROM 127. In the event of powering off or power failure, the clock is not repositioned. Second, the radiotelephone 101 contains an error control device that uses a group of error codes to describe the problems that arose in the radiotelephone 101 during operation. If an error occurs during the operation of the radiotelephone 101, the error code and its instant of occurrence are memorized in the EEPROM 127 to assist in the subsequent repair of the radiotelephone 101.

In addition, EEPROM 127 is used to store phone numbers and user choices, such as ring volume. The preceding operations are controlled by the microprocessor 121 during the operation of the radiotelephone 101.

 Figure 2 is a block diagram showing the use of the invention.

The data writing cycle from the microprocessor 121 begins with the sending of a known binary configuration to a predetermined address.

The predetermined address corresponds to the data verifier 207. The data verifier 207 receives the known byte of data from the microprocessor 121 and checks it against its known byte of data. During the verification, the microprocessor 121 then changes the address to that of the EEPROM 127 and begins to load the desired data on the data bus 217. Simultaneously, the data verifier 207 produces a signal 211 for triggering validation of d writing which is applied to the input of the monostable circuit 203. The monostable circuit 203 produces a write authorization signal 213 for a predetermined period. This predetermined duration is equal to the time necessary to write the largest data block in the EEPROM 127 coming from the microprocessor 121. In the preferred embodiment, the time of the monostable circuit is fixed at 50, us. The write authorization signal 213 and the read / write signal 219 are applied to the input of an AND gate 205. This guarantees that, in the event of an incorrect triggering by the monostable circuit, the signal 215 of validation of writing in the EEPROM will not be erroneously validated, which protects the EEPROM 127 against corrupted data. The AND gate 205 and the data verifier 207 are, in the preferred embodiment, implemented in the form of a programmable logic circuit (PLA) designated by the reference number 129 in FIG. 1 and which can be a model PAL16V8, which can be obtained from the company Advanced Micro
Devices. When the logical product (AND function) of the three signals 211, 213 and 219 can be formed, the AND gate 205 delivers a write validation signal (WE) 215 to the write validation input of the EEPROM 127 This authorizes the writing of the data present on the data bus 217 in the EEPROM 127 at the addresses determined by the microprocessor 121.

 The repositioning signal 209 of the monostable circuit can be used to shorten the duration of the write validation signal of the monostable circuit, so that a write validation signal of variable duration is created. There are several reasons why a variable duration is desirable for the write enable signal. First of all, if the data block which is to be written in the EEPROM 127 has a shorter duration than the largest data block, the signal 209 for repositioning the monostable circuit can then be triggered by the microprocessor 121, as a result of which there is invalidation of the write authorization signal 213 sent to the EEPROM 127 at the time when the shorter data block has been written. The duration of the write enable signal is equal to the length of the data block to be written to the EEPROM 127, which appreciably eliminates the possibility of writing corrupted data in the EEPROM 127. According to another case, the repositioning signal 209 can be used to interrupt a write cycle in EEPROM 127 when it is determined that a problem exists inside the radiotelephone. In the preferred embodiment, the repositioning signal 209 is used to interrupt a write cycle when the radiotelephone detects a read request signal or a chip selection signal sent to a device other than the EEPROM 127. These Problems are particular to the system within which the invention is used and those skilled in the art will be able to use equivalent criteria for invalidating the writing cycle.

 Note that the monostable circuit 203 is particular to this embodiment. Other embodiments may employ equivalent timing devices, including digital clocks, shift registers, and resistance / capacitor (RC) circuits, in place of the monostable circuit. Likewise, a person skilled in the art can replace the EEPROM 127 with any memory device.

 FIG. 3 shows the positions over time of all the main signals appearing in the functional diagram of FIG. 2. The microprocessor 121 positions the data bus 305 on a known binary configuration, and the address bus 307 to the data verifier 207. After the data verifier 207 has received the known binary configuration, the microprocessor 121 positions the address bus 307 on a memory location located inside the EEPROM 127 and begins to transfer the desired data to the data bus 307. When verifying the known binary configuration, the data verifier 207 creates the write validation trigger signal 313 (211). The signal is applied to the input of the monostable circuit 203. The monostable circuit 203 then creates a write authorization signal 311 (213), which lasts for 50, us and is applied to the input of the logical AND device 205 The logical AND device 205 uses the signals applied to the input of the microprocessor, namely the read / write signal 309 (219), the write validation trigger signal 313 (211) and the authorization signal d 'write 311, to create the write validation signal 315 in the EEPROM. The duration of the write validation signal 315 can be shortened by the microprocessor 121, which validates the repositioning signal 317 (209). The repositioning signal 317 (209) reposition the monostable circuit 203, which deactivates the write validation signal 315 (215).

 FIG. 4 is a flow diagram of the method used by this embodiment to reduce the risk of writing corrupted data in the EEPROM 127.

The flowchart begins at 401. At 403, the microprocessor 121 produces a known binary configuration on the data bus 217 and it positions the address on the bus 217 intended for the data verifier 207. At 405, the microprocessor 121 positions the address bus 217 on an address placed inside the EEPROM 127 and begins to transfer the desired data to the data bus 217. At 407, the verifier 207, after checking the known received bit pattern, produces a write validation trigger signal 313, which is applied to the input of the monostable circuit 203 and to that of the circuit
AND 205. At 409, the monostable circuit 203 produces, in response to the write validation trigger signal 313, the write authorization signal 311 for the time necessary for the transfer of the largest possible block of desired data to EEPROM 127. In the preferred embodiment, this duration is 50, us.

 In 411, if the data block sent by the microprocessor 121 is shorter than the largest possible data block, the repositioning signal 317 (209) is then produced by the microprocessor 121 and is applied to the repositioning input of the monostable circuit, which invalidates the application of the write enable signal 315 to the EEPROM 127. The repositioning signal 317 (209) acts as a variable window for the write enable signal 315, which window is set to fit the length of the data block written to the EEPROM. Alternatively, the repositioning signal 317 (209) can be produced in response to the existence of a problem in the radiotelephone 101, which has the effect of canceling the rest of the write cycle by avoiding any further damage to the EEPROM 127. In the preferred embodiment, the repositioning signal 317 (209) is triggered in response to an attempt to read or a signal to select another chip, executed by the microprocessor 121. These signals indicate that microprocessor 121 can execute the error code.

 Of course, those skilled in the art will be able to imagine, from the apparatus and the method, the description of which has just been given by way of illustration only and in no way limitative, various variants and modifications not departing from the part of the invention.

Claims (10)

 1. Write protection apparatus for protecting a memory device (127) to prevent it from receiving corrupted data during the writing of a data block to the memory device (127) from a device (121) for supplying data, the memory device (127) having a write validation input and a data input, the write protection apparatus being characterized by:  means for coupling the data supply device (121) to the data input of the memory device (127);  means for producing a first signal (211);  means which responds to said first signal producing means (211) by producing a second signal (215) for a first predetermined duration, said second signal (215) being applied to the write enable input of the memory device (127) so as to allow the data supply device (121) to write the data to the data input of the memory device (127) for the first predetermined time only; and  means for producing a repositioning signal (209) after a second predetermined time has elapsed since the production of said first signal (211) by said first signal producing means, which has the effect of deactivating said second signal (215), said second predetermined duration being less than or equal to said first predetermined duration.  2. write protection apparatus according to claim 1, characterized in that said first predetermined duration is equal to the time necessary to write in the memory device (127), from the data supply device (121), the block of data as large as possible.  3. Radiotelephone (101) comprising at least one user interface (125), a central processing unit (121), a data bus, an address bus and a memory (127), the data bus carrying data between the user interface (125) and the memory (127), the memory (127) having a write validation input and a data input, the radiotelephone being characterized by:  a memory protection means (127) making it possible to prevent it from accepting incorrect data from the user interface (125), said protection means being such that:  the central processing unit (121) produces a first signal for a first predetermined duration,  a time measuring device (203) produces, in response to the production of said first signal by the central processing unit (121), a second signal (215) for a second predetermined duration, said second predetermined duration being less than or equal at said first predetermined duration, said second signal being applied to the write validation input for the memory (127), so that writing to the memory (127) can only occur during said second predetermined duration, and  the central processing unit (121) produces, in response to a first condition, a third signal (209) appearing a third predetermined duration after the production of said second signal (215), said third signal (209) being applied to an input repositioning said time measuring device (203), which has the effect of rendering said second signal (215) inactive, said second predetermined duration being less than or equal to said first predetermined duration.  4. Radiotelephone according to claim 3, characterized in that said first condition is an error indication provided by the central processing unit.  5. Method for writing data to a memory device (127) contained in a system while reducing the alteration of the memory device (127), the memory device (127) having a data input and a write validation input , said method being characterized by the following operations:  writing a predetermined bit pattern to a logic device (403);  determining that said predetermined bit pattern is correct;  coupling a data producing device to the data input of the memory device (405);  producing, in response to the fact that it has been determined that said predetermined bit pattern is correct, a first signal (407); and  producing, in response to the production of said first signal, a second signal for a first predetermined duration (409), said second signal being applied to the write enable input of the memory device (127), so that the memory device (127) can only accept data during said first predetermined duration.  6. The method of claim 5, further characterized by the operation of producing a repositioning signal at a time intervening a second predetermined duration after the production of said write validation signal (411), said second predetermined duration being less or equal to said first predetermined duration, which has the effect of making said second signal inactive.  7. Method according to claim 5, characterized in that said first predetermined duration is equal to the time necessary to write in the memory device (127) the largest possible data block.  8. Method according to claim 7, characterized in that said second predetermined duration is equal to the time necessary to write in the memory device (127) a data block, where said data block is smaller than said most data block great possible.  9. Method according to claim 5, characterized by the operations consisting in comparing said second signal with said first signal and in creating a third signal, said third signal being activated in response to the production of said first and second signals, said third signal being applied at the write validation input of the memory device (127).  10. Method according to claim 5, characterized in that the data production device is associated with a microprocessor (121).