IT1161467B - Interfaccia di tipo parallelo per la gestione del colloquio tra un bus asincrono e un bus sincrono collegato a piu terminali dotati ognuno di un proprio segnale di sincronizzazione - Google Patents

Interfaccia di tipo parallelo per la gestione del colloquio tra un bus asincrono e un bus sincrono collegato a piu terminali dotati ognuno di un proprio segnale di sincronizzazione

Info

Publication number
IT1161467B
IT1161467B IT67070/83A IT6707083A IT1161467B IT 1161467 B IT1161467 B IT 1161467B IT 67070/83 A IT67070/83 A IT 67070/83A IT 6707083 A IT6707083 A IT 6707083A IT 1161467 B IT1161467 B IT 1161467B
Authority
IT
Italy
Prior art keywords
synchronization signal
multiple terminals
parallel interface
bus
terminals equipped
Prior art date
Application number
IT67070/83A
Other languages
English (en)
Other versions
IT8367070A0 (it
Inventor
Silvano Appiano
Paolo Destefanis
Cesare Poggio
Original Assignee
Cselt Centro Studi Lab Telecom
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Cselt Centro Studi Lab Telecom filed Critical Cselt Centro Studi Lab Telecom
Priority to IT67070/83A priority Critical patent/IT1161467B/it
Publication of IT8367070A0 publication Critical patent/IT8367070A0/it
Priority to JP59002745A priority patent/JPS59140536A/ja
Priority to CA000446872A priority patent/CA1203919A/en
Priority to EP84100565A priority patent/EP0116863A1/en
Priority to DE198484100565T priority patent/DE116863T1/de
Priority to US06/572,579 priority patent/US4639861A/en
Application granted granted Critical
Publication of IT1161467B publication Critical patent/IT1161467B/it

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Information Transfer Systems (AREA)
IT67070/83A 1983-01-21 1983-01-21 Interfaccia di tipo parallelo per la gestione del colloquio tra un bus asincrono e un bus sincrono collegato a piu terminali dotati ognuno di un proprio segnale di sincronizzazione IT1161467B (it)

Priority Applications (6)

Application Number Priority Date Filing Date Title
IT67070/83A IT1161467B (it) 1983-01-21 1983-01-21 Interfaccia di tipo parallelo per la gestione del colloquio tra un bus asincrono e un bus sincrono collegato a piu terminali dotati ognuno di un proprio segnale di sincronizzazione
JP59002745A JPS59140536A (ja) 1983-01-21 1984-01-12 複数個の端末装置に接続された非同期バスと同期バスとの間の２方向デ−タ転送を制御し、各端末装置はそれ自身の同期信号を前記同期バスに送る並列インタフエ−ス
CA000446872A CA1203919A (en) 1983-01-21 1984-01-16 Parallel interface for controlling the bidirectional data transfer between an asynchronous bus and a synchronous bus connected to a plurality of terminals each sending its own synchronism signal onto said synchronous bus
EP84100565A EP0116863A1 (en) 1983-01-21 1984-01-19 Interface for controlling the bidirectional data transfer between an asynchronous bus and a synchronous bus
DE198484100565T DE116863T1 (de) 1983-01-21 1984-01-19 Interface fuer die bidirektionelle datenuebertragungssteuerung zwischen einem asynchronbus und einem synchronbus.
US06/572,579 US4639861A (en) 1983-01-21 1984-01-20 Interface controlling bidirectional data transfer between a synchronous and an asynchronous bus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT67070/83A IT1161467B (it) 1983-01-21 1983-01-21 Interfaccia di tipo parallelo per la gestione del colloquio tra un bus asincrono e un bus sincrono collegato a piu terminali dotati ognuno di un proprio segnale di sincronizzazione

Publications (2)

Publication Number Publication Date
IT8367070A0 IT8367070A0 (it) 1983-01-21
IT1161467B true IT1161467B (it) 1987-03-18

Family

ID=11299341

Family Applications (1)

Application Number Title Priority Date Filing Date
IT67070/83A IT1161467B (it) 1983-01-21 1983-01-21 Interfaccia di tipo parallelo per la gestione del colloquio tra un bus asincrono e un bus sincrono collegato a piu terminali dotati ognuno di un proprio segnale di sincronizzazione

Country Status (6)

Country Link
US (1) US4639861A (it)
EP (1) EP0116863A1 (it)
JP (1) JPS59140536A (it)
CA (1) CA1203919A (it)
DE (1) DE116863T1 (it)
IT (1) IT1161467B (it)

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NL8502642A (nl) * 1985-09-27 1986-04-01 Oce Nederland Bv Raster-beeld-processor.
JP2749819B2 (ja) * 1987-10-26 1998-05-13 松下電工株式会社 共有メモリ制御方式
DD266436B3 (de) * 1987-12-11 1993-02-04 Jenoptik Jena Gmbh Systembuserweiterung zur kopplung multimasterfaehiger mehrrechnersysteme
US5060139A (en) * 1989-04-07 1991-10-22 Tektronix, Inc. Futurebus interrupt subsystem apparatus
JPH0324677A (ja) * 1989-06-21 1991-02-01 Oki Micro Design Miyazaki:Kk Ｃｐｕコア
DE69016991D1 (de) * 1989-08-18 1995-03-23 Schlumberger Technology Bv Gerät zum anschluss eines einen zentralprozessor enthaltenden zentralprozessorbus an einen peripheren bus, an den mehrere periphere geräte angeschlossen sind.
JPH0753422Y2 (ja) * 1991-03-19 1995-12-06 株式会社安川電機 扁平形直流電動機
US5265216A (en) * 1991-06-28 1993-11-23 Digital Equipment Corporation High performance asynchronous bus interface
US5576554A (en) * 1991-11-05 1996-11-19 Monolithic System Technology, Inc. Wafer-scale integrated circuit interconnect structure architecture
US5831467A (en) * 1991-11-05 1998-11-03 Monolithic System Technology, Inc. Termination circuit with power-down mode for use in circuit module architecture
DE69226150T2 (de) * 1991-11-05 1999-02-18 Hsu Fu Chieh Redundanzarchitektur für Schaltungsmodul
US5498990A (en) * 1991-11-05 1996-03-12 Monolithic System Technology, Inc. Reduced CMOS-swing clamping circuit for bus lines
JPH05324546A (ja) * 1992-05-18 1993-12-07 Canon Inc 情報処理システム
JPH08500687A (ja) * 1992-08-10 1996-01-23 モノリシック・システム・テクノロジー・インコーポレイテッド ウェハ規模の集積化のためのフォルトトレラントな高速度のバス装置及びバスインタフェース
US5339395A (en) * 1992-09-17 1994-08-16 Delco Electronics Corporation Interface circuit for interfacing a peripheral device with a microprocessor operating in either a synchronous or an asynchronous mode
US5715396A (en) * 1992-10-13 1998-02-03 Bay Networks, Inc. Method for providing for automatic topology discovery in an ATM network or the like
US5694547A (en) * 1992-10-13 1997-12-02 Bay Networks, Inc. System for registration of clients in an ATM network providing for communication of client registration messages to a central manager
US5420853A (en) * 1993-04-05 1995-05-30 Motorola, Inc. Self controlling crossbar switch and method
US6067408A (en) * 1993-05-27 2000-05-23 Advanced Micro Devices, Inc. Full duplex buffer management and apparatus
JPH0779233A (ja) * 1993-06-29 1995-03-20 Synoptics Commun Inc トポロジを確定する装置及びトポロジ情報を通信する方法及び装置
US5655113A (en) 1994-07-05 1997-08-05 Monolithic System Technology, Inc. Resynchronization circuit for a memory system and method of operating same
US6128689A (en) * 1997-04-14 2000-10-03 Hms Fieldbus Systems Ab System for exchanging data through data memory area of common memory in synchronous and asynchronous modes
US6014036A (en) 1997-11-20 2000-01-11 International Business Machines Corporation Bidirectional data transfer path having increased bandwidth
US6578086B1 (en) 1999-09-27 2003-06-10 Nortel Networks Limited Dynamically managing the topology of a data network
KR100453071B1 (ko) * 2003-01-18 2004-10-15 삼성전자주식회사 프로세서 버스 연결 장치 및 방법
US9489009B2 (en) 2014-02-20 2016-11-08 Samsung Electronics Co., Ltd. System on chip, bus interface and method of operating the same

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3558811A (en) * 1967-05-25 1971-01-26 Xerox Corp Graphic communication electrical interface system
US3825901A (en) * 1972-11-09 1974-07-23 Ibm Integrated diagnostic tool
US4218740A (en) * 1974-10-30 1980-08-19 Motorola, Inc. Interface adaptor architecture
IT1111606B (it) * 1978-03-03 1986-01-13 Cselt Centro Studi Lab Telecom Sistema elaborativo modulare multiconfigurabile integrato con un sistema di preelaborazione
US4379327A (en) * 1980-07-21 1983-04-05 Motorola, Inc. Universal interface circuit for synchronous and asynchronous buses
GB2099619B (en) * 1981-05-29 1985-09-18 Gen Electric Plc Data processing arrangements

Also Published As

Publication number Publication date
EP0116863A1 (en) 1984-08-29
IT8367070A0 (it) 1983-01-21
CA1203919A (en) 1986-04-29
US4639861A (en) 1987-01-27
DE116863T1 (de) 1985-05-09
JPS59140536A (ja) 1984-08-11

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