GB964901A - A synchronising system for a time division multiplex pulse code modulation system - Google Patents

Abstract

964,901. Multiplex pulse code signalling. NIPPON ELECTRIC CO. Ltd. Feb. 10, 1961 [Feb. 12, 1960], No. 5044/61. Heading H4L. A pulse code modulation time division multiplex receiving system in which the synchronizing signals consist of (a) a series of "1" signals, or (b) a series of "0" signals, appearing in succeeding time slots, comprises means for generating clock pulses coincident with and having a repetition frequency equal to that of the incoming pulse train, a channel separator operable step-by-step in response to the clock pulses to separate the synchronizing and signalling channels, and means responsive to the failure of a time coincident comparison between the incoming synchronizing signals and the signals appearing at the output of the synchronizing channel to reset the channel separator to the position immediately prior to the first digit position of the synchronizing code. As shown, in a system using a series of " 1 " signals for synchronizing, clock pulses are generated at 2 from the incoming signal and supplied to the channel separator 3 controlling the decoder 4. The clock pulses and the synchronizing channel output from the channel separator 3 are supplied to an AND gate 7 and the incoming signal and the synchronizing channel output are supplied to a further AND gate 5, the two AND gates being connected to an EXCLUSIVE OR circuit 6. If the pulses at both inputs of circuit 6 coincide, showing correct synchronizing, no output results, but if the pulses are not in coincidence a signal from circuit 6 returns the channel separator to the zero position, i.e. one bit before the beginning of the synchronizing signal. This process is repeated until synchronism is restored. In a modification, Fig. 4 (not shown), a series of " 0 " signals are used for the synchronizing signal and the AND gate 7 and EXCLUSIVE OR circuit 6 are dispensed with. If the synchronizing channel output from the channel selector 3 and the series of " 0 " signals forming the synchronizing signal are not coincident at the AND gate 5, denoting an error, an output signal from the gate 5 operates on the channel selector 3 as before. Specification 891,918 is referred to.