GB8725497D0 - Isolation of silicon - Google Patents

Isolation of silicon

Info

Publication number
GB8725497D0
GB8725497D0 GB878725497A GB8725497A GB8725497D0 GB 8725497 D0 GB8725497 D0 GB 8725497D0 GB 878725497 A GB878725497 A GB 878725497A GB 8725497 A GB8725497 A GB 8725497A GB 8725497 D0 GB8725497 D0 GB 8725497D0
Authority
GB
United Kingdom
Prior art keywords
isolation
silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
GB878725497A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
UK Atomic Energy Authority
Original Assignee
UK Atomic Energy Authority
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by UK Atomic Energy Authority filed Critical UK Atomic Energy Authority
Priority to GB878725497A priority Critical patent/GB8725497D0/en
Publication of GB8725497D0 publication Critical patent/GB8725497D0/en
Priority to GB8825311A priority patent/GB2211991B/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26533—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically inactive species in silicon to make buried insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Element Separation (AREA)
GB878725497A 1987-10-30 1987-10-30 Isolation of silicon Pending GB8725497D0 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
GB878725497A GB8725497D0 (en) 1987-10-30 1987-10-30 Isolation of silicon
GB8825311A GB2211991B (en) 1987-10-30 1988-10-28 Electrical isolation of regions within semiconductor bodies

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB878725497A GB8725497D0 (en) 1987-10-30 1987-10-30 Isolation of silicon

Publications (1)

Publication Number Publication Date
GB8725497D0 true GB8725497D0 (en) 1987-12-02

Family

ID=10626199

Family Applications (2)

Application Number Title Priority Date Filing Date
GB878725497A Pending GB8725497D0 (en) 1987-10-30 1987-10-30 Isolation of silicon
GB8825311A Expired - Fee Related GB2211991B (en) 1987-10-30 1988-10-28 Electrical isolation of regions within semiconductor bodies

Family Applications After (1)

Application Number Title Priority Date Filing Date
GB8825311A Expired - Fee Related GB2211991B (en) 1987-10-30 1988-10-28 Electrical isolation of regions within semiconductor bodies

Country Status (1)

Country Link
GB (2) GB8725497D0 (en)

Families Citing this family (41)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2681472B1 (en) * 1991-09-18 1993-10-29 Commissariat Energie Atomique PROCESS FOR PRODUCING THIN FILMS OF SEMICONDUCTOR MATERIAL.
FR2714524B1 (en) * 1993-12-23 1996-01-26 Commissariat Energie Atomique PROCESS FOR MAKING A RELIEF STRUCTURE ON A SUPPORT IN SEMICONDUCTOR MATERIAL
US7148119B1 (en) 1994-03-10 2006-12-12 Canon Kabushiki Kaisha Process for production of semiconductor substrate
JP3352340B2 (en) * 1995-10-06 2002-12-03 キヤノン株式会社 Semiconductor substrate and method of manufacturing the same
EP0703608B1 (en) * 1994-09-23 1998-02-25 Consorzio per la Ricerca sulla Microelettronica nel Mezzogiorno - CoRiMMe Method for forming buried oxide layers within silicon wafers
FR2748851B1 (en) 1996-05-15 1998-08-07 Commissariat Energie Atomique PROCESS FOR PRODUCING A THIN FILM OF SEMICONDUCTOR MATERIAL
FR2756847B1 (en) 1996-12-09 1999-01-08 Commissariat Energie Atomique METHOD FOR SEPARATING AT LEAST TWO ELEMENTS OF A STRUCTURE IN CONTACT WITH THEM BY ION IMPLANTATION
US6013563A (en) 1997-05-12 2000-01-11 Silicon Genesis Corporation Controlled cleaning process
US6291313B1 (en) 1997-05-12 2001-09-18 Silicon Genesis Corporation Method and device for controlled cleaving process
US6033974A (en) 1997-05-12 2000-03-07 Silicon Genesis Corporation Method for controlled cleaving process
US20070122997A1 (en) 1998-02-19 2007-05-31 Silicon Genesis Corporation Controlled process and resulting device
EP0889505B1 (en) * 1997-07-03 2005-06-08 STMicroelectronics S.r.l. Process for cutting trenches in a single crystal substrate
US6548382B1 (en) 1997-07-18 2003-04-15 Silicon Genesis Corporation Gettering technique for wafers made using a controlled cleaving process
FR2773261B1 (en) 1997-12-30 2000-01-28 Commissariat Energie Atomique METHOD FOR THE TRANSFER OF A THIN FILM COMPRISING A STEP OF CREATING INCLUSIONS
FR2774510B1 (en) * 1998-02-02 2001-10-26 Soitec Silicon On Insulator PROCESS FOR TREATING SUBSTRATES, ESPECIALLY SEMICONDUCTORS
US6291326B1 (en) 1998-06-23 2001-09-18 Silicon Genesis Corporation Pre-semiconductor process implant and post-process film separation
US6263941B1 (en) 1999-08-10 2001-07-24 Silicon Genesis Corporation Nozzle for cleaving substrates
US6500732B1 (en) 1999-08-10 2002-12-31 Silicon Genesis Corporation Cleaving process to fabricate multilayered substrates using low implantation doses
FR2823596B1 (en) 2001-04-13 2004-08-20 Commissariat Energie Atomique SUBSTRATE OR DISMOUNTABLE STRUCTURE AND METHOD OF MAKING SAME
FR2823599B1 (en) 2001-04-13 2004-12-17 Commissariat Energie Atomique DEMOMTABLE SUBSTRATE WITH CONTROLLED MECHANICAL HOLDING AND METHOD OF MAKING
JP4277481B2 (en) * 2002-05-08 2009-06-10 日本電気株式会社 Semiconductor substrate manufacturing method and semiconductor device manufacturing method
JP2004063730A (en) * 2002-07-29 2004-02-26 Shin Etsu Handotai Co Ltd Manufacturing method for soi wafer
US8187377B2 (en) 2002-10-04 2012-05-29 Silicon Genesis Corporation Non-contact etch annealing of strained layers
FR2848336B1 (en) 2002-12-09 2005-10-28 Commissariat Energie Atomique METHOD FOR PRODUCING A STRESS STRUCTURE FOR DISSOCIATING
FR2849017B1 (en) * 2002-12-20 2005-11-18 Michel Bruel METHOD FOR PROCESSING A STRUCTURE FOR OBTAINING INTERNAL SPACE AND STRUCTURE HAVING INTERNAL SPACE
FR2856844B1 (en) 2003-06-24 2006-02-17 Commissariat Energie Atomique HIGH PERFORMANCE CHIP INTEGRATED CIRCUIT
FR2857953B1 (en) 2003-07-21 2006-01-13 Commissariat Energie Atomique STACKED STRUCTURE, AND METHOD FOR MANUFACTURING THE SAME
FR2861497B1 (en) 2003-10-28 2006-02-10 Soitec Silicon On Insulator METHOD FOR CATASTROPHIC TRANSFER OF A FINE LAYER AFTER CO-IMPLANTATION
FR2889887B1 (en) 2005-08-16 2007-11-09 Commissariat Energie Atomique METHOD FOR DEFERING A THIN LAYER ON A SUPPORT
FR2891281B1 (en) 2005-09-28 2007-12-28 Commissariat Energie Atomique METHOD FOR MANUFACTURING A THIN FILM ELEMENT
DE102006004870A1 (en) * 2006-02-02 2007-08-16 Siltronic Ag Semiconductor layer structure and method for producing a semiconductor layer structure
US9362439B2 (en) 2008-05-07 2016-06-07 Silicon Genesis Corporation Layer transfer of films utilizing controlled shear region
US8993410B2 (en) 2006-09-08 2015-03-31 Silicon Genesis Corporation Substrate cleaving under controlled stress conditions
US8293619B2 (en) 2008-08-28 2012-10-23 Silicon Genesis Corporation Layer transfer of films utilizing controlled propagation
US7811900B2 (en) 2006-09-08 2010-10-12 Silicon Genesis Corporation Method and structure for fabricating solar cells using a thick layer transfer process
FR2910179B1 (en) 2006-12-19 2009-03-13 Commissariat Energie Atomique METHOD FOR MANUFACTURING THIN LAYERS OF GaN BY IMPLANTATION AND RECYCLING OF A STARTING SUBSTRATE
FR2925221B1 (en) 2007-12-17 2010-02-19 Commissariat Energie Atomique METHOD FOR TRANSFERRING A THIN LAYER
US8330126B2 (en) 2008-08-25 2012-12-11 Silicon Genesis Corporation Race track configuration and method for wafering silicon solar substrates
US7927975B2 (en) 2009-02-04 2011-04-19 Micron Technology, Inc. Semiconductor material manufacture
US8329557B2 (en) 2009-05-13 2012-12-11 Silicon Genesis Corporation Techniques for forming thin films by implantation with reduced channeling
FR2947098A1 (en) 2009-06-18 2010-12-24 Commissariat Energie Atomique METHOD OF TRANSFERRING A THIN LAYER TO A TARGET SUBSTRATE HAVING A THERMAL EXPANSION COEFFICIENT DIFFERENT FROM THAT OF THE THIN LAYER

Also Published As

Publication number Publication date
GB8825311D0 (en) 1988-11-30
GB2211991A (en) 1989-07-12
GB2211991B (en) 1991-02-20

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