GB2592672A - A high-speed data link (HSDL)-peripheral component interconnect express (PCIe) interface for establishing communication in vehicles - Google Patents

Abstract

The present disclosure relates to a High-Speed Data Link (HSDL) - Peripheral Component Interconnect Express (PCIe) interface for establishing communication between a host terminal and one or more device terminals over a High-Speed Data Link (HSDL) cable channel in a vehicle. The HSDL-PCIe interface is configured in each of the host and the one or more device terminal. The interface comprises a Peripheral Component Interconnect Express (PCIe) switch comprises at least one of an upstream port and a downstream port. The interface comprises an HSDL physical layer for facilitating communication between host terminal and device terminal over a HSDL cable channel. The HSDL physical layer of the host terminal is configured to transmit data packets from the upstream port over the HSDL cable channel, and the HSDL physical layer of the at least one device terminal receives the data packets and routes the data packets to the corresponding downstream port

Description

TITLE OF THE INVENTION

A HIGH-SPEED DATA LINK (HSDL)-PERIPHERAL COMPONENT INTERCONNECT EXPRESS (PC1e) INTERFACE FOR ESTABLISHING

COMMUNICATION IN VEHICLES

[1] PREAMBLE TO THE DESCRIPTION

[2] The following specification particularly describes the invention and the manner in which it is to be performed:

[3] DESCRIPTION OF THE INVENTION:

[4] Technical field

[5] The present disclosure relates to establishing a High-Speed Data Link via a cable channel interconnect between terminals in vehicles. The present disclosure is also applicable to high-speed data links in general. More particularly, but not specifically, the present disclosure relates to an automotive cable channel referred to as a High-Speed Data Link (HSDL) that is used as an interconnect between Electronic Control Units (ECUs) or other endpoints in a vehicle provisioning a Peripheral Component -Interconnect Express (PCIe0) link as established by the PCI Express Base Specification and the relevant specification framework published by PCI-SIG. PCI Express® or PCIe® are registered trademarks of PCI-SIG. The PCI Express Base Specification is a Copyright 0 of PCI-SIG.

[6] Background of the disclosure

[7] Typically, multiple ECUs are utilized to control and operate automobiles. In-vehicle networking is an internal communication network that interconnects the ECUs via a distributed field bus. The ECUs communicate with each other and with a gateway/Main Controller Unit (MCU) using standard in-vehicle field bus protocols like Controller Area Network (CAN), Local Interconnect Network (LIN), FlexRay' or Media Oriented Systems Transport (MOST'). The ECUs use the distributed field bus in a time-shared basis for establishing communication between one another. The ECUs present in the automobiles follow a System on Chip (SoC) architecture. Conventional vehicle platform architectures include a variety of ECUs comprising specific modules for implementing specific functionalities. The specific modules generally include protocol-specific connection interfaces present in a SoC that connect to the peripheral devices via protocol-specific plugs and cables. For example, a vehicle may include one or more USB-speci fie controllers that connect to a peripheral device via a US B-specific connection interface, a display-specific controller (e.g.. DisplayPort) that connects to a peripheral device via a display-specific connection interface, a PCI Express controller that connects to a peripheral device via a PCIe specific connection interface, and so on.

[8] Each of the protocol specific connection interfaces operate at different speeds and operating bandwidths. Due to an increase in consumer demand for advanced driver assistance and infotainment features, use of Automotive Ethernet is increased. Automotive Ethernet is an Ethernet-based network for connections between in-vehicle ECUs. A physical network is used to connect components within a car using a wired network. It is designed to meet the needs of the automotive market, including meeting electrical requirements, bandwidth requirements, latency requirements, synchronization and network management requirements. Ethernet is preferred for connection between distant entities and not preferably meant for a distributed field bus/instrument bus as present in vehicles. Moreover, Ethernet has high latency and limited bandwidth. For instance, Gigabit Ethernet has a maximum bandwidth of 125 MB/s. Ethernet. latency is measured in tens of microseconds. Peripheral Component Interconnect Express (PCIe) protocol is a well-established protocol, which provides scalable Bandwidth options and supports switch-based fabrics for connecting seamlessly with many devices. PCIe utilizes a serial interconnect and a packet-based protocol and has a plurality of advantages compared to Ethernet. Further the problem of requirements for protocol specific connection interfaces may be resolved by using PCIe as the interconnect of choice. However existing specifications for transmission of native PCIe signalling over long cables e.g. the PCI Express@ External Cabling Specification and the PCI Express@ OCuLink are limited by the associated link margin of a given cable, and specifically for automotive use by the size and cost of the required wired interconnects for each transmit and receive pair as well as sideband signals. Therefore, there is need of a system for improving channel capacity, speed and latency as well as simplifying the system infrastructure of interconnects between modules present at longer distances and to overcome die disadvantages as mentioned above.

[9] While existing solutions provide a robust way for transmission of message signals within the modules present in a vehicle network, implementation of scalable bandwidth along with low latency remain problematic. One such conventional arrangement employed in the vehicles is disclosed in US9720871B2 to AiToyo et al. Arroyo et al. disclose electronic signalling links formed of multiple cables, with more particular aspects relate to determining connections between devices using cables forming a single link. Thus, Arroyo et al. use separate signalling links formed of multiple cables in order to transmit data between devices.

[0010] The information disclosed in this background of the disclosure section is only for the enhancement of understanding of the general background of the invention and should not be taken as an acknowledgement or any form of suggestion that this information forms the prior art already known to a person skilled in the art.

[0011] SUMMARY OF THE DISCLOSURE

[0012] In an embodiment, the present disclosure relates to a High-Speed Data Link (HSDL) in a vehicle that is comprised of an automotive cable channel that is attached to a pair of integrated circuit devices (HSDL-IC), where one such HSDL-IC is attached to each end of the cable channel. This High-Speed Data Link is a part of a PCIe-Fabric and forms an interface for establishing communication between two or more PCIe-Devices. Such a PCIe-Device can be a PCIe-Host (Host, Root Complex), or a PCTe-End Point (End Point), or an additional HSDLPHY (physical) port extending the link to attach additional HSDL-ICs and PCIe-Devices to the PCIe-Fabric. This High-Speed Data Link transports or tunnels a PCIe transaction protocol routed between a requester and a completer of the PCIe-Fabric. The PCIe Ports at the system interface terminal of the HSDL-IC are compliant with the PCIe Data Link and physical layer specification, and the HSDL-IC devices act together as a PCIe-Bridge or as PCIe-S witch across automotive cable channels routing the PCIe transaction layer packet point-to-point between a requester and a completer.

[0013] In another embodiment, the present disclosure relates to a High-Speed Data Link (HSDL) where the terminals of this link provide a PCI Express® interface for establishing communication between at least one requester e.g. a PCIe Host (Root Complex) and at least. one completer e.g. a PCIe device (End Point), and where each terminal of this link implements or represents a PCIe compliant Port configured as either a Downstream Port (DSP) or Upstream Port (USP), and where the PCIe protocol and data traffic between the two terminals is transported or tunnelled over a high capacity low latency link utilizing unspecified hut sufficient physical signalling technologies and routing, transport or tunnelling protocols. This HSDL interface is configurable in each of its terminals and may also transport sideband signals and other interfaces along with PCIe. Each HSDL terminal of this link provides for at least one PCIe compliant port that connects the HSDL to a host or an endpoint through either a Downstream Port or an Upstream Port as appropriate. The cable channel of this Link is terminated at each end by the HSDL-PHY. The HSDL-PHY is an interface of the HSDL-IC that transmits and receives the HSDL signals via the automotive cable channel.

[0014] The foregoing summary is illustrative only and is not intended to be in any way limiting. In addition to the illustrative aspects, embodiments, and features described above, further aspects, embodiments, and features will become apparent by reference to the drawings and the following detailed description.

[0015] BRIEF DESCRIPTION OF THE ACCOMPANYING DRAWINGS [0016] The novel features and characteristic of the disclosure are set forth in the appended claims. The disclosure itself, however, as well as a preferred mode of use, further objectives and advantages thereof, will best be understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying figures. One or more embodiments are now described, by way of example only, with reference to the accompanying figures wherein like reference numerals represent like elements and in which: [0017] Figure 1 shows a general architecture in a vehicle, in accordance with some embodiments of the present disclosure; [0018] Figure 2 shows an architecture of a PCIe topology associated with a SoC, in accordance with some embodiments of the present disclosure; [0019] Figure 3A shows an architecture of an HSDL-PCIe interface, in accordance with some embodiments of the present disclosure; [0020] Figure 3B shows an arrangement indicating the HSDL-PCIe interface configured in the host and device terminal, in accordance with some embodiments of the present disclosure; [0021] Figure 4 illustrates a centralized head unit, in accordance with some embodiments of the present disclosure; [0022] Figure 5 illustrates a distributed head unit, in accordance with some embodiments of the present disclosure; and, [0023] Figure 6 illustrates a HSDL T-Bridge, in accordance with some embodiments of the present disclosure.

[0024] It should be appreciated by those skilled in the art that any block diagrams herein represent conceptual views of illustrative systems embodying the principles of the present subject matter. Similarly, it will be appreciated that any flow charts, flow diagrams, state transition diagrams, pseudo code, and the like represent various processes which may be substantially represented in computer readable medium and executed by a computer or processor, whether or not such computer or processor is explicitly shown.

[0025] DETAILED DESCRIPTION

[0026] In the present document, the word 'exemplary" is used herein to mean "serving as an example, instance, or illustration." Any embodiment or implementation of the present subject matter described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.

[0027] While the disclosure is susceptible to various modifications and alternative forms, specific embodiment thereof has been shown by way of example in the drawings and will be described in detail below. It should be understood, however that it is not intended to limit the disclosure to the particular forms disclosed, but on the contrary, the disclosure is to cover all modifications, equivalents, and alternative falling within the scope of the disclosure.

100281 The terms "comprises", "comprising", or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a setup, device or method that comprises a list of components or steps does not include only those components or steps but may include other components or steps not expressly listed or inherent to such setup or device or method. In other words, one or more elements in a system or apparatus proceeded by "comprises.., a" does not, without more constraints, preclude the existence of other elements or additional elements in the system or apparatus.

[0029] Embodiments of the present disclosure relate to a Peripheral Component Interconnect Express (PC1e) High-Speed Data Link (HSDL), which is an interface for establishing communication between PCIe devices over a High-Speed Data Link (HSDL) via an Automotive Cable Channel in a vehicle.

100301 A High-Speed Data Link (HSDL) as envisioned in this disclosure is a wired interface used in a vehicle that typically connects two ECUs or an ECU with an attached subsystem through the use of an Automotive Cable Channel. Examples of attached subsystems are control units, storage, sensors, wireless or wired communication systems, customer data and video ports or maintenance ports. HSDLs are used for protocol-specific interfaces requiring high capacity data channels with low latency. Examples of these protocol-specific interfaces arc PCI Express, USB, protocols defined for USB Alternate Mode, Gigabit Ethernet or sideband channel aggregates of lower speed protocols e.g. UART, I2C, I2S, SPI, CAN, etc. Sidcband signals are also used for configuration and monitoring of link integrity and system status.

100311 A High-Speed Data Link is typically comprised of a pair of integrated circuits (HSDLICs) and an Automotive Cable Channel. The HSDL-IC integrates a transmitter and receiver which is the HSDL-PHY port of the HSDL-IC. The HSDL-PHY is connected to an impedance matched transmission line that spans from one HSDL-IC located in one ECU via an Automotive Cable Channel to the HSDL-PHY of the second HSDL-IC located on an ECU or subsystem at the other end of the cable channel. Each HSDL-IC supports selected protocol-specific ports on its system-side interface referred to as the system interface terminals or the HSDL-Terminal. Signals present on ingress ports of one HSDL Terminal are routed via the pair of HSDL-ICs to the egress ports of the other HSDL-Terminal and vice versa, or in case of a Daisy Chain or Ring Topology the signals will be routed from HSDL-PHY to HSDL-PHY to the destination egress port off the destination HSDL-IC. For PCIe, -signals present" relates to the Transaction Layer Packet (TLP).

100321 PCIe HSDL-ICs include one or more PCIe Port on the HSDL-Terminal. The HSDLTerminal implements for each PCIe Port all mandatory functions from link training and link initialization, to interfacing with, or terminating the PCIe Physical Layer and the PCIe Data Link layer and to act like a PCI Express Packet Switch spanning across the High-Speed Data Link. In a simple point-to-point link with a single PCTe Port on each HSDL-Terminal, the HSDL-IC utilizes the same or equivalent functions of a PCIe packet switch to route the PCIe Transaction Layer Protocol via bridges from one HSDL-1C to the other across the Automotive Cable Channel, where the data channel between the two bridges is stretched across the link. Since the link between two FISDL-ICs is using different methods of transport, a bridge may be implemented differently as a typical PCI-Bridge. Special attention is required for the handling of data commtion (Bit Errors) occurring on PCIe packets (TLPs) crossing the cable channel. Different methods are possible, however some implementations may cause compliance violations or interoperability issues that need to be resolved before traffic is bridged between the PCIe protocol layers of the system interfaces. Possible solutions are to use error correction (e.g. FEC) or to treat the cable channel as a virtual PCIe link with its own Data Link Layer for TLP Error correction and flow control, not excluding other methods.

[0033] PCIe HSDL-Terminal Ports with multiple lanes may support bifurcation and fan-out or aggregation of PCIe traffic. For HSDL-ICs used in Daisy Chain or Ring Topologies, a PCIe Switch with fan-out and aggregate functionality is needed. Other features to include are support for Reset, Interrupt, Wake and Hot-insert signalling and propagation, as well as power state configuration of all ports. The implementation of a Non-Transparent Bridge (NTB) for Hostto-Host communication as well as measures for channel security such as authentication and encryption are also desirable.

[0034] Further, the envisioned HSDL-IC utilizes existing or future physical layer technology with transmitter and receiver interfaces DL-PH Y) capable of transmitting and receiving the aggregate of the signals present at the HSDL Terminal over a twisted pair, a parallel pair or a coaxial cable with sufficient link margin and bit-error rate sustaining system fidelity with low retry counts. HSDL-ICs are utilizing state of the art packet framing and routing techniques along with encoding, multiplexing, serialization and/or signal modulation to allow for a reliable and maintainable point-to-point link. When both, transmit and receive circuits of the HSDLPHY operate at the same bandwidth, this is referred to as a symmetric channel. Depending on the HSDL-PHY design and or cable loss limitations, the link may utilize asymmetric channels with complementary asymmetric HSDL-PHYs on each end of the cable channel, e.g. an asymmetric cable channel is transporting the PCI Express downstream and the PCI Express upstream parts of a link over a separate cable. It should be noted that the physical layer signalling of the HSDL-PHY does not comply with the physical layer requirements of the PCIe interfaces at the HSDL-Terminal and therefore allows for longer cables runs.

[0035] The Automotive Cable Channel for HSDL is comprised of a durable cable assembly with connectors attached on both ends, and with the mating connectors fitted as cable ports on ECUs or subsystems. In-line cable extensions arc permissible with an anticipated overall cable length of 15m or more. The Automotive Cable Channel provides an impedance matched transmission line with adequate insertion and return loss, supporting a sufficient link margin for the intended HSDL bandwidth, signal modulation and encoding. The Automotive Cable Channel may use a replication of cable assemblies and connector interfaces to support asymmetric HSDL-PHY ports or multiple HSDL-PHY lanes of symmetric or asymmetric channels within one link.

100361 High Speed Data Link topologies range from simple full duplex end-to-end to complex full duplex or dual simplex daisy chain or ring architectures. A link "AB" with a lowest complexity for example is an HSDL between a Headunit and a PCIe-to-USB3.0 bridge providing customer USB port connectivity. This link utilises HSDL-ICs with a single PCIe Port on HSDL-Terminal "A" and "B", a single symmetric HSDL-PHY on cable port "A" and "B", and a cable channel with one A-to-B lane.

100371 A daisy chain link "ABC" can be used to provide multiple separate USB access points utilizing two HSDL-ICs with a single PCIe Port on HSDL-Terminals "A" and "C", single symmetric HSDL-PHY on cable ports "A" and "C", one HSDL-IC with a single PCIe Port on HSDL-Terminal "B", two symmetric HSDL-PIYs on cable ports "B I" and "B2", and two cable channels with one A-to-Bl lane and one B2-to-C lane.

[0038] A dual redundant "Primary ABCDA" and "Secondary ADCB A" ring can be envisioned for interfacing four ADAS-ECUs A. B, C and D over a dual counter-rotating full duplex ring architecture, or a dual counter-rotating dual simplex ring architecture. The dual counter-rotating full duplex ring architecture requires HSDL-ICs with two PCIe Ports (Primary and Secondary) on the EISDL-Terminal, four symmetric FISDL-PHYs and four HSDL cable ports on each ECU (two each for the primary ring and two each for the secondary ring), and four cable channels for Ring 1: lane AP2BP1, BP2CP1, CP2DP1, DP2AP1; and four cable channels for Ring 2: lane AS3DS4, DS3CS4, CS3BS4, BS3AS4. Full redundancy can be achieved by duplicating the 1-ISDL-ICs and its supply in each ECU, and to use the 2nd PCIe HSDL-Terminal port as a cross channel link.

[0039] A PCI Express Root Complex connects a host (compute device) and its memory subsystem to a PCIe fabric using at least one Downstream Port. A host or compute device may also connect to the PCIe fabric of another Root Complex as a PCIe Endpoint using an Upstream Port. Hosts implement PCIe transaction protocol requesters and completers. Typical automotive PCI Express compute devices are e.g.: CPU, GPU, AT and ML Accelerators, and SoC components.

[0040] A PCI Express Endpoint is a device or component that implements 1 to 8 PCIe Functions or in other words a PC le transaction protocol requester and/or completer. PCI Express Endpoints have a single Upstream Port. Typical automotive PCI Express Functions are e.g. modems and NVMe Storage Devices Controllers, USB Controllers, Ethernet Controllers, Display Controllers and SoC or compute devices with configurable PCIe ports.

[0041] A PCI Express Switch is a packet router that is used to fan-out or aggregate PCIe traffic between PCIe requesters and completers of a PCIe fabric. A PCI Express Switch is used where a direct point-to-point link between a requester and a completer within the PCle fabric is not possible because of the lack of available ports. Switches use virtual PCI-to-PCI Bridges to route PCI Express packets between multiple PCIe devices. PCIe Switches support multiple virtual channels, port arbitration, Quality of Service (QoS), interrupt messaging and routing, wake signalling, power management, and more. Routing PCI Express packets from Host-to-Host is possible but requires address translation usually implemented via non-transparent bridges (NTB) and doorbell registers. Once configured, switches are typically handled natively by operating systems, and are enumerated and appear as a group of bridges. However, QoS and NTBs require special handling and fine-tuned drivers.

Switches support fan-out through lane partitioning into multiple links They also support reset, interrupt, wake and hot-insert signalling and propagation, as well as power state configuration of all ports. Like every PC le device, Switches comply with the PCIe Data Link Layer Protocol (DLLP) and the PCIe Physical Layer and perform PCIe link training and initialization on all upstream and downstream ports. The DLLP performs PCIe link data integrity checks and handles flow control with sequence numbers, retry buffers, retransmission requests and the Ack/Nak Protocol and latency timer.

[0042] Figure 1 is indicative of a general architecture 100 in accordance with some embodiments of the present disclosure. The general architecture 100 comprises a plurality of nodes, for example a node 101a, node 101b, node 101c, to node 101n, a gateway 102 and a distributed field bus 104. The node 101a, node101b, node 101c, to node 101n may be referred to as a plurality of nodes 101 hereafter in the present disclosure. In an embodiment, the plurality of nodes 101 may also be referred as a plurality of modules 101. The distributed field bus 104 interconnects the plurality of nodes 101 and the gateway 102. The gateway 102 facilitates communication between the plurality of nodes 101. In a vehicle network, the plurality of nodes 101 represents plurality of Electronic Control Units (ECUs) 101 configured in the vehicle. The gateway 102 may also be referred as a Main Controller Unit (MCU) in case of the vehicle network. In the vehicle network, the gateway 102 separates the plurality of ECUs 101 and onboard diagnostics (OBD) (not shown) and divides the in-vehicle network into functional domains like body control module, chassis control module, power train control module, infotainment module. Each functional domain may comprise one or more modules. A module present in one functional domain may communicate with a module of another functional domain via the gateway/ MCU 102. Each functional domain may use a specific network protocol. The plurality of modules may be connected to the distributed field bus using Ethernet cables or standard twisted pair cables by physical hard-wired point to point connection. The gateway 102 is responsible for communication between the functional domains. Each of the functional domains is growing in complexity and may require more powerful SoCs or additional ECUs. With the increased complexity, it is difficult to implement exchange of information supporting high speed / high data rates using the Ethernet cables as it would require a disproportionate length of cable, an increase of cost and production time and reliability problems. Even though, SoC devices support PCIe channels and have built in PCIe ports, the existing cable channel technologies implement a PCIe based on the current interface specification that carry the protocol in it's native form. This is not attractive for automotive use cases with cost, size and length constraints, e.g. typical cable channels require unshielded or shielded twisted pair, or coax with a length of 15m.

[0043] Figure 2 shows an architecture of a PCIe topology associated with a SoC, in accordance with some embodiments of the present disclosure. The SoC 200 is a system, which combines the required electronic circuits of various components onto a single, integrated chip (IC). SoC is a complete electronic substrate system that may contain analog, digital, mixed-signal or radio frequency functions. Its components usually include a graphical processing unit (GPU), a central processing unit (CPU) that may be multi-core, and system memory (RAM). The SoC 200 is associated with a root complex 201. The root complex 201 connects the SoC 200 and memory to a PCIe switch 202 comprising a switch fabric composed of one or more switch devices. The root complex 201 generates transaction requests on behalf of the SoC 200, which is interconnected through a local bus. The functionality of the root complex 201 may be implemented as a discrete device or may be integrated with the SoC 200. The root complex 201 may contain more than one PCIe ports and multiple switch devices can be connected to ports on the root complex 201. One or more PCIe endpoint 203 are connected to the PCIe switch 202. Each of the one or more PCIe endpoint 203 may be PCIe device. One PCIe device is connected to a port of the PCIe switch 202. The PCIe switch 202 routes data packets between ports. The PCIe is a point to point topology where separate serial links connect every PCIe endpoint 203 to the root complex 201. PCIe devices communicate via the serial links (logical connection). A serial link is a point-to-point communication channel between two PCIe ports allowing both of them to send and receive ordinary PCI requests (configuration, 1/0 or memory read/write) and interrupts (INTx, MSI or MSI-X). At the physical level a link is composed of one or more lanes. Each lane may be used as a full-duplex byte stream, transporting data packets in eight-bit "byte" format simultaneously in both directions between endpoints of a link. Physical PCI Express links may contain from one to 32 lanes, more precisely 1, 2, 4, 8, 12, 16 or 32 lanes. Lane counts are written with an "x" prefix (for example, "x8" represents an eight-lane PCIe card or PCIe slot). The PCIe switch 202 comprises at least one upstream port and one or more downstream ports. The upstream port points towards the root complex 201 and the downstream port points in a direction away from the root complex 201. When the PCIe switch 202 receives, for example, a packet on the upstream port, the switch fabric puts the packet into a buffer, and uses the destination in the packet header to determine on which downstream port the packet has to be forwarded to.

100441 The SoC 200 implies to one or more requirements. The one or more requirements may be, hut not limited to SoCs with internal GPUs supporting the main video channels with onboard video ports and the use of attached or integrated High Speed Video Link (HSVL) SerDes devices interfacing high bandwidth video devices directly with the GPU, support for SoC to SoC or SoC interface and SoC to shared compute Accelerator Devices, support for PCIe attached storage (NVMe) and modern devices (LTE, Wi-H, WiGig), and support for devices attached via High Speed Data Link (HSDL) e.g. ECUs, storage, modem, etc. 10045] Figure 3A shows an architecture of a PCIe HSDL-IC 300, in accordance with some embodiments of the present disclosure. The PCIe FISDL-IC 300 comprises a PCIe-to-HSDL Bridge (PCIe Switch) 301, a PCIe port (1ISDL-Terminal) and a FISDL physical Layer (FISDLPHY). The PCIe port may be at least one of a PCIe upstream port and a PCIe downstream port.

The HSDL-PCIe interface 300 is used for establishing communication between a host terminal and one or more device terminals over a High-Speed Data Link (HSDL) cable in a vehicle. The HSDL-PCIe interface 300 may be configured in at least one of the host terminal and the one or more device terminals. The HSDL-PCIe interface 300 is configured to transmit and receive data packets between a module of a first set of modules associated with the host terminal and the at least one device terminal via the HSDL cable, when configured in the host terminal. In an embodiment, the HSDL-PCIe interface 300 is configured to transmit and receive the data packets between the host terminal and a second set of modules associated with the one or more device terminals. The HSDL physical layer facilitates communication between the host terminal and the one or more device terminals over the HSDL cable.

[0046] Figure 3B shows an arrangement indicating the HSDL-PCIe interface configured in the host and device terminal, in accordance with some embodiments of the present disclosure. Illustrated Figure 3B comprises a host terminal 400, a device terminal 401, a HSDL cable 402, a HSDL-PCIe interface 300 configured in the host terminal 400 and the HSDL-PCIe interface configured in the device terminal 401. The PCIe switch 301 configured in the HSDL-PCIe interface of the host terminal 400 and the device terminal 401, comprises one or more ports. The PCIe switch 301 configured in the host terminal 400 comprises at least one upstream port. As illustrated in Figure 3B, the PCIe switch 301 configured in the host terminal 400 comprises an upstream PCIe port. The PCIe switch 301 configured in the device terminal 401 comprises at least one downstream port. As illustrated in Figure 3B, the PCIe switch 301 configured in the device terminal 401 comprises a downstream PCIe port. The host terminal 400 may be connected to any SoC/ ECU/ module via the PCIe interface, e.g. using x4-link as indicated in Figure 3B. The upstream PCIe port configured in the host terminal 400 is configured to transmit and receive data packets between the module of the first set of modules associated with the host terminal and the device terminal 401 via the HSDL cable 402.

[0047] In an embodiment, a single HSDL cable 402 (HSDL channel) can consist of four PCIe lanes bonded together, yielding predictable scaling. For example, a second-gen PC1 Express x4 slot. HSDL serves up 2000 MB/s of throughput. Thus, the use of HSDL cable 402 helps in achieving a high data rate of up to 16 Gb/s up and 16 Gb/s down. At the host terminal 400 a logical PCIe layer is used along with HSDL physical layer (FISDL PHY). The FISDL physical layer of the host terminal 400 is configured to transmit the data packets from the upstream PCIe port over the HSDL cable 402. At the host terminal 400 there may be a conversation chip for converting data from other formats into PCIe-type signal, which is serialized and re-buffered before transmitting over the HSDL cable 402. Further, the HSDL physical layer at the device terminal 401 transmits and receives the data and serves as the basic physical protocol conversion to turn the physical layer data into PCIe packets. Further, the HSDL physical layer of the device terminal 401 routes the PCIe packets to corresponding a downstream port. The PCIe switch 301 present at the device terminal 401 comprises the downstream port. Thereafter, the downstream port is configured to transmit and receive data packets sent and received from the host terminal 400, and route the data packets to the module of the other devices associated with the device terminal 401. The other devices may be a SoC/ ECU/Main Control Unit (MCU)/ Ethernet module, a Universal Serial Bus (USB) module and the like.

[0048] In an embodiment, the entire PCIe protocol data including the sideband channel of the PCIe is transmitted over the HSDL cable 402. The HSDL cable 402 may be a coaxial, a twisted pair or parallel pair cable. The HSDL cable 402 may extend to a length of 15m.

[0049] In an embodiment, the PCIe switch 301 comprises at least a PCIe-to-HSDL bridge facilitating the transport between a PCIe Upstream port and a PCIe Downstream Port via the High Speed Data Link 40/ For support of more than one host or device terminal 400/401, or for support of more than one HSDL PHY 600, and for support of typical PCIe Switch features e.g. blocking/non-blocking Host-to-Host transfers, Access Control Service (ACS), Alternative Routing-ID Interpretation (ARI), Virtualization and Quality of Service (QoS) a PCIe Switch 301 may be required.

[0050] In an embodiment, the PCIe Host or Device Terminal 400/401 comprises at least one lane and is compatible with at least PCIe Gen 1 or later PCIe Generations. If fully implemented the PCIe switch 301 is compatible with PCIe port bifurcation (splitting the PCI Express Bus into smaller buses), and the PCIe switch 301 has flexible assignment of at least one of host temiinal and the device terminal.

[00511 Figure 4 illustrates a centralized head unit, in accordance with some embodiments of the present disclosure. As illustrated in Figure 4, the centralized head unit is configured on a PCIe backplane. The PCIe backplane consists of PCIe slots of variable lane lengths. Different modules may be plugged into the PCIe slots. As illustrated in Figure 4, the centralized head unit comprises main components like Power supply module, an Audio DSP amplifier module, a Main SoC, a car line specific module for sensors and controls and a Solid-State Drive (SSD) integrated on the centralized head unit. Further, the centralized head unit comprises one or more modules like Accelerator optional SoC, CAN module, and Ethenet (GbE) modules, WLAN module, WiFi module, BT/LTE module, and DSRC module were native PCIe component interfaces are utilized to connect modules to the centralized head unit via the PCIe ports present on the PCIe backplane. Further, HSDL-PCIe interfaces 300 are configured as modules and named HSDL module are integrated to the centralized head unit via PCIe ports. The main components may communicate with the one or more modules via the HSDL modules which act as a HSDL-PCIe interface 300. The HSDL module is configured with the properties of the HSDL-PCIe interface 300.

[0052] Figure 5 illustrates a distributed head unit, in accordance with some embodiments of the present disclosure. Consider an instance where few components of the centralized head unit are removed and formed into a separate electronic control unit (ECU) and located in a place away from the head unit. As illustrated in Figure 5 the centralized head unit of Figure 4 is divided into 3 separate units. A first unit indicated as a distributed modular head unit, a second unit and a third unit indicated as remote electronic control unit. For establishing a communication path between the distributed modular head unit and the remote ECU the HSDL module is plugged into the first unit and the remote ECU via the PCIe port present in the PCIe backplane of the first unit and the remote ECU. The distfibuted modular head unit may be considered as the host terminal and each of the remote ECU may be considered as the device terminal. The HSDL module connected to the backplane of the first unit and the remote ECU take the PCIe protocol data packets in the backplane and extends it over the HSDL cable into the HSDL modules plugged into the PCIe backplane of the remote ECUs. Initially in the backplane copper wires carried the signals. Instead by using the HSDL module with the PCIe port and the HSDL physical layer, the signals may be transmitted over the HSDL cable to the remote ECUs.

[0053] Figure 6 illustrates a HSDL T-Bridge 600, in accordance with some

embodiments of the present disclosure.

[0054] The HSDL T-Bridge 600 comprises the PCIe switch 301 comprising one or more ports, wherein the PCIe switch 301 configured in the host terminal comprises at least one upstream port and at least one downstream port. The at least one upstream port is configured to transmit and receive data packets to and from a module of a first set of modules associated with the host terminal 400 and the at least one device terminal 401 via the HSDL cable 402, and the at least one downstream port is configured to transmit and receive data packets to and from the host terminal 400 and to route the data packets to a module of a second set of modules associated with the at least one device terminal 402. The HSDL T-Bridge 600 comprises a plurality of link ports for facilitating communication between the host terminal and the at least one device terminal over the HSDL cable, wherein one of the plurality of link ports connected to the host terminal 400 is configured to transmit and receive the data packets to and from the upstream port of the host leiminal 400 over the HSDL cable, and another link port of the plurality of link ports connected to the device terminal 401 is configured to route the data packets to a corresponding downstream port of the at least one device terminal 401, for establishing communication between the host terminal and the device terminal.

[00551 The method and system as disclosed in the present disclosure transfers data packets over long distance cables present between the host and the device at a high data-rate and reliability [0056] The described operations may be implemented as a method, system or article of manufacture using standard programming and/or engineering techniques to produce software, firmware, hardware, or any combination thereof The described operations may be implemented as code maintained in a -non-transitory computer readable medium", where a processor may read and execute the code from the computer readable medium. The processor is at least one of a microprocessor and a processor capable of processing and executing the queries. A non-transitory computer readable medium may comprise media such as magnetic storage medium (e.g., hard disk drives, floppy disks, tape, etc.), optical storage (CD-ROMs. DVDs, optical disks, etc.), volatile and nonvolatile memory devices (e.g.. EEPROM s, ROMs, PROMs, RAMs, DRAMs, SRAMs, Flash Memory, firmware, programmable logic, etc.), etc. Further, non-transitory computer-readable media comprise all computer-readable media except for a transitory. The code implementing the described operations may further be implemented in hardware logic (e.g., an integrated circuit chip, Programmable Gate Array (PGA), Application Specific Integrated Circuit (AS IC), etc.).

[0057] Still further, the code implementing the described operations may be implemented in "transmission signals'', where transmission signals may propagate through space or through a transmission media, such as an optical fiber, copper wire, etc. The transmission signals in which the code or logic is encoded may further comprise a wireless signal, satellite transmission, radio waves, infrared signals, Bluetooth, etc. The transmission signals in which the code or logic is encoded is capable of being transmitted by a transmitting station and received by a receiving station, where the code or logic encoded in the transmission signal may be decoded and stored in hardware or a non-transitory computer readable medium at the receiving and transmitting stations or devices. An "article of manufacture" comprises non-transitory computer readable medium, hardware logic, and/or transmission signals in which code may be implemented. A device in which the code implementing the described embodiments of operations is encoded may comprise a computer readable medium or hardware logic. Of course, those skilled in the art will recognize that many modifications may be made to this configuration without departing from the scope of the invention, and that the article of manufacture may comprise suitable information bearing medium known in the art.

[0058] The terms "an embodiment" "embodiment", "embodiments", "the embodiment", "the embodiments", "one or more embodiments", "some embodiments", and "one embodiment" mean one or more (but not all) embodiments of the invention(s)" unless expressly specified otherwise.

[0059] The terms "including". "comprising", "having" and variations thereof mean "including but not limited to", unless expressly specified otherwise.

[0060] The enumerated listing of items does not imply that any or all of the items are mutually exclusive, unless expressly specified otherwise.

[0061] The terms "a", "an" and "the" mean one or more", unless expressly specified otherwise. A description of an embodiment with several components in communication with each other does not imply that all such components are required. On the contrary a variety of optional components are described to illustrate the wide variety of possible embodiments of the invention.

[0062] When a single device or article is described herein, it will be readily apparent that more than one device/article (whether or not they cooperate) may be used in place of a single device/article. Similarly, where more than one device or article is described herein (whether or not they cooperate), it will be readily apparent that a single device/article may be used in place of the more than one device or article or a different number of devices/articles may be used instead of the shown number of devices or programs. The functionality and/or the features of a device may be alternatively embodied by one or more other devices which are not explicitly described as having such functionality/features. Thus, other embodiments of the invention need not include the device itself.

[0063] Finally, the language used in the specification has been principally selected for readability and instructional purposes, and it may not have been selected to delineate or circumscribe the inventive subject matter. It is therefore intended that the scope of the invention be limited not by this detailed description, but rather by any claims that issue on an application based here on. Accordingly, the disclosure of the embodiments of the invention is intended to he illustrative, but not limiting, of the scope of the invention, which is set forth in the following claims.

[0064] While various aspects and embodiments have been disclosed herein, other aspects and embodiments will be apparent to those skilled in the art. The various aspects and embodiments disclosed herein are for purposes of illustration and are not intended to be limiting, with the true scope and spirit being indicated by the following claims.

REFERRAL NUMERALS:

Reference number Description

Environment 101 Plurality of nodes/ ECUs 102 Gateway/ MCU 103 Intrusion detection system

104 Distributed field bus

SoC/Host 201 Root complex 400 Host terminal 401 Device terminal 402 HSDL Cable Channel 600 HSDL-T Bridge

Claims (8)

1. [0065] Claims: We claim: 1. An interface for establishing communication between a host terminal and one or more host or device terminals over a High-Speed Data Link (HSDL) cable channel in a vehicle, wherein the interface is configured in at least one of the host terminal and the one or more device terminals, wherein upon being configured in the host terminal the interface is configured to: Transport data packets between a module of a first set of modules associated with the host telininal and the one or more device terminal via the HSDL cable channel; and wherein upon being configured in the each of the one or more device terminals the interface is con figured to: Transport the data packets to and from the host terminal and route the data packets to and from a module of a second set of modules associated with the one or more device terminals.
2. 2. The interface as claimed in claim 1, wherein the interface comprises: a Peripheral Component Interconnect Express (PCIe) bridge or switch comprising one or more ports, wherein a PCIe bridge or switch is configured in the host. terminal and comprises at least one upstream port and a PCIe bridge or switch is configured in the each of the one or more device terminals and comprises at least one downstream port, wherein the at least one upstream port is configured to transmit and receive data packets to and from the module of the first set of modules associated with the host terminal and configure the data packets for transmitting to or receiving from the at least one device terminal via the HSDL cable channel, and wherein the at least one downstream port is configured to transmit and receive data packets to and from the host terminal and to route the data packets to the module of the second set of modules associated with the one or more device terminals; and an HSDL physical layer for facilitating communication between the host let tinal and the one or more device terminals over the HSDL cable channel, wherein the HSDL physical layer of the host terminal is configured to transmit or receive the data packets to or from the upstream port over the HS DL cable channel and the HS DL physical layer of the at least one device terminal and routes the data packets to and from the corresponding downstream port, for establishing communication between the host terminal and the at least one device terminal.
3. 3. The interface as claimed in claim 1, wherein the data packets transmitted in the HSDLPCIe Interface at the one or more host or device terminals comply with PCTe protocol, wherein the cable channel is comprised of a durable cable assembly with connectors attached on both ends, and with mating connectors fitted at cable ports connected to EISDL-PHY ports, wherein the cable channel provides an impedance matched transmission line with insertion and return loss supporting link margin for HSDL bandwidth, signal modulation and encoding, wherein the cable channel uses a single cable channel to support symmetric channels with one link or a replication of cable assemblies and connector interfaces to support asymmetric HSDL-PHY ports or multiple HSDL-PHY lanes of symmetric or asymmetric channels with one link
4. 4. The interface as claimed in claim 1, wherein the first set of modules, the host terminal, the second set of modules and the one or more device terminals or host terminals are configured as respective upstream or downstream ports of a PCIe Fabric.
5. 5. The interface as claimed in claim 1, wherein the interface is configured as an HSDL bridge comprising a plurality of link ports and at least one port configurable as at least one of an upstream port and a downstream port.
6. 6. A High-Speed Data Link (HSDL) -Peripheral Component Interconnect Express (PCIe) interface for establishing communication between a host teiminal and one or more device terminals or host terminals over a High-Speed Data Link (HSDL) cable channel in a vehicle, wherein the HSDL-PCIe interface is configured in each of the host and the one or more device terminals, the interface comprising: a PCIe bridge or switch comprising one or more ports, wherein the PCIe bridge or switch is configured in a host terminal and comprises at least one upstream port and the PCIe bridge or switch is configured in each of the one or more device terminals and comprises at least one downstream port, wherein the at least one upstream port is configured to transmit or receive data packets between a module of a first set of modules associated with the host terminal and configures the data packets for transmitting and receiving between the at least one device terminal via the HSDL cable channel and wherein the at least one downstream port is configured to transmit and receive data packets between the host terminal and to route the data packets to a module of a second set of modules associated with the device terminal; and an HSDL physical layer for facilitating communication between the host temtinal and the one or more device terminals or a second host terminal over the HSDL cable channel, wherein the HSDL physical layer of the host terminal is configured to transmit and receive the data packets between the upstream port over the HSDL cable channel and the HSDL physical layer of the one or more device terminals and transports and routes the data packets to a corresponding downstream port, for establishing communication between the host terminal and the one or more device terminals or a second host terminal.
7. 7. The HSDL-PCIe interface as claimed in claim 6, wherein a PCIe Host or Device Terminal comprises at least one lane and is compatible with at least one of PCIe Gen 1. PCIe Gen2. PCIe Gen3. or a later PCIe generations, wherein the PCIe bridge or switch is compatible with PCIe port bifurcation, splitting the PCI Express Bus into smaller buses, wherein the PCIe bridge or switch has flexible assignment of at least one of a host terminal and a device terminal, wherein the PCIe bridge or switch has support for Host-to-Host transfer (blocking/non-blocking), wherein the PCIe bride or switch supports Access Control Service (ACS) and Alternative Routing-ID Interpretation (ARI) for Virtualization and wherein the PCIe bridge or switch provides Quality of Service (QoS).
8. 8. The HSDL-PCIe interface as claimed in claim 6, wherein the HSDL-PCIe interface utilize physical layer technology with transmitter and receiver interfaces (H SD L-PHY) capable of transmitting and receiving the aggregate of the signals present at the HSDL Terminal over a twisted pair, a parallel pair or a coaxial cable with link margin and bit-error rate sustaining system fidelity with low retry counts, wherein the HSDL-PCIe interface further utilizes packet framing and routing techniques along with encoding, multiplexing, serialization and/or signal modulation to allow for a secure and maintainable point-to-point link, wherein based on the HSDL-PHY design and cable loss limitations, the point-to-point link utilizes symmetric or asymmetric channels with complementary symmetric or asymmetric HSDL-PHYs on each end of the cable channel.