GB2497605A - Audio interface circuitry - Google Patents

Abstract

Audio interface circuitry is disclosed for the transfer, receiving and transmitting of audio signals. Said circuitry is operable in an analogue mode for receiving analogue audio signals, and in a digital mode for receiving digital audio signals. In the digital mode, the digital audio signals comprise a series of data pulses wherein the length of each pulse encodes at least two audio digital data streams, and wherein the interface circuitry decodes at least one of said digital data streams. Also disclosed is audio apparatus, audio processing circuits, methods of receiving audio signals and audio codec comprising the aforementioned interface circuitry. The circuitry finds use in the connection of devices such as mobile phones, mobile computers and similar media devices with peripheral devices such as headphones or headsets. The interface allows the use of such peripheral devices with devices that use analogue and/or digital signal formats.

Description

Data Interface This application relates to methods and apparatus for providing a data interface, especially for communication of audio data, that is suitable for use for two or more types of data communication, in particular to analogue data transfer and digital data transfer. The application is particularly applicable to interfaces for connectors of accessory devices, such as audio headsets, that can be connected to various different equipments.

In many electronic devices, especially portable devices such as mobile telephones or mobile computing or media devices, the device is designed to be used with various peripheral or accessory apparatus. For example a device such as a mobile telephone may be operable with a set of headphones and thus such a device will have a connector, usually a suitable socket, for connecting to a plug associated with the set of headphones and via which audio data may be transferred. The audio data may include at least two channels of audio, for instance left and right audio channels for stereo.

Typically such audio data is transferred from the device as left channel and right channel analogue audio signals for driving the speakers. The headset may therefore have a three pin connector, for example the common 3.5mm TRS jack plug. Two of the pins are arranged to receive left and right analogue audio channels respectively, and the third pin is a ground pin. Some headsets may also comprise a microphone, for instance for voice communication, and such headsets may typically have a four pin connector, such as a 3.5mm TRRS jack, with the additional pin being for communicating an analogue microphone signal. Often such headsets may not have their own source of power and thus the analogue audio signals received are used to drive the loudspeakers directly and the microphone may be an unpowered microphone.

This analogue audio-out connection can also be used to connect the device to other audio accessory or peripheral devices and may drive a line-level output when required.

Figure 1 shows a typically arrangement where a device 101 may be provided with an audio processing unit such as an audio codec 102 which may or may not include Digital Signal Processing (DSP) circuitry. The device may have an interface 103 comprising a socket 104 for connecting an accessory audio device 105 such as a headset. In this example the headset comprises loudspeakers 106 for left and right stereo audio playback and a microphone 107 for voice communication. The headset thus has a jack plug 108, i.e. connector, for connecting to the device 101 and in this example the jack plug 108 is a four pin TRRS type jack. The tip and first ring of the plug are typically for receiving the two audio channels, the second ring may be used for the microphone signal from microphone 107 in this example and the sleeve may be used for a common ground. The socket 104 of the device has connections in the same arrangement. Some devices may however use different configurations, for instance the microphone and ground connections may be swapped.

The headset may not have its own power source and so the socket 104 supplies analogue driving signals for the audio that can be passed directly to loudspeakers 106 to generate the required audio and receives the signal generated by unpowered microphone 107.

However, especially for devices with RE transmission capability such as a mobile telephone or computing device, analogue audio signals are liable to be corrupted by electromagnetic interference (EMI) and coupling from other nearby circuitry. It has therefore been proposed to transmit audio signals from the device to a peripheral or accessory in a digital format.

Various formats for outputting digital audio data have been proposed, such as optical outputs, USB connections and the like. In some devices therefore there may be a digital audio-out connection in addition to the headphone/auxiliary analogue audio-out connection. However, especially for portable devices it may be wished to minimise the number of connectors for reasons of both cost and space. Thus ideally only one connector for a set of headphones would be desirable. Ideally therefore this connector would be suitable for allowing communication with a peripheral or accessory apparatus using digital audio signals.

Typically however a device manufacturer may want the device to be useable with a number of existing legacy accessory apparatuses, for instance analogue headsets, and thus ideally such a connector may desirably have an accepted form factor and be operable to communicate using analogue signals.

Consequently there is a desire for an audio interface that can enable a device to communicate audio data with a peripheral device, such as a headset, using either analogue or digital formats.

Likewise a user may want to use the same peripheral device with a number of different electronic devices. Thus for example a user may want to use the same headset with a mobile phone handset, which may be able to communicate using digital data, and with an older music player which uses conventional analogue audio communication with external devices.

Thus there is also a desire for an interface for a peripheral device than can operate using either analogue or digital signal formats.

Thus according to the present invention there is provided audio interface circuitry for transfer of audio signals wherein said interlace circuitry is operable in: an analogue mode for receiving analogue audio signals; and a digital mode for receiving digital audio signals wherein, in said digital mode, said digital audio signals comprise a series of data pulses wherein the length of each pulse encodes at least two audio digital data streams, and wherein the interface circuitry decodes at least one of said digital data streams.

In a further aspect of the invention there is provided a method of receiving audio signals comprising: receiving said audio signals at an interface operable in analogue mode and also in digital mode and selecting a mode to operate in, wherein: in said analogue mode at least one analogue audio signal is received and forwarded for an audio output transducer; and in said digital mode at least one digital audio signal is received, said digital audio signal comprising a series of data pulses wherein the length of each pulse encodes at least two audio data streams, and the interface circuitry decodes at least one of said data streams and forwards said digital data stream for an audio output transducer.

In a further aspect of the invention there is provided audio interface circuitry for receiving audio signals wherein said interface circuitry is operable: in an analogue mode to receive analogue audio signals; and in a digital mode to receive digital audio signals wherein, in said digital mode, the audio data comprises a series of data pulses at a pulse rate wherein the length of each pulse encodes at least two audio data streams.

A further aspect provides audio interface circuitry for transmitting audio signals to an apparatus external to a host device wherein said interface circuitry is operable: in an analogue mode to transmit analogue audio signals; and in a digital mode to transmit digital audio signals wherein, in said digital mode, the audio data comprises a series of data pulses at a pulse rate wherein the length of each pulse encodes at least two audio data streams.

Embodiment of the invention also provide a headset for receiving audio signals comprising at least one audio output transducer and a connector for connecting to an audio device wherein the headset is operable in a digital mode for receiving digital audio signals via said connector and applying said digital audio signals to said at least one audio output transducer and an analogue mode for receiving analogue audio signals via said connector and applying said received analogue audio signals said at least one audio output transducer.

In a further aspect there is provided an audio apparatus comprising: at least first and second audio output transducers; a connector for connecting the audio apparatus to another device having at least first and second contacts; interface circuitry operable: in a first mode to enable first and second analogue signal paths from the first and second contacts directly to the first and second audio output transducers respectively; and in a second mode to disable said first and second analogue signal paths and provide at least a first digital signal path trom the first contact to a digital decoder.

The invention will now be described, by way of example only, with reference to the following drawings, of which: Figure 1 shows a conventional connection for a headset to an electronic device; Figure 2 illustrates a digital data transmission that may be used in embodiments of the present invention; Figure 3 illustrates example data waveforms on the various signal lines illustrated in Figure 2; Figure 4 illustrates a headset connected to a device with digital data transfer; Figure 5 illustrates a connection interface for an accessory according to an embodiment of the invention; Figure 6 illustrates an embodiment of data extraction circuitry suitable for use in the interface of figures; Figure 7 illustrates the data waveforms on the various signal lines of the data extraction interface shown in Figure 6; Figure 8 illustrates a pulse-length-modulator suitable for use in the interface of figure 5; Figure 9 illustrates the data waveforms on the various signal lines of the pulse-length-modulator of figure 8; Figure 10 illustrates a connection interface for an accessory according to another embodiment of the invention; and Figure 11 illustrates a connection interface for a device according to an embodiment of the invention.

As illustrated in figure 1 device may be arranged with connections to accessory apparatus such as headsets which communicate by sending and receiving analogue audio signals. Embodiments of the present invention are capable of using digital audio signals such that an accessory such as a headset receives digital data from the device and, if necessary, can provide digital data to the device.

One conventional format for transmission of stereo audio digital data is to transmit signal data for both L/R audio channels on one wire in serial format, for example in words of 24 bits, with separate words being sent for the left (L) data channel and the right (R) data channel. A bit clock signal (BCLK) is sent on another wire and a further clock at the left/right words rate (LRCLK) sent on a further wire. It will be clear however that this requires three wires for communicating the audio data and thus the connectors used to connect the devices must have at least three separate contacts or pins. For simultaneous bi-directional communication more wires and thus more pins will be required. Note that as used in this specification the term pin will be used to refer to any separate contact on a connector, such as a jack pin or socket, whatever the shape or form of the contact. Thus, for example on a standard TRS jack the tip contact will be a first pin, the ring contact a second pin and the sleeve contact a third pin. By separate contact is meant a contact on a connector which couples to a given distinct signal path.

The term connector shall mean any apparatus used to make a connection between apparatus which is suitable for signal communications and, for the avoidance of doubt includes male connectors, such as plugs, and female connectors, such as sockets, or connectors which have both male and female portions In addition to the pins discussed above for data transfer one pin will typically always be required for ground. Further as a headset device may typically not have its own power source and processing of digital data requires power it may be necessary to provide power on another pin.

In an alternative format for digital transmission the audio data may be transmitted as a high-rate 1-bit stream, sometimes referred to as Pulse Density Modulation (PDM).

Word-length reduction, noise shaping and/or delta-sigma techniques may be applied to reduce quantisation noise in the audio band at the expense of noise higher frequencies to reduce the required bit rate. However, this still requires two wires, one for the data and one for the clock. Stereo data may be transmitted along one wire, typically alternating between sending left channel data and right channel data, but the separate clock line is still needed. Again for simultaneous data transfer in both directions more than two data wires would be needed, together with ground and power as described above.

Thus for conventional digital transmission formats a digital-out connector for an accessory such as a headset would need to be separate to any conventional connector for analogue out signals as different numbers of wires would be required.

Embodiments of the present invention therefore use a digital data format that allows multiple channels of data to be transmitted over a single wile without the need for any separate transmission of any clock signal or any other signal necessary for the data encoding/decoding.

Figure 2 illustrates an embodiment of a data transfer system for transferring multiple simultaneous channels of data over a single link. In this example stereo audio data is transferred over a single wire, i.e. conductive path 211, between a first component 201 and a second component 202. The first component 201 and second component 202 may be located in a host device and accessory apparatus respectively. In this case the link 211 may comprise a conductive path involving a suitable connection (not shown) such as a plug and socket.

The audio interface circuitry of the first component 201 has a pulse-length-modulator (PLM) 203 which receives audio input data, PDM-R and PDM-L, for both the left and right audio channels. In this example the L/R input data are separate 1-bit (i.e. PDM) digital input audio data streams for each channel, i.e. left channel and right channel. At regular intervals, for instance in each period of a first clock signal OK (which preferably matches the sample rate of the L/R 1-bit audio data input) the PLM generates a data pulse with a length that depends on the logical combination of [JR input audio data.

For left and right 1-bit audio data inputs there are four possible combinations of input data and the PLM 203 generates a data pulse having a length (i.e. duration) which varies according to the output of the particular LIR input data combination, as illustrated

in table 1 below.

PDM-L Value PDR-R Value PDM Combined Pulse length (TFCK) value o o 00 1 0 1 01 2 1 0 10 3 1 1 11 4

Table 1

The pulse length is preferably determined as a multiple of a clock period of a second clock signal, ECK, which has a frequency which is a multiple of the first clock signal OK. It will be clear that the frequency of the second clock signal FCK should be at least four times the frequency of the first clock signal CK and is preferably at least five times the frequency of the first clock signal to allow for a pulse length of 4TFCK within each period of the first clock signal and also allow a gap between pulses to ease downstream clock recovery.

Figure 3 illustrates the first clock signal CK and second clock signal ECK, which in this example has a frequency five times that of the first clock signal CK. Figure 3 also illustrates that in each period of the first clock signal OK the right and left input data streams PDM-L and PDM-R will each have a data value of 1 or 0 depending on their respective current data i.e. logic levels. The resulting PLM data signal (MPDM), generated to represent a logical combination of L/R input audio data as per table 1, is also illustrated. This comprises a series of data pulses, at the frequency of the first clock signal CK, where the length of each individual data pulse encodes a data value for the left audio channel and also a data value for the right audio channel.

It will be noted that there is always one data pulse per period of the first clock signal CK and that the data pulses are arranged so that there is always a gap between data pulses. This means that the PLM data signal, MPDM, can itself be used to recover the first clock signal CK by the receiving interface circuitry. In the example shown, the rising edges of the clock signal are separated by the clock period but the skilled person will appreciate that the falling edges could instead be synchronised to the first clock signal CK.

Referring back to Figure 2 the output from the PLM 203 is transmitted as data signal MPDM to the second component 202. The audio interface circuitry of the second component 202 has an interface 205 for receiving the data which comprises a data extraction module 205. The data extraction module 205 extracts the first clock signal from the data signal. As mentioned above the period between the rising (or alternatively the falling) edge of each data pulse indicates the first clock period. The data extraction module 205 then determines the length of each data pulse and uses this to determine the audio data for the left and right audio channels based on the correspondence between pulse length and data channels values set out in table 1.

The data extraction module therefore outputs a version of the first clock signal OK and a 1-bit data (PDM) signal for each relevant audio channel. The data extraction modules thus decodes the data which is encoded in the PLM data pulse and conditions the digital data streams into the desired type of digital signal. These signals can be passed to respective DAC-amplifiers 207, 208 to drive respective loudspeakers 209 and 210.

Thus the PLM 203 acts as a PLM encoder for encoding received data streams into a PLM signal and data extraction circuitry 205 acts as a PLM decoder for decoding the PLM signal to recover the original data as required.

Figure 2 shows a single data extraction module 205 that extracts the data for both stereo channels. In an alternative arrangement there could be a separate data extraction module associated with each relevant DAC-amplifier 207, 208 and speaker 209, 210 for each channel. In an accessory apparatus having internal stereo speakers the speakers may typically be separated and arranged to receive signals from an audio source such as an audio codec and thus separate data extraction modules for each speaker may be preferred. In this case the data extraction module for each channel may be integrated with the respective DAC-amplifier 207, 208 for that channel. In other embodiments however the arrangement of Figure 2 is preferred.

Figure 3 illustrates that the data signals PDM-RX and PDM-LX, extracted by data extraction module 205, are the same as the respective input data PDM-R and PDM-L.

This embodiment of the present invention therefore supplies simultaneous audio data for multiple audio channels using only a single communication link, i.e. a single data wire, without requiring any clock signals to be sent.

This means that a single wire can be used for communication of digital audio data from the device to the accessory and a separate wire can be used for simultaneous, i.e. full duplex, transmission of digital data from the accessory to the device.

In one embodiment therefore standard connectors such a four pin TRRS jack can be used for the digital data transfer.

Figure 4 illustrates a two way data exchange between a DSP or audio codec 401 of a first device 402, such as a personal media player, gaming device or mobile telephone, to a headset 403 via interface circuitry 404. In this embodiment there is two way digital data exchange (MFDM_UP and MPDM_DOWN) which uses the digital data transfer as described above in relation to figures 2 and 3. The headset may have interface module 405 which receives the MPDM_UP data signal, as well as separate power and ground links, and which transmits the MPDM_DOWN signal. The device 402 may therefore connect to the headset 403 via a 4-pin connector jack plug 406.

The interface module 405 of the headset may receive the PLM signal (MPDM_UP) and extract left and right audio data for loudspeakers 407 and 407 and send the appropriate PDM data to each loudspeaker as described previously. Alternatively the interface circuitry could transfer the signal to data extraction circuitry associated with each loudspeaker 407, 408.

In this way left and right audio data is transferred from the device 402 to the headset 403, along with a common ground and power for the headset device using only three pins of a connector. For devices which just provide stereo audio a three pin connector In the example shown in Figure 4 however the headset has a microphone 413 for receiving voice communication from the user. This voice data may be transmitted to the DSP/Codec 401 of device 402 using a separate wire for a device having a four pin connector. Thus full duplex communication is enabled.

If there were voice data only this could be transferred as an analogue signal however digital communication may be preferred. Thus the microphone output may be digital, or an analogue output converted to digital by a suitable DAC, and transferred to the interface as, for example, a PDM data stream. The interface 405 may then forward this data to the device 402. A PLM signal encoding the one channel of voice data may be generated and transferred.

In some accessory devices however there may be a need to transfer additional data streams from the headset to the device. In the example shown in figure 4 there are microphones 409 and 410 associated with loudspeakers 407 and 408 for noise cancellation. The microphones may be outward facing for a feedforward type noise cancellation and/or there may be inward facing microphones for a feedback or each loudspeaker may have a plurality of microphones to form a combined feedback/feedforward system.

In some headsets the noise cancellation may be performed within the headset but this can add to the cost and complexity of the headset. Thus for some headsets the signals from the noise cancellation microphones may be transmitted to the DSP/codec 401 of device 402 to perform appropriate noise cancellation for the audio signals transmitted to the headset.

The signals from microphones 409 and 410 may therefore be sent to interface 405 of the headset, for example as 1 bit FDM streams. The data from the microphone 407 and 408 may then be combined with any voice data from microphone 413 and transmitted as a PLM digital signal (MPDM_DOWN) as described above.

Thus a single wire is used for communication of multiple audio channels from the headset 403 to the device 402.

Figure 5 shows an embodiment of a suitable interface module that allows accessory apparatus to use standard connectors for digital data transfer and also to function with legacy devices outputting, and possibly receiving, analogue audio signals.

Figure 5 shows a jack plug connector 501 which, in this embodiment has four pins or contacts, 501a-d, such as a TRRS type plug.

One pin, 501d, of jack 501 provides a ground connection and is connected to an appropriate ground path of the accessory apparatus. The other three pins 501a-c are connected, via signal paths HP LEFT, HP RIGHT and MIC to series switches 502a-c respectively which connect to loudspeakers 503 and 504 and microphone 505 respectively.

Series switches 502a-c can thus connect the pins 501 a-c of the jack 501 directly to the transducers 503, 504 and 505. Thus in a legacy mode of operation where analogue audio signals are used, the series switches 502a and 502b can connect pins 501a and 501 b of the jack directly to the left and right loudspeakers 503 and 504 respectively so that the received analogues audio signals can drive the loudspeakers. The microphone may be resistively biased through the MIC line and, in use, superimposes a small signal modulation that is transmitted via pin SOlcto the device to which the accessory is connected enabling read-out of the microphone data. The microphone ground reference and speaker coil ground current return use the ground connection provided by pin SOld.

In some embodiments the accessory may not have its own source of power. The series switches 502a-c are therefore configured to default to providing a connection between the analogue signal paths and the transducers. Suitable switches include normally-closed relays or depletion mode FETs with gates grounded for example via a resistor.

In addition the three pins 501a-c are also connected to paths DATA_UP, DATADOWN and PWRt0 digital processing circuitry 506. The paths from pins 501a and 501b, which carry the analogue driving signal for the loudspeakers in legacy mode, default to high impedance.

In a digital mode of operation pin 501 c is used to supply power to the headset. When power is available on the PWR/Mic line the digital processing circuitry 506 may operate to switch the series switches 502a-c to disconnect the signal lines HP LEFT, HP RIGHT and MIC from the jack pins and to connect the transducers to the DAC5 507 and 508 and ADO 509.

The digital processing circuitry comprises a discrimination or identification circuit 510 which determines whether the device is capable of using the appropriate digital protocol.

There are a number of ways in which the discrimination circuit can operate. For instance a device could be arranged, on detection of insertion of a jack into a socket (either during operation or on device start-up/wake-up/reset etc.) to provide power via pin 501c and attempt a brief digital handshaking sequence with the connected accessory, for example by transmitting a first data sequence to the accessory via pin 501a and monitoring for a second data sequence (which may be the same or different to the first data sequence) received via pin 501 b. On receiving power the digital processing circuitry of the accessory may transmit the second data sequence to the device, possibly in response to receipt of the first data sequence. If the handshaking is successful the device and accessory will then transmit and receive digital data. If the handshaking is not successful both device and accessory may revert to legacy mode using analogue communications. For example if the accessory is connected to a device in which pin5Olc appears to provide suitable power but the device does transmit the first data sequence the accessory may continue to operate in legacy mode. Other types of discrimination circuitry may be used however. For example the signals received via any of the pins 501 a-c may be analysed when suitable power is available via pin 501 c to determine whether the characteristics match those of the expected digital signals or analogue signals or to look for particular modulations which may be embedded in the signals.

Assuming that the discrimination circuitry 510 determines that the device is capable of using the appropriate digital protocol a control signal may be generated to control the switches 501a-c as described above. It will be appreciated that the switches 501 a-c may comprise more than one switch element for disconnecting the transducers from signal lines HP LEFT, HP RIGHT and MIC and connecting them to the DACs 507 and 508 and ADO 509.

PLM processing circuitry 511 will also be enabled and data lines DATA_IP and/or DATA_DOWN may be switched out of high impedance mode as required. Power received via line PWR may also be distributed to other components within the accessory that require power in digital mode.

In digital mode data may be received via pin 501a and supplied to the PLM circuitry 511. Data extraction circuitry, i.e. a PLM decoder, can extract the left and right audio data streams as described previously. The relevant signals can then be supplied to DAOs 507 and 508 associated with loudspeakers 503 and 504 respectively, for example as 1 bit PDM signals, to generate the analogue driving signals for the speakers.

Signals received from microphone 505 will be converted to digital by ADC 509, for instance a 1 bit PDM data stream and passed to PLM processing circuitry. As described previously if there is only one channel of audio data to be transmitted to the device then a PLM signal encoding only one 1-bit PDM data channel may be transmitted.

However the accessory may have one or more additional microphones 512 and 513 for noise cancellation. In legacy mode these microphones may not be operational and no noise cancelling is applied. However in digital mode these microphones may be operational and he signals from the microphones may be digitised and received by the PLM circuitry 511. The PLM circuitry may therefore generate a pulse-length-modulated signal encoding all audio data channels to be transmitted to the device as an MPDM_DOWN signal via path DATA_DOWN and pin 501b.

It will therefore be seen that the interface embodiment shown in Figure 5 is able to operate in both an analogue legacy mode with devices that communicate using analogue signals and also in a digital mode with devices able to communicate using digital signals. The interface can use a standard connector suitable for legacy devices.

In digital mode additional functionality may be enabled due to the increased possibility of communication. In the event that the accessory is plugged into a device unable to support digital communications it will default to legacy mode operation.

The embodiment described above with relation to Figure 5 relates to an accessory which, in legacy mode, receives two audio data streams and provides a voice microphone data stream, each via separate pins of a four pin connector (the fourth pin being ground). Some legacy devices may however use a three pin connection, for example a music player may be provided with a three pin socket, i.e. a socket with three separate contacts, for providing left and right audio data and ground.

Embodiments of the invention could therefore be implemented with a three pin connector, for example with one pin used for receiving digital PLM data, one pin for receiving power and the third pin for ground.

In some embodiments however the interface circuitry may be arranged to derive power by using the received data signal to provide power through various known power harvesting techniques. In one known technique the received data signal line, which will swap between a high voltage level and a low voltage level according to the data, may be connected via a suitable diode to a capacitor. In use when the voltage level is high and the capacitor is relatively uncharged the diode will forward bias and charge the capacitor which can then be used to supply power for the PLM processing circuitry.

This will result in a voltage drop on the signal line but the sending device may be configured to use high and low voltage signal levels which are suitable for providing power and also for ensuring good signal quality. Other power harvesting techniques are known and could be used as appropriate. A PLM signal is particularly suitable for use in such power harvesting techniques as there is a data pulse, and hence high voltage, every clock period.

The use of power harvesting in this way could reduce the number of pins required and/or allow additional functionality for a given number of pins. For instance a headset could be provided with a three pin connector. In legacy mode the three pins may be used for left audio, right audio and ground. Thus the headset simply receives audio data. In digital mode however one pin may be used for receiving a digital data signal and, as described above, power harvesting may be applied to this signal line to provide power for the headset. A second pin could therefore be used to send data from the headset to the device, for instance audio data from ANC microphones or a voice microphone or control data, thus enabling various controls on the headset. The third pin could be ground. Thus an accessory with a three pin connector could be connected to some devices, such as an older music player, to operate in legacy mode and simply receive analogue stereo audio. The same accessory could also be used with a different device however to receive digital stereo audio and also to provide signals for voice data, noise cancellation and/or headset based control -all via a connector with just three contacts.

It will also be appreciated that some devices may use different pins for different functions. For instance with the standard TRRS connector for analogue audio signals there is a convention regarding which pins are used for left and right audio, but some devices use an alternative arrangement for the mic and ground pins compared to other devices.

In some embodiments the interface circuitry may be able to determine which pin-out configuration the connected device is using, e.g. with respect to Mic and ground, and may be able to swap the coupling of pins of the plug 501 to paths of the interface circuitry accordingly. Thus if the accessory were connected in use to a device that used the relevant contact for pin 501 c for ground and the relevant contact for pin 501 d for microphone signals, this could be detected. The coupling between pins 501c and 501d and the respective paths shown in FigureS could then be swapped. Various techniques are known for detecting the pin-out configuration of the device (in terms of use of Mic and Ground pin out configurations), for instance by detecting the resistive biasing applied to the contact which is used for the microphone and various means are known for automatically swapping the coupling to the signals paths, any of which could be applied to embodiments of the present invention.

It will be appreciated that in the embodiment shown in figure 5 one pin (pin 501 b) which is used for receiving analogue signals in the legacy mode is actually used for outputting digital data in the digital mode. It will of course be appreciated that in other embodiments the roles of pins 501a and bin the digital mode could easily be swapped.

The PLM circuitry 511 will thus comprise data extraction circuitry for extracting the relevant audio data from the received PLM signal (DATA_UP). Figure 6 illustrates one embodiment of suitable data extraction circuitry, i.e. a suitable PLM decoder. In this embodiment, the clock signal is recovered using a Delay-Locked-Loop (DLL) comprising a voltage-controlled delay line 601, itself comprising a chain of voltage-controlled delay elements 602. together with a phase-frequency detector (PFD) 603, charge pump 604 and loop filter 605 as known. The DLL receives the PLM signal, e.g. signal MPDM shown in Figure 3, and the PFD 603 is designed suitably so that each rising edge of delay line output SYNC is locked to a rising edge of the incoming PLM stream. Thus the delay along the delay line becomes equal to a period of the original CK clock.

The duty cycle of SYNC will vary with the data carried on the PLM signal, MPDM. To establish a clock with 50% duty cycle, SYNC is applied to the set input S of an edge-triggered RS flip-flop 606, while a signal y5 from half way along the delay line is applied to the reset input.

To extract a measure, PL, of the length of each transmitted PLM data pulse, the data at a number of equally spaced taps of the delay line 601 is summed in a summer 607.

The delay taps are arranged to sample the signal at intervals equal to the second clock frequency FCK and in sufficient number to be able to discriminate between the number of different possible pulse lengths. In this embodiment, where the second clock frequency is known to be five times the frequency of the first clock signal and there are four possible different pulse lengths, there are five delay taps at equal spacings along the delay line.

The determined data pulse length value FL is then applied to a look-up table 608 or equivalent logic to decode the PLM signal (MPDM) into the relevant 1-bit PDM audio data channel or channels. The look-up table is effectively the same as table 1 above.

It will be noted that this detection method does not require explicit recovery of the second clock signal FOK (or any clock signal faster than the fist clock signal). However if this is required, for instance for other circuitry, such a clock may be generated by logical combination of the tapped outputs yl toy9 as known. The recovered first or second clocks may be used for other functions in the device. Indeed the rising (or even both) edges of the unprocessed MPDM signal may be used as a clock edge.

Figure 7 illustrates the PLM input signal, MPDM, that would be received for the various possible data combinations, how the first clock signal CKX can be recovered and how the output of the delay tap y5 can set a 50:50 duty cycle for the clock signal. These waveforms also shows how the outputs of the delay taps yl to y9, when summed, provide an indication of the length of the data pulse which can then be used to extract the PDM-R and PDM-L audio data streams.

In correct operation, the sampled output of the first delay tap yl is always 0 and the sampled output of the last delay tap y9 is always 1. This can be used to generate a flag indicating correct operation i.e. lock of the DLL loop and correctly formatted input data.

In this case it can then be noted that the value of PL only varies due to the contribution of delay taps {y3, y5 and y7}. If the value PL were produced by summing just the output of these three delay taps then the values of PDM-L and/or PDM-R can then be selected merely as the MSB and LSB bits of PL.

The embodiments described above relate to two channels of audio data, e.g. left and right stereo data. Howevei it will be appreciated that the principle can be extended to more channels of audio data, for example foi suiiound sound. For example if there were four channels of audio data, left-front, left-rear, right-front, right-rear and each data channel was a 1-bit PDM data stieam then the combined data would comprise a 4-bit data signal which could be encoded by 16 different pulse lengths.

Referring back to Figure 5 the PLM circuitry may also comprise a pulse-length-modulator for receiving data from one oi more sources, such as the voice microphone and/or noise cancelling microphones and generating a pulse with a pulse length encoding the various data channels. Figure 8 illustrates one example of a suitable pulse-length-modulator (PLM) that may be used as pad of the audio interlace, i.e. a PLM encoder. As illustrated the PLM has a combiner 801 that receives the various input data streams. For ease of explanation only two input data streams, PDM-ML and PDM-MR are illustrated, for instance the 1-bit signals from left and right noise cancellation microphones although the same general principle applies to more than two input data streams. The combiner 801 conveits the input data to a 2-bit combined data stream PDM-C. A counter 802 is also arranged to leceive the first and second clock signals CK and FCK respectively. The second clock signal FCK is arianged to clock the counter to increment and the first clock signal is provided at the reset input. Thus each period of the first clock signal the counter will increment at the rate of the second clock signal. The output is thus is a sawtooth ramp waveform that is reset to zero at the start of each period of the first clock signal (oi alternatively the counter could be arranged to count down from a certain starting level each period).

The output of the combinei 801 and counter 802 is compaied by comparator 803 which is clocked at the second clock frequency FCK, and is configured to give a high output if RAMP is greater than the combined signal PDM-C. At the first relevant (e.g. rising) clock edge of ECK after the countei has reset, the RAMP signal will be zero, and the combined signal will be zeio 01 greater, so the output of the comparatoi goes high at the beginning of the first relevant edge of FCK in each period of the first clock signal. At successive FCK edges, the RAMP signal will have increased: the comparator output goes low when the ramp signal has exceeded the combined data value. This results in a data pulse where the using edge is synchronised to the first clock signal (i.e. the rising edge of each data pulse occurs at the first relevant FCK edge after the rising edge of the CK clock signal) and the pulse length depends on the combined data value. It will of course be appreciated that the comparator could be arranged so that the output goes low at the start of the clock period and goes high only as a result of the comparison to synchronise the falling edges of the data pulses.

Figure 9 illustrates the various data waveforms and shows how the comparison of the combined data value PDM-C with the ramp signal can generate the PLM data signal (MPDM).

Other techniques for pulse length modulation in general, for example using delay-locked loops (DLL) are known and could be adapted for use in embodiments of the invention.

Figure 10 shows another embodiment of an accessory device interface. This embodiment has several of the same components discussed above in relation to Figure 5. In the embodiment of Figure 10 however the signal paths HP LEFT and H P RIGHT includes ADC5 1001 and 1002 respectively for converting the received analogue signals into digital signals. This allows various digital signal processing techniques to be applied within the accessory even when the legacy device transmits analogue signals. There may therefore be a digital signal processor (DSP) 1004 arranged to receive digital signals from the ADCs 1001 and 1002 and possibly noise cancellation microphones 1005 and 1006, for example to perform noise cancellation or spectral equalising to compensate for speaker shortcomings etc. The digital signals can then be converted into analogue signals by DACs 1007 and 1008 associated with the loudspeakers.

Likewise in legacy mode the signals from voice microphone 505 may be digitised in ADC 1009, optionally subject to any digital processing, and then converted back to an analogue signal in DAC 1003 to be transmitted over the Mic line to the connected device.

In digital mode, as described previously, the Mic line may be used to supply power. In this embodiment however the serial switches may be located within the digital domain of the circuit and thus connect the output of the PLM circuitry with the inputs to DACs 1007 and 608 and output of ADC 1009. In some embodiments DSP 1010 may be arranged to process the signals output from and input to the PLM circuitry, possibly in addition to as an alternative to DSP 1004.

This embodiment does require at least some power available in legacy mode however this could be provided by a battery in the accessory which may be recharged, for example when operating in digital mode. In some arrangements, if the power requirements of the digital processing is relatively low, it may be possible to derive the power needed from the audio signals themselves using similar power harvesting techniques to those described above but based on the received analogue signals.

Like the interface embodiment shown in Figures, the embodiment shown in figure 10 is also able to operate in both an analogue legacy mode with devices that communicate using analogue signals and also in a digital mode with devices able to communicate using digital signals, again using a standard connector suitable for legacy devices.

It will be noted that both of the embodiments shown in Figures Sand 10 are operable in a digital mode that uses pulse length modulation to encode one or more streams of digital data. The PLM digital signal may also be used to encode other data streams as well. For instance control data could be encoded into the pulse length to allow the device to provide control instructions for the transducers and/or any DSP of the accessory. Likewise control data such as indicating button presses etc. may be transmitted from the headset to the device in digital mode. Additional data from the accessory device, such as data on the current flowing through a loudspeaker coil may also be measured and transmitted to the device for speaker protection for example.

In some embodiments the accessory may be operable in more than one digital mode of operation. The use of the PLM digital format as described is advantageous due to the fact that high data rates can be achieved with continuous communication in one direction over a single wire without requiring transmission of a bit clock or the like and with good fidelity. However other digital formats could be supported.

For instance, in a second digital mode pins 501 a and 501 b may be used together for differential digital signalling or a 1-bit PDM signal may be received on pin 501a with a bit clock signal being received on pin 501b, again with pin 501c being used for power and pin SOld being used for ground. In both of these modes full duplex communication is not possible but this would be suitable for receiving data only, for instance just for audio playback or two-way half-duplex communication could be established which may be suitable for some applications.

The discrimination circuitry of the digital processing circuitry may thus be configured to not only identify whether digital communication is supported but also the format of digital communication.

The embodiments have been described in relation to transfer of multiple channels of audio data but it will be appreciated that the principles may be applied to other types of data for driving transducers such as haptic transducers! ultrasonic transducers! hearing aid coils and the like.

Figure 11 shows an embodiment of interface circuitry that may be used in an electronic device to communicate with an accessory.

Figure 11 illustrates a device 1101 which includes an interface 1102. for instance a codec, for communicating with an external accessory apparatus when connected via connector 1103, which in this example may be a socket configured to receive a standard connector such as a TRRS jack plug. In this example therefore the connector has four separate pins or contacts which each are coupled to signal lines of the codec 1102.

The interface is capable of operating in a legacy mode for transmitting and receiving analogue signals and also in a digital mode for transmitting and receiving digital signals.

The PLM codec 1102 may include a digital signal processor (DSP) 1104 for communicating with other parts of the host device. For example, the DSP 1104 may be arranged to communicate via a first interface 1105 with a first device component, such as an applications processor 1106 of the host device. The DSP may also communicate via a second interface 1107 with a second device component, such as a wireless codec (e.g. used for wireless and/or RF baseband communications). In some applications the DSP 1104 of codec 1102 may also communicate with further device systems, such as via interface 1109 with a Bluetooth (RTM) codec 1110. Note that as well as providing a communications interface between any of the applications processor 1106, wireless codec 1108 and BT codec 1110 and the attached accessory device, the codec may provide a path for communications between at least two of the device components, preferably a digital only path.

In operation in legacy mode audio data to be transmitted to the accessory device may be received by DSP 1104 as digital data and any necessary processing applied.

Individual left and right audio streams will then be transmitted to digital to analogue converters (DACs) 1111 and 1112 respectively. The output from DACs 1111 and 1112 are then passed, via HP Left and HP Right signal paths respectively, to the relevant pins/contacts of connector 1103, possibly via suitable amplifiers 1113. In legacy mode, signals received on the mic signal path from the relevant pin/contact of connector pass to switch 1114 which will connect to the input to ADC 1115. ADC 1115 will convert any received microphone signals into a suitable digital signal which is then passed to DSP 1104, possibly for communication onward to wireless codec 1108 say.

In digital mode the switch 1114 may be switched to connect the path used for MIC in the legacy mode to a supply voltage VBNDD. Amplifiers 1113 may also be disabled and the DSP 1104 will transmit any data to the be transmitted to PLM module 1116.

PLM module 1116 will encode the data into a PLM data stream to be transmitted to the device on the DATA_UP signal path as described previously. Digital data may also be received from the device on the DATA_DOWN signal path and decoded into appropriate data streams and transmitted to DSP 1104.

Operation in digital or legacy mode may be controlled by discrimination circuitry 1117.

This circuitry may, on detection that an accessory apparatus is connected either during operation or at power-on or reset-determine whether the accessory apparatus is capable of communicating using the relevant digital protocol. For example the device may initially start in digital mode and attempt a handshaking exercise as described previously. If the handshaking is successful the codec 1102 may continue in digital mode. However if the handshaking is not successful then the codec 1102 may revert to legacy mode and make the Data_up and Data_down lines high impedance and generate a control signal to enable amplifiers 1113 and switch 1114 to connect the Mic line toADC 1115.

The codec 1102 is thus capable of communicating with an accessory device that supports PLM digital communications, such as described above in relation to Figures 4 and 5, but also with legacy accessory devices using analogue signals.

Although reference is made herein to "audio signals", the electrical signals that are handled by the "interface" can represent any physical phenomenon. For example, the term "audio signals" can mean not just signals that represent sounds that are audible by the human ear (for example in the frequency range of 20Hz -20kHz), but can also mean input and/or output signals from and/or to haptic transducers (typically at frequencies below 20Hz, or at least below 300Hz) and/or input and/or output signals from and/or to ultrasonic transducers (for example in the frequency range of 20kHz - 300kHz) and/or to infrasonic transducers (typically at frequencies below 20Hz).

Possibly, an "interface" may not receive any audio signals in a range audible by the human ear, for instance an "interface" dedicated in design or in a particular use case may only receive haptic or ultrasonic signals related "audio signals".

It will be appreciated that the interface circuitry may conveniently be implemented, at least partly, as an integrated circuit and may form part of an accessory device, such as a headset, which can be connected to another electronic device, especially a portable device and/or a battery powered device. The term headset includes set of headphones, earphone, earbuds etc. whether or not with microphones for voice communications and/or active noise cancellation. An accessory device may be used with an audio device such as a personal music or video player or a mobile communications device such as mobile telephone or a computing device, such as a laptop or tablet computer or PDA or a gaming device.

It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be able to design many alternative embodiments without departing from the scope of the appended claims. The word "comprising" does not exclude the presence of elements or steps other than those listed in a claim, "a" or "an" does not exclude a plurality, and a single feature or other unit may fulfil the functions of several units recited in the claims. The word "amplify" can also mean "attenuate", i.e. decrease, as well as increase and vice versa and the word "add" can also mean "subtract", i.e. decrease, as well as increase and vice versa. Any reference numerals or labels in the claims shall not be construed so as to limit their scope.

Claims (1)

1. <claim-text>CLAIMS1 Audio interface circuitry for transfer of audio signals wherein said interface circuitry is operable in: an analogue mode for receiving analogue audio signals; and a digital mode for receiving digital audio signals wherein, in said digital mode, said digital audio signals comprise a series of data pulses wherein the length of each pulse encodes at least two audio digital data streams, and wherein the interface circuitry decodes at least one of said digital data streams.</claim-text> <claim-text>2. Audio interface circuitry as claimed in claim 1 wherein the interface circuitry decodes and conditions at least one of said digital data streams.</claim-text> <claim-text>3. Audio interface circuitry as claimed in claim 1 or claim 2 comprising: at least a first analogue signal path for receiving analogue audio data from a first contact on a connector; at least a first digital path for receiving digital audio signals from the first contact on the connector; and at least a first switch for enabling/disabling the first analogue signal path.</claim-text> <claim-text>4. Audio interface circuitry as claimed in claim 3 comprising: a second analogue signal path for transferring analogue audio data to/from a second contact on a connector; a second digital path; a second switch for enabling/disabling the second analogue signal path.</claim-text> <claim-text>5. Audio interface circuitry as claimed in claim 4 wherein the at least first and second switches default to enabling the first and second analogue signal paths.</claim-text> <claim-text>6. Audio interface circuitry as claimed in claim 5 wherein said first and second switches comprise depletion modes EEls within the first and second analogue signal paths respectively.</claim-text> <claim-text>7. Audio interface circuitry as claimed in any of claims 4 to 6 wherein said second analogue path is for receiving an audio signal from said contact and said second digital path is for transferring digital audio signals to said second contact.</claim-text> <claim-text>8. Audio interface circuitry as claimed in any of claims 3 to 7 comprising: a third analogue signal path for transferring analogue audio data to/from a third contact on a connector; a third digital path, wherein said third digital path is a path providing power to the interface circuitry from a third contact of a connector; and a third switch for enabling/disabling the third analogue path.</claim-text> <claim-text>9. Audio interface circuitry as claimed in 8 wherein the third switch defaults to enabling the third analogue signal path.</claim-text> <claim-text>10. Audio interface circuitry as claimed in claim 8 or claim 9 wherein said third analogue signal path is for transferring analogue audio data to the third contact of the connector.</claim-text> <claim-text>11. Audio interface circuitry as claimed in any of claims 3 to 7 wherein the interface circuitry comprise circuitry configured to, in the digital mode, derive power from digital audio signals received on said first digital data path.</claim-text> <claim-text>12. Audio interface circuitry as claimed in any of claims 4-11 wherein said first and second analogue signal paths are for receiving audio data for respective loudspeakers.</claim-text> <claim-text>13. Audio interface circuitry as claimed in claim 12 when dependent on any of claims 8-10, wherein said third analogue signal path is for transferring audio data to the connector from a microphone.</claim-text> <claim-text>14. Audio interface circuitry as claimed in any of claims 2-8 comprising digital decoding circuitry coupled to said first digital path configured to decode said data pulses in the digital mode.</claim-text> <claim-text>15. Audio interface circuitry as claimed in claim 14 when dependent on claim? comprising digital encoding circuitry coupled to said second digital path configured to encode data pulses in the digital mode.</claim-text> <claim-text>16. Audio interface circuitry as claimed in claim 8 or any claim dependent on claim 8 comprising discrimination circuitry configured to, when power is available on the third digital path, to determine whether to operate in the digital mode and, if so, generate a control signal to disable the analogue signal paths.</claim-text> <claim-text>17. Audio interface circuitry as claimed in claim 16 wherein said discrimination circuitry is configured to, when power is available on the third digital path, to attempt handshaking with a device connected via said connector.</claim-text> <claim-text>18. Audio interface circuitry as claimed in any preceding claim comprising a ground path for connecting to a ground contact on a connector in both said digital and said analogue mode.</claim-text> <claim-text>19. An integrated circuit comprising audio interface circuitry as claimed in any of claims ito 18.</claim-text> <claim-text>20. An audio apparatus comprising audio interface circuitry as claimed in any preceding claim and at least a first audio output transducer, where said interface circuitry is configure to forward a received analogue audio signal to said first audio output transducer in the analogue mode and to decode said digital audio signal and forward a decoded digital data stream to said first audio output transducer in the digital mode.</claim-text> <claim-text>21. An audio apparatus comprising audio interface circuitry as claimed in claim 4 or any of claims 5-18 when dependent on claim 4 and at least first and second audio output transducers wherein, when enabled, said first and second analogue signal paths provides a direct connection to said first and second audio output transducers respectively.</claim-text> <claim-text>22. An audio apparatus as claimed in claim 21 when dependent on claim 15 wherein said digital decoding circuitry comprises first and second analogue output for connecting to said first and second audio output transducers respectively.</claim-text> <claim-text>23. An audio apparatus as claimed in claim 22 wherein said first and second switches switch between the first and second analogue signal paths and the first and second outputs of the digital decoding circuitry.</claim-text> <claim-text>24. An audio apparatus comprising audio interface circuitry as claimed claim 4 or any of claims 5-18 when dependent on claim 4 and at least first and second audio transducers wherein said first and second signal paths are connected to first and second converters for converting between analogue and digital signals such that any analogue audio signals received for the transducers are converted to corresponding digital signals.</claim-text> <claim-text>25. An audio apparatus as claimed in claim 24 comprising digital processing circuitry configured to apply digital processing to the digital signals output from said first and second converters.</claim-text> <claim-text>26. An audio apparatus as claimed in claim 25 wherein said digital processing circuitry comprises analogue outputs for connecting to said first and second transducers respectively.</claim-text> <claim-text>27. An audio apparatus as claimed in any of claims 20-26 wherein said interface circuitry is connected to a connector and said connector is a TRRS jack.</claim-text> <claim-text>28. An audio apparatus as claimed in any of claims 20-27 wherein the apparatus is an audio headset.</claim-text> <claim-text>29. An audio apparatus as claimed in any of claims 20-27 where the apparatus is an accessory apparatus configured to be connected to an electronic device.</claim-text> <claim-text>30. An audio apparatus as claimed in claim 29 where said accessory apparatus is configured to be connected to an electronic device which is at least one of: a portable device, a battery powered device, a communications device; a computing device; a media player; a mobile telephone.</claim-text> <claim-text>31. A method of receiving audio signals comprising: receiving said audio signals at an interface operable in analogue mode and also in digital mode and selecting a mode to operate in, wherein: in said analogue mode at least one analogue audio signal is received and forwarded for an audio output transducer; and in said digital mode at least one digital audio signal is received, said digital audio signal comprising a series of data pulses wherein the length of each pulse encodes at least two audio data streams, and the interface circuitry decodes at least one of said data streams and forwards said digital data stream for an audio output transducer.</claim-text> <claim-text>32. A method as claimed in claim 31 comprising determining whether a connected device transmitting the audio signals is capable of sending signals suitable for the digital mode and, if so operating in the digital mode, otherwise operating in the analogue mode.</claim-text> <claim-text>33. Audio interface circuitry for receiving audio signals wherein said interface circuitry is operable: in an analogue mode to receive analogue audio signals; and in a digital mode to receive digital audio signals wherein, in said digital mode, the audio data comprises a series of data pulses at a pulse rate wherein the length of each pulse encodes at least two audio data streams.</claim-text> <claim-text>34. Audio interface circuitry for transmitting audio signals to an apparatus external to a host device wherein said interface circuitry is operable: in an analogue mode to transmit analogue audio signals; and in a digital mode to transmit digital audio signals wherein, in said digital mode, the audio data comprises a series of data pulses at a pulse rate wherein the length of each pulse encodes at least two audio data streams.</claim-text> <claim-text>35. Audio interface circuitry as claimed in claim 34 comprising: at least first and second analogue signal paths for transmitting analogue audio data to respective first and second contacts on a connector; at least a first digital path for transmitting digital audio signals to the first contact on the connector; and at least a second digital path coupled to a second contact on the connector.</claim-text> <claim-text>36. Audio interface circuitry as claimed in claim 35 wherein the second digital path is for receiving digital data from the second contact in digital mode.</claim-text> <claim-text>37. Audio interface circuitry as claimed in claim 35 or claim 36 comprising: a third analogue signal paths for receiving analogue audio data from a third contact on a connector; a third digital path for transmitting power to the third contact on the connector in digital mode.</claim-text> <claim-text>38. Audio interface circuitry as claimed in any of claims 34 to 37 comprising at least a first interface for digital communication with a first component of a host device and a second interface for digital communication with a second component of a host device.</claim-text> <claim-text>39. Audio interface circuitry as claimed in claim 38 having a digital only path for communication between said first and second interfaces.</claim-text> <claim-text>40. Audio interface circuitry as claimed in claim 38 or claim 39 where said first component comprises an applications processor, a baseband processor, a transmission codec or a wireless codec.</claim-text> <claim-text>41. An audio codec comprising audio interface circuitry as claimed in any of claims 34 to 37.</claim-text> <claim-text>42. An audio processing circuit comprising audio interface circuitry as claimed in any of claims 34 to 40 or an audio codec of claim 41.</claim-text> <claim-text>43. An audio device comprising audio interface circuitry as claimed in any of claims 34 to 40.</claim-text> <claim-text>44. An audio device as claimed in claim 43 wherein said device is at least one of: a portable device, a battery powered device, a communications device; a computing device; a media player; a mobile telephone.</claim-text> <claim-text>A headset for receiving audio signals comprising at least one audio output transducer and a connector for connecting to an audio device wherein the headset is operable in a digital mode for receiving digital audio signals via said connector and applying said digital audio signals to said at least one audio output transducer and an analogue mode for receiving analogue audio signals via said connector and applying said received analogue audio signals said at least one audio output transducer.</claim-text> <claim-text>46. An audio apparatus comprising: at least first and second audio output transducers; a connector for connecting the audio apparatus to another device having at least first and second contacts; interface circuitry operable: in a first mode to enable first and second analogue signal paths from the first and second contacts directly to the first and second audio output transducers respectively; and in a second mode to disable said first and second analogue signal paths and provide at least a first digital signal path from the first contact to a digital decoder.</claim-text> <claim-text>47. An audio apparatus as claimed in claim 46 wherein in said digital mode the interface circuitry provides power to the digital decoder from the second contact.</claim-text>