GB2397946A - Cadmium telluride based multi-layer graded band gap photovoltaic device - Google Patents

Abstract

A 11-Vi and 111-V thin film photovoltaic device comprises multiple layers, where the band gap energy of the semiconductor layers decreases form a wide band gap CdS window layer towards a Schottky metal contact at the surface of a CdTe layer. A thin surface portion of the CdTe layer is converted to p-type conductivity. A thin insulating layer may be provided between the Schottky metal contact and the CdTe semiconductor layer.

Description

THIN FILM PHOTOVOLTAIC DEVICES AND METHODS OF MAKING

THE SAME

Field of the Invention

The present invention relates to the field of thin film photovoltaic devices.

The invention more particularly, but not exclusively, relates to improved photovoltaic devices, and methods of their manufacture, which comprise photon absorber semiconductor compounds made up of elements from Class II B and Group Vl, or Groups lil and V, of the Periodic Table of Elements.

o Backaround to the Invention

Development of a low cost thin film solar cell device with a reasonable efficiency for terrestrial solar energy conversion has been the subject of active research over the past two decades. Throughout the world, two systems are currently under substantial research and development-systems based on using s CuinGaSe2 (CIGS) absorber materials and those using cadmium telluride (CdTe) based absorber materials. CIGS based solar cells are currently leading with record efficiencies of 18.8% [Reference No. 1] and CdTe based solar cells have achieved 15.9% efficiencies [Reference No. 2], to date, for small-scale laboratory devices. The development of CdTe based solar cells is hampered, at least in part, by the lack of understanding of the physics of the device structure. The prior art model of a standard CdTe based solar cell, which is widely accepted, is based on a standard pen junction. This prior art model is, it is submitted herein, inadequate and therefore requires substantial modification to enable progress to be made as regards improvement of CdTe based and other types of solar cells and photovoltaic devices.

Currently accepted model based on a pen Junction Known CdTe based thin film solar cells consist of two semiconducting layers! A wide band gap etype CdS (Eg=2.42 eV) layer is used as the window so material and a smaller band gap CdTe (Eg=1.45 eV) layer is used as the lower energy photon absorber material. If the CdTe layer is p-type, then the active junction is regarded as a simple pen type heterojunction, and the required internal electric field within the device is provided by this interface.

To date, various methods have been used to grow the materials and fabricate devices using the above two material layers. A genuine pen junction device could have a typical assumed prior art structure 101 of metal-1/n- CdS/p- CdTe/metal-2, providing two ohmic contacts for collection of current from the device, as is schematically illustrated in Fig. 1. Metal-1 102, serves as the ohmic contact to the n-CdS layer 103 and a suitable metal contact 104 such as Au, Cu/Au, Cu/Ni or Ni serves as the ohmic contact to the p-type CdTe layer 105.

There are numerous publications on these types of genuine pen junction type thin film solar cells in the literature.

As is known to those skilled in the art for a standard pen junction of the type schematically illustrated in Fig. 1, in the case of an illuminated pen junction, photogenerated electrons move towards the e- type layer and holes move towards the p-type layer, creating a current in the external circuit.

Globally, a large amount of research has been directed to glass/Conducting Glass(CG)/CdS/CdTe/metal structures using low cost and transparent glass/CG substrates as the starting material. The conducting glasses used are usually indium tin oxide (ITO) or fluorine doped tin oxide (FTO) with metallic conduction and over 98% light transparency. The CdS layer used is always e-type and various growth methods such as chemical bath deposition (CBD), electrodeposition (ED), spray pyrolysis and vacuum evaporation have been used to produce this window layer. The thickness of the CdS window layer varies from 0.05 microns (pm), to a few microns, according to the state of the art. The absorber layer! CdTe, has also been produced using a variety of methods such as electrodeposition and the closed space sublimation technique (CSST). The so thickness of the CdTe layer typically varies from about 2 microns up to about 5 microns. A typical device may contain a 0.1 micron layer of CdS and about 2 microns in thickness of CdTe. As is known to those skilled in the art the fabrication process of the complete solar cell consists of one or more selected chemical treatments, post deposition heat treatment, chemical etching and metallisation. Thus for example, chemical treatment of the CdTe layer with CdCi2 followed by heat treatment in air at 450 C for approximately 20 minutes have been found to be beneficial, but little understood steps, for obtaining the required degree of photovoltaic activity for this device. In the early 1980's, this device was first fabricated by Basol et al [Reference No. 3] and the observed photovoltaic effect was explained in terms of complete type conversion of the CdTe layer from e-type to p-type during annealing in an air atmosphere, forming the active pen To junction at the n-CdS/p-CdTe interface. Although this original work produced an excellent device with a good scientific explanation to describe the action of the solar cell, unfortunately this explanation has been taken for granted over the past two decades. Research activities have been carried out on the basis of this assumed model and hence the development of this device has been unduly hindered due to misguided analysis and understanding of the underlying physics.

Comprehensive work on metal/CdTe interfaces over the last two decades has shed light on this complex system and has pointed to the need for improved methods of designing, modelling and fabricating cadmium based photovoltaic devices that exhibit improved efficiencies with scope for further improvement 2 o thereafter. The present state of the art is particularly well set out in the paper by Fritsche et al, 2001 (Reference No. 18), from which it is clearly stated that there is a problem with further developing CdTe based photovoltaic devices due to a lack of understanding of the underlying mechanisms operating in these devices.

2 5 Summarv of the Invention One object of the present invention is to formulate a new an improved model for photovoltaic devices such as thin film multi-layer solar cells.

Another object of the present invention is to provide guidelines, based on o the new model, for further increasing the performance efficiencies of photovoltaic devices designed and fabricated in accordance with the invention.

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Another object of the present invention is to provide improved methods for designing and fabricating photovoltaic devices which comprise photon absorber layers substantially made of compounds from the set of compounds: (a) Class II B element, of the Periodic Table of the Elements, and Group Vl element containing compounds, and (b) Group lil element and Group V element containing compounds.

0 A further object of the present invention is to formulate a new or improved model for glass/conducting glass/CdS/CdTe/metal solar cells and other photovoltaic devices.

Yet a further object of the present invention is to utilise the new guidelines to s fabricate improved photovoltaic devices, such as CdS/CdTe based devices, producing open circuit voltage (VOC) values over 600 mV, fill factor (FF) values over 0.45, short circuit current density (Jsc) values over 60 mAcm2 and efficiencies of 18%.

A further object of the present invention is, following improvement of Jsc in t accordance with the methods of the invention, to develop and fabricate improved I multilayer graded band gap tandem solar cells based on the CdS/CdTe system.

According to a first aspect of the present invention there is provided A thin 2 film photovoltaic device comprising: an e-type thin film window layer of a first semiconducting material substantially comprising a compound from the set of compounds: so (i) Class II B elements, of the Periodic Table of Elements, and Group Vl element containing compounds; and (ii) Group 111 element and Group V element containing compounds; an etype thin film photon absorber layer of a second semiconductor material, said photon absorber layer substantially comprising a compound from the set of compounds: (i) Class 11 B elements, of the Periodic Table of Elements, and Group Vl element containing compounds; and To (ii) Group 111 element and Group V element containing compounds; and a metal contact affixed to the outer surface of said second material layer; said device being characterized in that: in between said first and said second semiconductor layers there is an intermediate thin film layer of a third semiconductor photon absorber material substantially comprising a compound from the set of compounds: (i) Class 11 B elements, of the Periodic Table of Elements, and I Group Vl element containing compounds; and (ii) Group 111 element and Group V element containing compounds; and wherein the band gap of said semiconducting materials decreases from said window material to said outermost second said semiconducting material.

In a preferred embodiment of such a multi layered device, each said semiconductor layer comprises the element cadmium.

Preferably, one or more of said layers are deposited by electrodeposition.

Preferably, said window layer comprises e-type cadmium sulphide.

Preferably, said window layer comprises e-type zinc selenide.

Preferably, said intermediate layer comprises e-type cadmium selenide (CdSe).

o Preferably, said outermost second semiconductor layer comprises cadmium telluride.

In a further preferred embodiment, said device is further characterized in that: in accordance with a predetermined model of said device wherein said second and said intermediate photon absorber layers are substantially e-type during operation; an n-n heterojunction is required within said device; and a large Schottky barrier is required at the metal- second semiconductor thin film interface, at least one of said second and said intermediate layers has been treated to enhance its e-type electrical conductivity; and said second semiconductor layer has been treated, to increase the height of said Schottky barrier at the interface between said second semiconductor layer and said metal contact, by pinning the Fermi energy level of said second layer below the conduction band minimum and closer to the valence band maximum.

Preferably, said enhancement of said e-type electrical conduction is due to e-type doping.

Suitably, said enhancement of said e-type electrical conduction comprises treatment with CdCI2,Cdl2 or CdBr2.

Preferably, said second semi-conductor layer is doped with an impurity comprising iodine, bromine or chlorine atoms.

Preferably, said layers are heated in air to a temperature of 250 to 500 C.

Preferably, said layers are heated at a temperature of approximately 450 C for approximately 20 minutes.

Preferably, said device is treated to encourage mixing of the semiconductor layer materials at the boundaries of said layers.

Preferably, in between said back metal contact and said second photon absorber layer, there is additionally included a protective layer so configured to prevent reaction between said second semiconductor material and said metal.

Preferably, said protective layer comprises an organic polymer, an inorganic fluoride layer or a p-type conducting polymer.

Preferably, said device comprises a multi-layer graded band gap structure.

Preferably, the outer surface of said second semiconductor material has been chemically etched.

Preferably said Fermi energy level is pinned at the largest of a plurality of predetermined energy level positions.

Said Fermi energy level may be pinned at approximately 0.96 eV. Said Fermi energy level may be pinned at approximately 1.18 eV.

Preferably, said semiconductor material comprises defect levels due to addition of impurities or native defects configured to enable capture of low energy infra-red electromagnetic radiation having an energy of less than 1.45 eV.

According to a second aspect of the present invention, there is provided a method of fabricating a thin film photovoltaic device of the type comprising: an e-type thin film window layer of a first semiconducting material : substantially comprising a compound from the set of compounds: (i) Class II B elements, of the Periodic Table of Elements, and Group Vl element containing compounds; and so (ii) Group lil element and Group V element containing compounds; an e-type thin film photon absorber layer of a second semiconductor material deposited on said window material layer, said second photon absorber layer substantially comprising a compound from the set of compounds: (i) Class II B elements, of the Periodic Table of Elements, and Group Vl element containing compounds; and (ii) Group lil element and Group V element containing compounds; and a metal contact affixed to an outer surface of said second layer; said method being characterized by comprising the steps of: configuring a layer of said first semiconductor material; I upon said first semiconductor material depositing an intermediate thin film layer of a semiconductor photon absorber material comprising a third compound from the set of compounds: (i) Class 11 B elements, of the Periodic Table of Elements, and Group Vl element containing compounds; and (ii) Group 111 element and Group V element containing compounds; on top of said intermediate layer depositing said second semiconductor material layer; and affixing said metal contact to said second layer, wherein the band gap of said semiconductor materials decreases from said window material layer to said outermost second semiconductor material layer.

2 Preferably, said method includes depositing at least one of the said layers using electrodeposition.

Preferably, said window layer comprises zinc selenide.

3 o Preferably, said second semiconductor comprises cadmium telluride.

Preferably, said intermediate layer comprises cadmium selenide.

Preferably, said cadmium telluride layer is doped with an e-type dopant.

Said dopant may comprise iodine, bromine or chlorine atoms.

Preferably, said layers are annealed in air at a temperature of approximately 450 C for 20 minutes.

To A further layer may be introduced between said second semiconductor material and said metal, said further layer being configured to protect said second semiconductor material from chemically reacting with said metal.

Brief Descrintion of the Drawinas For a better understanding of the invention and to show how the same may be carried into effect, there will now be described by way of example only, specific embodiments, methods and processes according to the present invention with reference to the accompanying drawings in which: Fig. 2 schematically illustrates a prior art ladder of Fermi level pinning positions identified to date using bulk n-CdTe/metal contact work, photoluminescence (PL), deep level transient spectroscopy (DLTS) and ballistic electron emission microscopy (BEEM) work [Reference No. 5]; Fig. 3 schematically illustrates, in accordance with the present invention, the energy band diagram of a glass/CG/CdS/CdTe/metal solar cell based on the proposed alternative model of a CdS/CdTe solar cell; so Fig. 4 schematically illustrates the electrical contacts used to identify the location of the rectifying interface of the fully fabricated device. Au and In/Ga contacts are used side by side and In/Ga contacts have been heated using a sharp soldering iron tip to form ohmic contacts. The measurement results and conclusions are summarised in Table 1 in the detailed description; Fig. 5 (a) schematically illustrates the barrier heights obtained from dark currentvoltage measurements for glass/CG/CdS/CdTe/metal solar cells, fabricated with electrodeposited CdS and CdTe thin layers; and (b) The VOC values under illumination also follow the same discrete trend and the vertical axes indicate the number of observations; 0 Fig. 6 schematically illustrates, in accordance with the photovoltaic device of Fig. 3, the main steps in producing a high efficiency CdTe based photovoltaic device of this type; Fig. 7 schematically illustrates a cadmium chalcogenides based solar cell having a layer of insulator (CaF2, SrF2 or a polymer) located between the CdTe layer and the metal contact layer; Fig. 8 further details the step of optimising the base metal contact by adding a layer of insulator; Fig. 9 schematically illustrates the energy band diagram of a 3-layer glass/CG/CdS/CdSe/CdTe/metal solar cell with an intermediate CdSe layer; Fig. 10 schematically illustrates in accordance with the photovoltaic device of Fig. 9, the main steps in producing a CdTe based multi-layer graded band gap photovoltaic device; and Fig. 11 schematically illustrates, for improved devices as configured in accordance with the invention, the current-voltage curves under dark conditions, so Figs. 11 (a) and (b), and under illuminated (AM1.5) conditions in Fig. 11 (c). Note the barrier height of 1.18 0.02 eV due to the Fermi level pinning at the lowest position and the high Jsc over 60 mAcm2.

Detailed Description of the Best Mode for Carrvina Out the Invention There will now be described by way of example the best mode contemplated by the inventors for carrying out the invention. In the following description numerous specific details are set forth in order to provide a thorough understanding of the present invention. It will be apparent however, to one skilled in the art, that the present invention may be practiced without limitation to these specific details. In other instances, well known methods and structures have not been described in detail so as not to unnecessarily obscure the present invention.

New model for glasslCG/CdSlCdTelmetal solar cell The methods, devices and model in accordance with the present invention have arisen, in part, from work reported on metal contacts to Il-VI semiconductors as reported in a review article [Reference No. 5] published in 1998. As a result of s a large body of information assessed by the inventors of the present invention the Schottky barrier formation at metal/n-CdTe interfaces is summarised using the last diagram of this article which is shown at 201 in Fig. 2. Work leading to the formulation of a structure of the type depicted in Fig. 2 was carried out on various e-type CdTe materials, and the Schottky barrier formation 202 is found to be o governed by Fermi level pinning at one of five possible discrete levels 203 to 207 respectively. These identified defect levels are situated in the band gap at 0.40+0.04, 0.65+0.02, 0.73+0.02, 0.96+0.04 and 1.18+0.02 eV below the conduction band minimum. Depending on the history of the CdTe material 208, the particular fabrication process and the metal contact 209 used, the Fermi level s pinning is found to take place in one of the above identified five levels. A high density of these local defect states can be found in the top surface layer of the CdTe with a thickness of a few 100A (a few tens of nanometres; 100 A = 10 nary), and some of these defects coincide with the native defects found in the bulk material. The thickness of this modified surface layer depends on the surface treatment and etching prior to metallisation. Although this work was carried out in the past on bulk CdTe crystals, the principal inventor's subsequent work on electrodeposited CdTe thin layers has also produced an identical picture (Figure 5(a)) as described later under the heading 'Conclusions' It is known to those skilled in the art that for CdTe the same multi-layer pinning picture emerges from most of the published work in literature, irrespective of the growth method used for production of CdTe layers. As will be understood by those skilled in the art the new model of a CdTe/CdS based solar cell and the associated methods of fabrication have been derived by the inventors over many years of research.

However for purposes of conciseness the derivation of the new model and associated methods presented herein is based on the summary of observed results [Reference No. 5] on metal/n-CdTe interfaces as shown in Fig. 2 and its application to the CdTe/CdS system.

When the glass/CG/CdS/CdTe/metal structure is fabricated using methods such as chemical bath deposition, the closed spaced sublimation technique or :s electrodeposition, the energy band diagram of a CdTe/CdS device as modelled and as indicated in accordance with the present invention takes the form 301 as shown in Fig. 3. The CdS layer 302 is e-type and usually provides a better substrate than the conducting glass for growth of better quality CdTe material.

When adding a metal contact to a given batch of cadmium telluride material a set do of pinning levels as identified above, can be present in the final material. The particular pinning level achieved depends on the specific material property and any processing effected upon the cadmium telluride. Furthermore the pinning level obtained defines the Schottky barrier height present in a device configured in accordance with the invention. Since there are five pinning levels then there is s effectively a one out five chance of obtaining any one pinning level, but this is strongly dependent on the defect concentrations of each level. Although the multi-layer pinning model of Fig. 2 is known it has not previously been used in relation to undertaking investigations of the cadmium sulphide/cadmium telluride type solar cell systems. This is due to a deep seated belief in the fundamental so operating mechanism underlying this structure. In particular Basol's US patent No.4,388,483 clearly describes this system as being annealed in air with the result that e-type cadmium telluride undergoes total type conversion to become a p-type material. In accordance with Basol's universally believed model, the device becomes active only upon the type conversion stage having taken place. In view of Basol's model having being taken so literally for many years then those skilled in the art of photovoltaic and solar cell research have found it difficult to consider any other model. It is relatively straightforward to see why a revised CdS/CdTe model which takes into account the model of Fig. 2 has not been arrived at previously. The main reason is that the model of Fig. 2 relates to e-type cadmium telluride-metal interfaces whereas Basol's model concerns p-type cadmium telluride-metal interfaces. Thus those skilled in the art have been strongly lead To away from a consideration, of the possible incorporation of the model of Fig. 2 into Basol's classic pen junction model. A further reason for those skilled in the art, not attempting to incorporate the model of Fig. 2 into Basol's model is that the Fermi energy level pinning positions are particularly variable and therefore these have caused much confusion in solar cell research, in effect providing a s substantial background 'noise' in experimental results. In other words, since these levels have not been taken into account as occurring in CdS/CdTe type systems then any results obtained through experimentation have been jeopardised in a random way.

go In accordance with the new proposed model the following elements are present: À The cadmium telluride layer remains substantially e-type during operation; this is in complete contrast to the Basol type model, wherein total type conversion from e-type to p-type is required; There exists a multi-layer Fermi energy level situation at the back metal contact-photon absorber (CdTe) interface; this is in complete contrast to the prior art model wherein an ohmic contact is required; and À A large Schottky barrier is required at the metal/cadmium telluride interface; again this is in complete contrast to the prior art model in that in the prior art model a zero Schottky barrier is required - in other words an ohmic contact is required.

The above features of the new model are in complete contrast to the almost

universally accepted prior art model.

To further enhance the devices as configured in accordance with the prior art model, existing research attempts by those skilled in the art have concerned doping the assumed p-type cadmium telluride layer with a specifically selected p type dopant. Any form of doping other than p-type doping would clearly be illogical in relation to the prior art model. This fact is especially clear from the Jo paper by J.Fritsche [Reference No. 18] wherein a 'magical' production step is discussed, but not understood. In contrast to the reports in the prior art the methods and device models in accordance with the present invention provide for industrially effective device production steps which are clearly understood.

The CdS layer may suitably be deposited by a process of electrodeposition upon conducting glass layer 303. N-type cadmium telluride layer 304 may similarly be deposited upon the cadmium sulphide layer. Following deposition of the layers doping using an e-type dopant such as cadmium chloride, may be effected so as to deliberately enhance the e-type conductivity characteristics of o the cadmium telluride layer and the cadmium sulphide layer. Following doping the layers may be suitably annealed at 450 C in air for approximately 20 minutes.

Following annealing and chemical etching a back metal contact 305 is added.

The model illustrated clearly shows holes 306, 307 migrating from the window layer to the metal and electrons 308, 309, having been exited by sunlight 310, returning to lower energies as they drift towards the conducting glass layer 303.

Cadmium sulphide has a band gap value of 2.42 eV and cadmium telluride has a band gap of 1.45 eV. Thus cadmium sulphide captures higher energy portions of the electromagnetic spectrum than cadmium telluride. The cadmium telluride is further enhanced to capture electromagnetic radiation having energy less than 1.45 eV by defect levels of the type e-type indicated at 311. The narrow p-like region 312 is responsible for the Fermi level pinning forming the Schottky barrier height as shown. The region may be extremely narrow, but provides the required defect concentrations required for the functionality of the system. In contrast to the standard pen junction model, the active internal electric field is therefore provided by the n- n heterojunction within the device and the large Schottky barrier formed at the metal contact. Suitable impurity levels may arise from native defects already present and promoted within the crystal structure or via introduction of external impurities for example. Impurity levels provide a smaller band gap within the cadmium telluride material in which electromagnetic radiation of energies of less than 1.45 eV can be captured. In particular the Figure clearly illustrates capture of infrared radiation by such processes, resultant excitation of electrons and their movement towards the conducting glass layer 303. Clearly a greater Schottky barrier is produced by pinning at energy level E5, which in turn results in greater energies being inflicted upon electrons within the cadmium telluride and therefore in a greater open circuit voltage, larger short circuit current and increased efficiency of the device. In contrast to the prior art model wherein the heterojunction is situated at the junction between the cadmium sulphide and cadmium telluride, the model concerning the present invention provides the required potential gradient, that is the required internal electric field, by a combination of the n-n heterojunction at the junction between the CdS and CdTe layers and, more importantly, the Schottky barrier formed at 2 o the junction of the cadmium telluride and the metal contact.

In a preferred embodiment of the present invention a thin film photovoltaic device is provided, of the type comprising: an e-type thin film window layer of a semiconductor material; an e-type thin film semiconductor photon absorber layer deposited on the window material layer, the photon absorber layer substantially comprising a compound from the set of compounds comprising: o (i) Class II B element, of the Periodic Table of Elements, and Group Vl element containing compounds; and (ii) Group lil element and Group V element containing compounds; and a back metal contact affixed to the photon absorber layer; the device beingcharacterized in that: in accordance with a predetermined model of the device, wherein the photon absorber layer remains substantially e-type rather than undergoing type conversion, an n-n heterojunction is present within the device and a large Schottky barrier is required at the metalthin film photon absorber layer interface, the photon absorber layer has been treated to: a. enhance e-type electrical conduction; and b. increase the height of the Schottky barrier, at the interface between the metal contact and said photon absorber layer, by pinning the Fermi energy level below the conduction band minimum and close to the valence band 2 o maximum.

As will be appreciated by those skilled in the art a variety of treatments can be determined from the new proposed model. Using the model various optimised treatments can be derived. Thus from reviewing the Periodic Table of the Elements, other Class II B metal elements exist in addition to cadmium. These include, for example, zinc and mercury. Similarly, a range of viable Group Vl elements exist including tellurium, selenium, and sulphur. Electrical conduction through semiconductors is known to be affected by crystal structure and therefore better crystallinity is generally preferred. Since cadmium sulphide comprises a o sulphur atom which is located next to chlorine in the Periodic Table then chlorine atoms are suitable for doping a cadmium sulphide based layer without major deformation being inflicted upon the crystal structure. In relation to cadmium telluride, a suitable doping agent would be iodine. If a doping atom is chosen which is too large then the crystal lattice is effectively swelled and therefore electron mobility is reduced. Similarly if too small a doping atom is chosen for a particular layer then the crystal structure shrinks and acts as a scattering centre thereby reducing charge carrier mobility.

During the annealing process intermixing of CdS and CdTe takes place forming ternary and/or quaternary compounds creating a graded band gap interface at the n-n heterojunction. Chemical treatments and annealing process improve crystallinity of CdTe, form larger grains, remove unwanted defects in the material, passivate grain boundaries and bring the doping concentrations to moderate values in the range 1015-1017 cm3. The bulk of the CdTe layer remains e-type and the outermost layer contains high concentrations of defects responsible for Fermi level pinning at one of the five already identified levels. The thickness of the top surface layer varies in the region of a few 100A, depending on the processing steps such as heat treatment and etching procedure. If the Fermi level is pinned close to the valence band, at 0.96+0.04 or 1.18+0. 02 eV below the conduction band minimum, a large Schottky barrier is formed at the metal/CdTe interface creating the required band bending across the device for photovoltaic activity. Then the top surface layer of the CdTe material can be considered as a p-type layer, since the Fermi level is close to the valence band maximum. The resultant device, as those skilled in the art will realise, can be completely or partially depleted depending on the doping concentration achieved for the CdTe layer during growth and subsequent processing.

As the energy band diagram shown in Fig. 3 indicates, the internal electric fields near the n-n heterojunction and the metal/CdTe interface add up and this becomes a tandem solar cell. This model has been formulated using the complex results observed for metal/n-CdTe interfaces as summarised in Fig. 2. Note the o large Schottky barrier contact required at the e-type CdTe/metal interface (not to scale). If alloying at the CdS/CdTe interface has properly taken place during the annealing process, the device structure is effectively a multilayer graded band gap tandem solar cell capable of absorbing a major part of the solar spectrum.

Under optimum conditions, such a structure may produce large currents in excess of the theoretically predicted maximum current density of 25 mAcm-2 [Reference No. 6] for a single pen junction solar cell. In addition, this solar cell structure acts as an impurity photovoltaic cell creating electron-hole pairs by making use of defect levels within the bulk of the CdTe and at the CdTe/metal interface. For this creation of charge carriers, the photons with energy less than the band gap are used as schematically illustrated in Fig. 3. In this case since there is a strong electric field for charge carrier separation within the device, To recombination and generation centres are favourably used to create more charge carriers to produce a higher current in the external circuit. Referring to the prior art model of Fig. 1 there is designated an ohmic contact to the p-type CdTe/metal interface. In contrast, according to the new model conducting glass forms an ohmic contact to n-CdS and the back metal contact forms a large Schottky barrier at the metal/CdTe interface.

Description of observed experimental results in terms of the two 2 o models Current-Voltage (I-V) measurements When light enters through the glass/CG side, the photogenerated charge carriers are created within the semiconducting layers and are separated and s collected by the internal electric field. In both models electrons flow towards the conducting glass and holes flow towards the back metal contact making the CG layer negative and the metal contact positive in polarity. Both models produce similar polarity making it harder to think differently from the already assumed pen junction model.

Capacitance-Voltage (C-V) measurements According to both models, C-V measurements are possible due to the presence of at least one active interface within each device structure. If the device is fully depleted due to low doping concentrations of CdTe in the region of 10'5 cm3, capacitance values remain almost unchanged with the applied bias voltage approximately equal to the geometric capacitance of the structure. If the doping concentration is such that the depletion region covers only a part of the CdTe layer, then the capacitance varies according to the applied bias voltage o providing a reasonable 1 /C2 versus voltage plot and estimated doping concentration in the range 10'610'7 cm3. There are numerous examples of such C-V measurements in the literature which demonstrate the above behaviour producing, doping concentrations in the range 10451047 cm3. The work reported in References [7-10] are good examples for devices with efficiencies close to 10%.

Electron Beam Induced Current (EBIC) Measurements There are various reports in the literature giving EBIC results for such devices with contradicting conclusions [References: 11-13]. This method should 2 o create a peak of EBIC at the junction where the internal electric field is maximum.

However, previous reports have shown peaks appearing at the CdS/CdTe interface, in the middle region of the CdTe layer and at the metal/CdTe interface, and therefore provide inconclusive EBIC results. In fact, if the device is fully depleted, the EBIC peak could appear at any place where the material quality is high with resultant greater charge carrier collection efficiency. The EBIC results reported in the past could be explained using both models for this device structure.

Results from Electrical Contacting Work so Since the Schottky barrier at the metal/CdTe interface is determined by Fermi level pinning, almost any electrical contact shows the photovoltaic activity with varying efficiencies of this device, provided the electrical contact used does not completely destroy the p-layer on the surface. For example, a metal such as Cu. a p-type dopant of CdTe helps to keep the Fermi level close to the valence band and hence produce a low resistance contact. This will provide good results for freshly made devices, but with aging, Cu diffuses into the e-type CdTe region (ie beyond the surface p-layer) and forms a highly resistive layer due to compensation. Therefore the device will rapidly deteriorate showing an increased contact resistance. However, a contact containing a small amount of Cu will reduce the contact resistance due to p±doping of the surface p-layer without getting into the n-CdTe region. For this reason Cu/Ni or Cu/Au contacts with less than 5% Cu should act as a low resistive electrical contact. If the device is a simple pen junction, Cu should always produce a good ohmic contact to p-CdTe due to in-diffusion of this p-type dopant instead of forming highly resistive contacts with aging. These experimental observations provide supporting evidence for the proposed alternative model, but the prior art pen junction model :5 fails to explain the results.

If indium or aluminium is used as the contact metal, photovoltaic activity may still be observed with a large series resistance and hence with a very small fill factor. This is due to the compensation effect introduced by e-type dopants (In o or Al) in the p-type CdTe surface layer. The series resistance of 2 ME has been observed for In contacts, when Cu containing contacts show only 50 Q series resistance for 2 mm diameter devices [Reference No. 14]. In many situations, if the p-type surface layer is very thin and the interactions of indium and aluminium are considerable during the processing steps, the metal contacts completely consume the surface p-layer reaching the e-type CdTe and thereby producing an ohmic contact. In these situations, there is no photovoltaic activities observed for the device and the l-V curves show ohmic behaviour with low series resistance.

These observations provide further strong basis for the inventors' assertions that the prior art pen junction model of CdTe based solar cells is incorrect and thereby o leads to devices with resulting poor efficiencies.

Doping of CdS and CdTe layers The main improvement necessary to existing CdTe based photovoltaic devices is the reduction of series resistance to increase the fill factor. Some groups, on the basis of the assumed pen junction model have carried out very thoughtful experiments in the past, and the reports can be found in the literature [Reference No. 15]. A typical device contains about 2pm thick CdTe and a negligibly thin (0.05-0.10 m) CdS layer on the conducting glass substrate.

Therefore the main body of this device contains CdTe, and if this material is assumed to be p-type, the most sensible doping is with a p- type dopant in CdTe To to reduce the resistance. The elements Na, Ag and Cu are wellestablished p- dopants in CdTe [Reference No. 16], and these elements have been added with fine control to the CdTe layers. Highly unexpected results were observed with an improved shunt resistance, increased series resistance of the diodes and hence a drastic reduction of the efficiency, mainly due to loss in the fill factor [Reference :5 No. 14]. These results clearly illustrate that the main body of e-type CdTe material becomes resistive due to self compensation during doping with p-type dopants such as Na, Ag and Cu. Furthermore this experimental evidence strongly supports, in accordance with the present invention, the new model of the device and the associated methods of fabrication of improved photovoltiac devices. As is well known to those skilled in the art these experimental results cannot be explained using the assumed prior art pen junction model.

The positive and drastic effects on device performance by CdCI2 treatment of both CdS and CdTe layers have been puzzling researchers during the past two decades [Reference No. 17]. In this treatment, according to the new model, chlorine clearly helps the e-type doping of both layers reducing the series resistance and hence improving the fill factor drastically. This treatment also helps to keep the CdTe surface rich in cadmium, which is necessary for producing high quality Schottky barriers at metal/n-CdTe interfaces [Reference so No. 18]. There may also be other benefits such as a cementing effect of chlorine to form larger grains, but there are contradictory reports indicating substantial improvement of efficiency without observing any grain size improvements [Reference No. 4]. All these prior art reports do not discuss 'e-type' doping of the CdTe layer since all the explanations are based on the assumed pen junction device model. It should be noted that Cl is a well- established e-type dopant for CdTe material [Reference No. 16]. This most crucial CdCI2 treatment, needed for drastic device improvement, is therefore strong supporting evidence for the new model of concern to the present invention.

Further Experimental Evidence to Confirm the Structure of the Device To The observed results and interpretations presented in the above entitled Results from Electrical Contacting Work' and 'Doping of CdS and CdTe Layers' strongly indicate the supporting evidence for the new model put forward based on Fermi level pinning at the metal/n-CdTe interface. The following experiments have also been carried out to further test and confirm the nature of the device structure.

Following the usual procedure of the fabrication of the device structure as is well known to those skilled in the art, Au contacts and In/Ga contacts were made side by side on the same sample as shown in the Fig. 4. The device comprises a cadmium sulphide layer 401 deposited upon a conducting glass layer 402 which in turn is affixed to glass layer 403. Connected to conducting glass 402 is electrical connection 1. Deposited upon cadmium sulphide layer 401 is deposited cadmium telluride layer 402. Upon layer 402 are connected gold contacts 2 and 3 respectively, which are adjacent to each other, and two further adjacent contacts 4 and 5 respectively, each comprised of indium and gallium. The various situations tested are presented in Table 1. In/Ga contacts were annealed using a fine soldering iron tip to consume the top surface layer and hence to form a good ohmic contact between the In/Ga layer and e-type CdTe layer. Various contact combinations, as labelled in Fig. 4, were measured and the observations

3 o and conclusions are summarised in Table 1.

Table 1: A summary of current-voltage measurements carried out between different electrical contacts made on the device of Fig. 4 and the conclusions arising from these measurements. i

Two contacts Observations Remarks measured 1. Measurements Efficiency10%. Rectifying Good solar cells between between (1&2), contacts with reverse Au and CG contacts.

(1&3). current of 10-7A. Series resistance is100Q.

2. Measurements Effficiency0%, current in Two Schottky diodes are between both directions are in the back to back. Therefore (2&3) orderof107A. the current measured is the reverse current of one of the diodes and there is no collection of charge carriers from this combination.

3. Measurements No photovoltaic activity Annealed In/Ga consume between and good ohmic currents p-surface layer and make (1&4),(1&5) are observed with series goodohmiccontactston resistance of 80Q. CdTe layer. No rectification at CdS/CdTe interface and therefore photovoltaic activity is minimal.

4. Measurements No photovoltaic activity, In/Ga make ohmic between good ohmic currents with contacts to n-CdTe and (4&5) series resistance of 30Q. therefore conduction is through the CdTe layer.

5. Measurements Efficiency10%. Rectifying In/Ga provide ohmic between (2&4), contacts with reverse contact to n-CdTe and (3&5). current 10-7A. Series the rectifying contact is at resistance is 40Q. the Au/CdTe interface.

The above measurements confirm the existence of a large Schottky barrier at the Au/CdTe interface and the non-existence of a strong rectifying contact at the CdS/CdTe heterojunction. It is also noteworthy that Das and Morris' work [Reference No. 19] on production of a better solar cell of 9.8% for ITO/SnO2/CdTe/metal without a CdS layer than a solar cell of 8.8% for ITO/SnO2/CdS/CdTe/metal device with CdS layer [Reference No. 19]. This clearly indicates the rectifying contact required for photovoltaic activity is at the metal/CdTe interface rather than the CdS/CdTe heterojunction. A large body of subsequent measurements on the electrodeposited glass/CG/CdS/CdTe/metal structures, as performed by the inventors of the present invention, has also confirmed the Fermi level pinning of barrier height at discrete levels (Fig. 5a). In To particular levels producing a desirable large Schottky barrier are identified at 501 (0.96 eV) and at 502 (1.18 eV) respectively. It is interesting to note that exactly the same barrier heights are observed for electrodeposited CdTe thin layers, as are observed for metal contacts on bulk e-type CdTe (see Fig. 2). The different barrier heights, as shown in Fig. 5a appear for different batches of fabrication and their respective VOC values also tend to produce values which are discrete in nature, as shown in Fig. 5b at 504 and 505 respectively for example. The VOC values follow respective barrier heights since the VOC is a function of the barrier height. In order to produce high efficiency solar cells, the Fermi level should, in accordance with the present invention, be pinned at either 0.96+0.04 or 1.18+0.02 eV levels below the conduction band minimum.

Manufacture of and further development of the CdS/CdTe solar cell The results reported in the literature [Reference No. 5] combined with further work conducted by the inventors have enabled the new model of cadmium 2 chalcogenide based photovoltaic devices to be put forward.

Fig. 6 schematically illustrates, in accordance with the photovoltaic device of Fig. 3, the main steps in producing a high efficiency CdTe based photovoltaic device of this type. At step 601 a model of a photovoltaic device to be fabricated so is devised. A suitable model may comprise a model of the type schematically illustrated in Fig. 3. Such a model may be implemented on a computer so that various parameters may be adjusted and varied as desired with resulting effects indicated visually on a VDU. Following analysis of the model at step 602 required materials to construct the given photovoltaic device being fabricated may be obtained and any processing equipment required prepared. Similarly required treatments, such as for example doping solutions and the like, may be prepared ready for use. Following step 602, at step 603 a clean glass/conducting glass substrate is prepared ready for electrodeposition of the various semiconductor layers. At step 604 the prepared and degreased glass substrate layer is placed in an electrodeposition chamber and an e-type window layer of cadmium sulphide To is deposited. Alternatively, other suitable window materials may be deposited such as zinc selenide, or copper oxide. Of course other methods of deposition may also be used in accordance with the present invention. However, in terms of costs associated with deposition methods, chemical bath deposition or electrodeposition is considered to be the best mode of deposition for use in relation to the present invention. Following step 604, at step 605 the e-type window layer may be enhanced in terms of its electrical conductivity through doping with an e-type group 111 or group Vll element. Thus for example doping with indium or gallium or chlorine or iodine may be appropriate. As those skilled in the art will understand, particular doping agents used depend upon the exact nature of the materials utilised and these can in general be relatively quickly found through routine experimentation. Following step 605 an absorber layer of cadmium telluride is deposited so as to form an e-type layer on top of the window layer. As will be recalled, the prior art method concerns depositing a layer of ntype cadmium telluride, but the prior art model specified that the cadmium telluride is fully converted to p-type upon annealing. Following step 606, in accordance with the present invention, the cadmium telluride layer is further processed. The window layer may also be processed along with the cadmium telluride layer. However the cadmium telluride layer at least is processed so as to maximise its e-type properties. This is in clear contrast to the methods o associated with the prior art model. Thus for example the cadmium telluride layer is suitably doped with an e-type dopant such as with a group 111 or group V11 element. Suitable elements include chlorine atoms and iodine atoms. In the preferred embodiment iodine atoms are used. Following step 607, at step 608 an optimised back metal contact may be added to the cadmium telluride layer. By optimise it is meant to create a large Schottky barrier at the metal semiconductor interface. In the best mode contemplated by the inventors the largest Schottky barrier possible should be obtained. By optimization of the back metal contact it is meant careful selection of the particular metal used, but more importantly the processing of the cadmium telluride upper surface layer through heat treatment and etching to promote the desired characteristics. Following 608, at step 609 the fabricated device may be attached to an electrical circuit so as to provide To useful power for various applications. Further details as regards improving the window material, the narrower band gap photon absorber material and the back metal contact are given below.

Further main steps to allow further improvement of these solar cell structure to achieve improved efficiencies are as described below. Preferred techniques for depositing the layers are electrodeposition or chemical bath deposition.

Improvements to window material The use of glass/CG substrates with lowest sheet resistance, minimum surface roughness and the selection of a suitable e-type window material with required qualities is a good starting point. Maximised crystallinity, lowest possible number of defects and doping concentration close to 1046 cm3 will be desirable for the window material. In the case of n-CdS type window layers the doping of the material with group 111 elements or group Vll elements enhances the electrical conductivity of the films. However, the introduction of some of these elements disrupts the crystallinity reducing the mobility of charge carriers and hence reduces the required electrical conductivity. All measures taken with the aim of obtaining the optimum electrical conductivity contributes to the enhancement of the device performance. The CdCI2 treatment of the CdS layer has already o shown the positive effects of doping with chlorine.

lmprovements to absorber material The absorber layer of the order of 2 Am thickness should have optimised characteristics to optimise semiconduction properties such as better crystallinity, large grain size, grain boundary passivation, minimum possible recombination and generation centres and the lowest possible background impurities. The material layer should retain e-type electrical conduction and hence the ideal dopants will be group lil or group Vll elements. Achievement of doping concentrations in the desired region of 5x10'5-5x10'7 cm3 are optimal for this device structure. Many factors contribute to this ultimate doping concentration To and hence to achieve the optimum electrical conductivity given by o=nep. This requires systematic experimentation on materials growth, impurity identification and removal, doping and processing steps including heat treatment. The processing steps including chemical treatments with cadmium halide solutions, heat treatment in air and wet etching should produce a CdTe layer with optimum e-type properties together with a p-like surface layer of the order of a few 100A, to achieve the Fermi level pinning close to the valence band maximum.

Improvements to back metal contact For an efficient solar cell device, the Schottky barrier height should be either 0.96 or 1.18 eV for the system. The formation of lower Shottky barriers results in poor performance of the cadmium telluride/cadmium sulphide based solar cell and is due to the weak internal electric field created within the cell. Selection of a metal contact containing a small amount of p-type dopant such as Cu or Sb support the Fermi level pinning close to the valence band and thereby produces an efficient solar cell. Hence the Cu/Au, Cu/Ni or Sb containing contacts are good candidates to produce low resistance contacts to this device structure.

However, the in-diffusion of a p-type dopant into the e-type CdTe layer should be avoided in order to eliminate the formation of a very resistive electrical contact with aging. When this happens, and the efficiency drops down considerably, it so should be possible to remove the entire back contact using chemical etching, and reproduce the working device again if there is no damage to the thin film structure. This procedure should re-produce the high effciency devices again and work on this aspect of the invention by the inventors has indeed confirmed this observation [Reference No. 14]. Introduction of a p-type thin semiconducting layer with a band gap larger than that of CdTe (eg: ZnTe), or Sb containing layers such as Sb2Te3 protects the p-type top surface layer from reactions with the metal contact layer, improving both the efficiency and the durability of the device.

A suitable conducting polymer layer with p-type conduction and a band gap greater than that of CdTe is ideal for this purpose as schematically illustrated in Fig. 7. Inorganic/organic hybrid devices of this kind made using a conducting o polymer layer can significantly increase the lifetime of the solar cell. A further way of improving both the performance efficiency and the lifetime is to form a metal insulator- semiconductor (MIS) type contact with ultra thin insulating layers. The methods of forming, and suitable types of, such layers can be derived from a consideration of the work reported in Reference No. 20. Inorganic compounds such as calcium fluoride (CaF2) or strontium fluoride (SrF2) or any other insulating material is suitable for this purpose. As further advantage of using such a material is that pinhole plugging of the device is provided for.

Fig. 7 schematically illustrates a cadmium chalcogenide based solar cell 701 which comprises a conducting glass substrate 702, a cadmium sulphide layer 703 deposited upon layer 702 and a cadmium telluride layer 704 deposited upon layer 703. The prior art model of cadmium sulphide/cadmium telluride based solar cells clearly teaches a way from adding an insulating material between the cadmium telluride and a metal layer 705. However in accordance with the present invention the height of the Schottky barrier can be increased further by introducing an additional layer 706 between said cadmium telluride layer and said metal contact. The main purpose for introducing a layer is to prolong the lifetime of the solar cell by protecting the cadmium telluride upper surface layer from chemical reactions occurring with the metal. However a secondary advantage is that, if an insulating polymer is used, the Schottky barrier height is desirably increased. As another embodiment shown earlier, the cadmium telluride layer may be further enhanced in terms of it's e-type electrical characteristics - by doping with group lil or group Vll atoms 707, 708.

Fig. 8 further details the step of optimising the base metal contact as illustrated in Fig. 6 by adding a layer of insulating polymer of the type schematically illustrated in Fig. 7. Following step 607, at step 801 a given metal contact to use for a particular device being made is selected. Following step 801, at step 802 a selected protective layer, such as a conducting polymer or an insulating polymer, such as CaF2 or SrF2 is introduced on top of the cadmium telluride layer so as to protect the narrow p-type top surface layer of the cadmium telluride. Following step 802, at step 803, the metal contact selected at step 801 is added on top of the protective layer. The steps shown in Fig. 8 may be adjusted for a given device under construction. In particular, for devices based on different compounds to cadmium sulphide and cadmium telluride the :5 insulating layer is to be positioned between the metal and the outermost photon absorber layer.

Multilayer graded band gap approach The introduction of a third layer, between the window layer and the cadmium based photon absorber layer, withan intermediate energy band gap will enable the strengthening of the slope of the energy band diagram which is the internal electric field, in order to enhance the charge carrier collection. The energy band diagram of such a device is shown in Fig. 9 (not to scale) and CdSe with an intermediate band gap of 1.70 eV has been found to be particularly 2 5 suitable since the element Cd is common for all three semiconductors used. Thus e-type CdSe layer 901 is deposited on to an n-CdS window layer 902 and an n- type CdTe layer 903 is thereafter deposited on layer 901. The example illustarted clearly comprises an n-n-n type structure with the band gap of the layers decreasing in a direction towards the metal contact 904. Fig. 11 may be considered to be an extension of Fig. 3 and has a large Shottky barrier 905 located at the junction between the outermost photon absorber layer 903 and the metal contact 904. During annealing and the aging process, this structure becomes a multilayer graded band gap tandem solar cell due to intermixing of materials at two heterojunctions. Thus in the device illustrated a first heterojunction is present at the interface between layers 901 and 902 and a second heterojunction is present at the interface between layers 901 and 903. If there are no other detrimental effects within the device, this solar cell structure should improve its energy conversion ability with time. During annealing treatments, intermixing at heterogunctions takes place and the device structure becomes a graded band gap multilayer tandem device with improved collection efficiencies. Devices fabricated in this way improve at their heterojunctions with o aging and absorb a major part of the solar spectrum due to effective utilisation of photons at different regions of the device structure. Photons with energy less than 1.45 eV are also utilised within the CdTe layer and closer to the back metal contact as shown in Fig. 9 to create photogenerated charge carriers. These carriers are collected efficiently, with the existing high electric field in these thin :s film device structures. Since the theoretical efficiencies predicted for these type of devices are 86% [Reference No. 21], the future potential of these devices is very high.

The device of Fig. 9 is designed to absorb as much of the electromagnetic o spectrum as possible. The two junctions and the Schottky barrier effectively add together to provide an increased electrical potential across the device as compared to the two layer device of Fig. 3. In common with the device of Fig. 3 the outermost absorber layer 903 has a narrow p-type outer layer.

s Fig. 10 schematically illustrates, in accordance with the photovoltaic device of Fig. 9, the main steps in producing a CdTe based multi-layer graded band gap photovoltaic device structure. At step 1001 a model of the device to be fabricated is established in accordance with the present invention. Thus a device to be fabricated is required to comprise an etype thin film window layer of a o semiconducting material comprising, for example, a metal element from Class II B of the period table of elements; a thin film photon absorber layer formed of a second semiconductor material comprising a metal element, for example, from Class II B of the periodic table of the elements; and a back metal contact fixed to the outer surface of said second layer. In between the first and second semiconductor layers there is required an intermediate thin film layer of a third semiconductor photon absorber material comprising, for example, a metal element of Class II B of the periodic table of the elements. A further requirement is that the band gap of the semiconducting materials is required to decrease from the window material to the outermost second semiconducting material. In other words the band gap is required to be largest for the window material, next largest for the intermediate layer and smallest for the outermost photon absorber layer.

To As indicated in Fig. 9 a suitable material for the outermost absorber layer is n- type CdTe, a suitable material for the intermediate layer is e-type CdSe, and a preferred window layer is e-type ZnSe, although CdS will suffice. In accordance with the predetermined model of the device the second and the intermediate photon absorber layers remain substantially e-type and the large Schottky barrier : and two n-n heterojunctions provide the required internal electric field. At least one of the second and the intermediate layers is treated to enhance its e-type electrical conductivity and the second semiconductor layer is treated to increase the height of the Schottky barrier at the interface between the second semiconductor layer and the metal contact by pinning the Fermi energy level of To the second layer below the conduction band minimum. Following step 1001, at step 1002, required materials for fabricating the device are obtained and relevant processing equipment and treatments to be applied are prepared. Following step 1002, at step 1003, a clean glass/conducting glass substrate is prepared ready for electrodeposition purposes. At step 1004, the glass substrate is placed in an electrodeposition chamber and an e-type window layer of CdS, ZnSe or Cu2O is deposited thereon. Following step 1004, at step 1005, the window layer is preferably doped using an e-type dopant consisting of a group lil or group Vl1 element so as to obtain optimum electrical conductivity. Following step 1005, at step 1006 the intermediate photon absorber layer of e-type cadmium selenide is deposited and doped with an e-type dopant to improve its e-type electrical conductivity. Following step 1006, at step 1007 the outermost photon absorber layer of e-type cadmium telluride is deposited using electrodeposition. Following step 1007, in step 1008, the outer absorber layer is processed so as to maximise it's e-type properties by doping with an e-type dopant and adding impurities, such as iodine atoms, and heat treating and chemically etching the surface to create the desired Fermi energy level pinning positions. Following step 1008, at step 1009, a back metal contact is added and the contact with the outermost photon absorber layer is optimised. In other words as large a Schottky barrier as possible is configured at the metal-semiconductor interface so as to promote flow of electrons and holes as schematically illustrated in Fig. 9. Following step 1009, at step 1010 the completed device is attached to a circuit for useful power generation. An MIS type contact can also be used here, as described earlier, to enhance the performance and the durability of the device.

In accordance with the invention, each photon absorber layer substantially comprises a compound from the set of compounds comprising: (i) Class II B element, of the Periodic Table of Elements, and Group Vl element containing compounds; and (ii) Group lil element and Group V element containing compounds.

Thus, for example, in the case of a Class II B element, cadmium is preferred for each layer. Using the same Class II B element in each layer is preferred as it aids intermixing at the boundaries of the layers and therefore enhances the multi-layer nature of the device. Over time the multi-layered device may infect become a device having a high, and perhaps infinite, number of layers, each layer having a slightly different band gap value to it's neighbouring layers and therefore facilitating absorption of a large proportion of the electromagnetic spectrum. For the Group Vl element the preferred structure is as indicated in 9. That is CdS for the window layer, CdSe for the intermediate photon absorber layer and CdTe for the outer photon absorber layer. This is because, as shown in Fig. 9, the band gaps decrease in this order of layers and therefore a wider span of the electromagnetic spectrum is absorbed.

The invention also allows for photovoltaic devices to be fabricated using photon absorber compounds of a wide range of other semiconductor materials. In particular compounds comprised of Group lil and Group V elements may yield high efficiency devices. Examples of suitable material combinations include: Gallium nitride (GaN) as a wide band gap window photon absorber material together with gallium arsenide (GaAs) as a narrower band gap photon absorber layer; and Indium nitride (InN) as a wide band gap window material together with indium phosphide (InP) as a narrower band gap photon absorber layer.

As will be appreciated by those skilled in the art the methods of fabrication and design of photovoltaic devices may, in accordance with the invention, be used with and applied to the entire range of semiconductor materials. However in the best mode contemplated by the inventors compounds comprised of the above specified Class and groups of elements should be used.

o Summary of latest results

The latest glass/CG/CdS/CdTe/metal devices show dark l-V curves as shown in Figures 11(a) and 11(b). The rectification factors at 1.0V, for best devices show over 4 orders of magnitude. It should be noted that to achieve over 12% efficiencies from this system, only 3 orders of magnitude rectification factor is sufficient [Reference. 14]. The barrier heights extracted from the diodes which show ideality factors less than 1. 4, provide values close to 1.20 eV, which is the desired Schottky barrier height obtained by the deepest Fermi level pinning position close to the valence band maximum.

A typical l-V curve under AM1.5 illumination for our latest devices is shown in Fig. 11. The VOC over 600 mV, and fill factors about 0.45 are typical values obtained for these devices but the Jsc over 60 mAcm2 is strikingly high as expected for a multilayer graded band gap tandem solar cell device.

Conclusions

The novel alternative model for the device structure, glass/CG/CdS/CdTe/ metal, solar cell explains the device behaviour in terms of a combination of an n-n heterojunction and a large Schottky barrier at the CdTe/metal interface. The materials growth, chemical and heat treatments and wet chemical etching provide the right conditions for the Fermi level pinning to occur at one of five identified ladder of energy levels (0.40+0.04, 0. 65+0.02, 0.73+0.02, 0.96+0.04 and 1.18+0.02 eV) at the metal/CdTe interface. To produce an efficient solar cell structure, the Fermi level should be pinned close to the valence band maximum (ie at 0.96+0.04 or 1.18+0.02 eV). Since, in accordance with the invention, both materials in the device structure remain e-type, the device can be treated as an n-n-Schottky barrier structure. Appropriate doping and improvements to the metal contacts help to further improve the efficiency of the device. Devices fabricated in accordance with the present invention show typical values of VOC over 600 mV, fill factors of about 0.45 and Jsc over 60 mAcm2. The corresponding efficiencies observed are 18%. In contrast to these multi-layer devices as configured in accordance with the present invention, the highest reported efficiency value for the 2-layer device is 15.9% as presented in Reference No. 2. The improvement in the short circuit current density made possible by the present invention and the ability to further improve both VOC and FF indicates the possibility of achieving much higher efficiencies in the future.

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Claims (31)

1. Claims: 1. A thin film photovoltaic device comprising: an e-type thin film

   window layer of a first semiconducting material substantially comprising a compound from the set of compounds: (i) Class 11 B elements, of the Periodic Table of Elements, and Group Vl element containing compounds; and (ii) Group 111 element and Group V element containing compounds; an etype thin film photon absorber layer of a second semiconductor material, said photon absorber layer substantially comprising a compound from the set of compounds: (i) Class 11 B elements, of the Periodic Table of Elements, and Group Vl element containing compounds; and 2 0 (ii) Group 111 element and Group V element containing compounds; and a metal contact affixed to the outer surface of said second material layer; said device being characterized in that: in between said first and said second semiconductor layers there is an intermediate thin film layer of a third semiconductor photon absorber material 3 o substantially comprising a compound from the set of compounds: (i) Class 11 B elements, of the Periodic Table of Elements, and Group Vl element containing compounds; and (ii) Group 111 element and Group V element containing compounds; and wherein the band gap of said semiconducting materials decreases from said window material to said outermost second said semiconducting material.
2. 2. A thin film photovoltaic device according to Claim 1, wherein each said semiconductor layer comprises the element cadmium.
3. 3. A thin film photovoltaic device according to Claim 1 or 2, wherein one or more of said layers are deposited by electrodeposition.
4. 4. A thin film photovoltaic device according to any of Claims 1 to 3, wherein said window layer comprises e-type cadmium sulphide.
5. 5. A thin film photovoltaic device according to any of Claims 1 to 3, o wherein said window layer comprises e-type zinc selenide.
6. 6. A thin film photovoltaic device according to any of Claims 1 to 5, wherein said intermediate layer comprises e-type cadmium selenide (CdSe).

   2s
7. 7. A thin film photovoltaic device according to any of Claims 1 to 6, i wherein said outermost second semiconductor layer comprises cadmium telluride.
8. 8. A thin film photovoltaic device according to any of Claims 1 to 7, 3 o wherein said device is further characterized in that: in accordance with a predetermined model of said device wherein said second and said intermediate photon absorber layers are substantially e-type during operation; an n-n heterojunction is required within said device; and a large Schottky barrier is required at the metal-second semiconductor thin film interface, at least one of said second and said intermediate layers has been treated to enhance its e-type electrical conductivity; and said second semiconductor layer has been treated, to increase the height of said Schottky barrier at the interface between said second semiconductor layer and said metal contact, by pinning the Fermi energy level of said second layer below the conduction band minimum and closer to the valence band maximum.
9. 9. A thin film photovoltaic device according to Claim 8, wherein said enhancement of said e-type electrical conduction is due to e-type doping.
10. 10. A thin film photovoltaic device according to Claim 8 or Claim 9, o wherein said enhancement of said e-type electrical conduction comprises treatment with CdCI2,Cdl2 or CdBr2.
11. 11. A thin film photovoltaic device according to any of Claims 8 to 10, wherein said second semi-conductor layer is doped with an impurity comprising iodine, bromine or chlorine atoms.
12. 12. A thin film photovoltaic device according to any of Claims 1 to 11, wherein said layers are heated in air to a temperature of 250 to 500 C.
13. 13. A thin film photovoltaic device according to Claim 12, wherein said layers are heated at a temperature of approximately 450 C for approximately 20 minutes.
14. 14. A thin film photovoltaic device according to any of Claims 1 to 13, wherein said device is treated to encourage mixing of the semiconductor layer materials at the boundaries of said layers.
15. 15. A thin film photovoltaic device according to any of Claims 1 to 14, wherein in between said back metal contact and said second photon absorber layer, there is additionally included a protective layer so configured to prevent reaction between said second semiconductor material and said metal.
16. 16. A thin film photovoltaic device according to Claim 15, wherein said Is protective layer comprises an organic polymer, an inorganic fluoride layer or a p- type conducting polymer.
17. 17. A thin film photovoltaic device as claimed in any of Claims 1 to 16, wherein said device comprises a multi-layer graded band gap structure.
18. 18. A thin film photovoltaic device as claimed in any of Claims 1 to 17, wherein the outer surface of said second semiconductor material has been chemically etched.
19. 19. A thin film photovoltaic device according to Claim 8, wherein said Fermi energy level is pinned at the largest of a plurality of predetermined energy level positions.
20. 20. A photovoltaic device as claimed in Claim 19, wherein said Fermi o energy level is pinned at approximately 0.96 eV.
21. 21. A photovoltaic device according to Claim 20, wherein said Fermi energy level is pinned at approximately 1.18 eV.
22. 22. A photovoltaic device according to any of Claims 1 to 21, wherein said semiconductor material comprises defect levels due to addition of impurities I or native defects configured to enable capture of low energy infra-red electromagnetic radiation having an energy of less than 1.45 eV.
23. 23. A method of fabricating a thin film photovoltaic device of the type I o comprising: an e-type thin film window layer of a first semiconducting material substantially comprising a compound from the set of compounds: : (i) Class II B elements, of the Periodic Table of Elements, and Group Vl element containing compounds; and (ii) Group lil element and Group V element containing compounds; 2 o an e-type thin film photon absorber layer of a second semiconductor material deposited on said window material layer, said second photon absorber layer substantially comprising a compound from the set of compounds: (i) Class II B elements, of the Periodic Table of Elements, and I Group Vl element containing compounds; and (ii) Group lil element and Group V element containing compounds; and a metal contact affixed to an outer surface of said second layer; said method being characterised by comprising the steps of: configuring a layer of said first semiconductor material; upon said first semiconductor material depositing an intermediate thin film layer of a semiconductor photon absorber material comprising a third compound from the set of compounds: (i) Class 11 B elements, of the Periodic Table of Elements, and To Group Vl element containing compounds; and (ii) Group 111 element and Group V element containing compounds; on top of said intermediate layer depositing said second semiconductor material layer; and affixing said metal contact to said second layer, wherein the band gap of said semiconductor materials decreases from said window material layer to said outermost second semiconductor material layer.
24. 24. The method according to Claim 23, wherein said method includes depositing at least one of the said layers using electrodeposition.
25. 25. The method according to Claim 23 or Claim 24, wherein said window layer comprises zinc selenide.
26. 26. The method according to any of Claims 23 to 25, wherein said 3 o second semiconductor comprises cadmium telluride.
27. 27. The method according to any of Claims 23 to 26, wherein said intermediate layer comprises cadmium selenide.
28. 28. The method according to any of Claims 23 to 26, wherein said cadmium telluride layer is doped with an e-type dopant.
29. 29. The method according to Claim 28, wherein said dopant comprises iodine, bromine or chlorine atoms.

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30. 30. The method according to any of Claims 23 to 29, wherein said layers are annealed in air at a temperature of approximately 450 C for 20 minutes.
31. 31. The method according to any of Claims 23 to 31, wherein a further layer is introduced between said second semiconductor material and said metal, said further layer being configured to protect said second semiconductor material from chemically reacting with said metal.