GB2383455A

GB2383455A - Non-volatile memory and method for operating a non-volatile memory

Info

Publication number: GB2383455A
Application number: GB0130578A
Authority: GB
Inventors: Engelbert Wittich
Original assignee: Motorola Inc
Current assignee: Motorola Solutions Inc
Priority date: 2001-12-21
Filing date: 2001-12-21
Publication date: 2003-06-25
Anticipated expiration: 2021-12-21
Also published as: TW200301487A; AU2002351774A8; GB2383455B; GB0130578D0; WO2003054888A3; AU2002351774A1; WO2003054888A2

Abstract

A non-volatile memory 10 Fig 1 comprises an array 12 of individual memory cells 14, a read circuit 16, and an identifying circuit 18. The memory cells 14 of the arrays are individually capable of having a threshold voltage programmed or erased to an intended level within a range e.g. 22, 24 Fig 2, the range being between range boundary levels V 1 and V 0 . The read circuit 16 reads the range of an actual threshold voltage of memory cells, and the identifying circuit 18 identifies any memory cells 14 having an intended level e.g. 24 in at least one predefined range that each has it's actual threshold voltage 26 shifted beyond a predetermined margin level V m within the range different from the range boundary levels. The address of an identified memory cell may be memorised so that patching may be effected for error correction used for redundancy data. A counter may be used to count the events of the same memory cell for use in estimating the end of life of the memory.

Description

NON-VOLATILE MEMORY AND METHOD FOR OPERATING A NON- VOLATILE MEMORY This invention relates to a non-volatile memory and method for operating a non-volatile memory, especially to a memory of a microcontroller unit (MCU).

Background of the Invention Stand alone non-volatile or flash memories face a disturb effect that causes cells of an erased or programmed block to lose charge during a READ operation from their floating gates each time a READ operation is performed. It depends on the technology and implementation if an erased or a programmed block loses charge. Such effects can be dealt with by checking and either repairing or patching.

In US 5,963, 473 a non-volatile memory device comprising an array of non-volatile memory cells which can be either programmed or erased has a disturb count circuitry which generates an output indicating a cumulative disturb effect on a first portion of the array as a result of erase operations performed on other portions of the array.

US 6,314, 027 describes a flash memory device that includes an erase control circuit, used as a state machine, having embodied erase algorithm which can prevent flash memory cells from being over-erased. The erase control circuit, first, checks whether or not threshold voltages of selected cells reach a predetermined pre-verify voltage higher than the maximum value of a target threshold voltage range corresponding to the erased state. When at least one of the selected cells has its threshold voltage higher than the pre-verify voltage, a high voltage generator generates a bulk voltage that is increased step by step by a predetermined voltage level. And, when the selected cells all have threshold voltages equal to or less than the pre-verify voltage, the high voltage generator generates a constant bulk voltage.

US 6,049, 899 discloses a semiconductor non-volatile memory comprising an array of memory cells, the memory cells of said array being individually capable of having a threshold voltage programmed or erased to an intended level within a range supported by the memory system. Monitoring means invoked at least one of a plurality of predefined events of the memory system identify one

or more cells each having a threshold voltage shifted beyond a predetermined margin from its intended level, and writing means re-write said shifted threshold voltage back to its intended level. The memory cells are individually programmable into more than two states in order to store more than one bit of data per cell. Such a memory is a stand-alone memory controlled by a memory controller. The plurality of predefined events of the memory system include memory operations on a portion of the memory array that are liable to perturb cells within the portion of the memory array.

These above described US 5,963, 4731 US 6, 314, 0271 US 6,049, 899 disclosures address primarily problems during a programmed or erased operation. There is no distinction between data or executable program code. A status of access is unknown and memory controllers do not know if an application can be stopped for a repair of a perturbed cell.

US 6,216, 251 describes a microcontroller with a CPU an a memory containing a memory array. A large portion of the array is used to contain functional data for the CPU but the array also contains one or a few rows of memory content parity information. Once the array is written with lasting data and/or software, a parity controller will generate initial parity values which correlate to the contents of the memory array. After generating the initial parity data, the parity controller occasionally, upon some parity checking event, generates current parity from the data stored within the array that is compared against the parity portion of the array. If errors are detected, corrective measures may be taken to extend the reliable life of the product. The microcontroller is able to detect a data error after it has happened but cannot identifying any memory cells that are likely to experience a data error in the near future.

This invention seeks to provide a MCU which mitigates the above mentioned disadvantages. There is a need for a MCU having a non-volatile memory, wherein an anticipated data error in the memory is detected before it actually occurs, such that an intended normal operation of the MCU can continue.

Summary of the Invention According to the invention it made use of the situation that is given in a microcontroller, which is different the situation in a Stand alone non-volatile memory. The microcontroller has a processor and a memory (EEPROM, FLASH) RAM, lias Timers, PWMs and other peripherals possibly including a state machine. The main software of the processor knows exactly the status of the state machine and the application program. The processor can depending on application interrupt the program flow for a repair of a perturbed memory cell.

The state machine can be used and triggered from the processor for a repair cycle of an NVM cell. In the background of a user program the state machine can use free cycles of the processor for a memory test sequence.

With respect to an NVM READ operation this invention is manly addressing a read disturb effect (charge losses, data retention issue) as a result of a READ operation in a normal use operation mode. If during the READ operation charge loss happen because of different effects, the application can be warned and a user software can decide which corrective action should be taken.

If a floating gate cell has a threshold voltage shifted during the READ operation beyond a predetermined margin from its intended level, an application is endangered to run erroneous with wrong instruction code being executed.

An example and definition of a typical two-state NVM cell embedded in a microcontroller is now given. A programmed or erased two-state NVM cell tends to aim to a natural neutral state over the time. The charge of a cell can be drifting raising data retention problems. The definition of an ERASED and of a programmed state of an NVM cell is design dependent. For example an erased could be a logical "1" represented by a typical 5V-2. 6V and a programmed state of the cell would be a logical "0" represented by a typical 0-2. 5V. The natural neutral state of the cell could be 1.5V and coincide in this case with a logical"0".

A typical failure mechanism of an NVM cell is now described. The typical live time of a cell is 15 years under specified worst case conditions. But charge can be lost faster because of some unpredictable circumstances. For example electron traps in the oxide isolation or defects in the oxide etc. causes charge losses that can be accelerating by temperature.

The current invention achieves an early detection of critical charge shifts of cells and provides a decision process if a threshold voltage of cell needs repair of patching. With a simple comparator technique charge losses leasing to dangerous shifts can be early detected and thus prevent programs to run erroneously or prevent stored Data are changed.

According to the present invention an improved method is proposed to detect out of range cells (perturbed cells) during a READ operation or an instruction execution. Different methods and algorithms for monitoring cells over the time are suggested. In an embodiment of the invention an individual cell or a group of cells can be monitored if the cell voltage drifts to a level representing a dangerous logic value change (flipping from"1"to"0"or visa versa). The cell voltage/current is tested if the drift is passing several specified reference level points within a predefined period of time. Depending on the technology employed this reference level point can be used to decide if a level shift is going out of control and necessary action like re-write or patching is needed. This critical cell can only be judged from NVM test software to avoid a fatal error in a running application. The monitoring can be done in real-time or with a separate memory test. A memory test can run in the background of an application or can be performed during a Power ON or OFF phase of a device. Such an NVM test algorithm can use a state machine in parallel to a processor. A state machine can use processor cycles that do not access the memory. In case of real time monitoring during an instruction access of the processor to the NVM the state machine can still be optionally activated in parallel to the processor to control memory. The state machine can perform a repair process if needed.

Brief Description of the Drawing An exemplary embodiment of the invention will now be described with reference to the drawings in which: FIG. 1 shows a schematic block diagram of a preferred embodiment of a non-volatile memory in accordance with the invention;

FIG. 2 shows a schematic voltage diagram relating to the non-volatile memory of FIG. 1; FIG. 3 shows a schematic block diagram of different preferred embodiment of a non-volatile memory in accordance with the invention; FIG. 4 shows a schematic block diagram of a another preferred embodiment of a non-volatile memory in accordance with the invention; FIG. 5 shows a schematic block diagram of a further preferred embodiment of a non-volatile memory in accordance with the invention; and FIG. 6 shows a schematic block diagram of a preferred embodiment of a method in accordance with the invention.

Detailed Description of a Preferred Embodiment Referring to FIG. 1, there is shown a non-volatile memory (NVM) 10 comprising an array 12 of individual memory cells 14, a read circuit 16 and an identifying circuit 18.

FIG. 2 shows a schematic voltage V versus time t diagram 20. The memory cells 14 of the array 12 are individually capable of having a threshold voltage Vt programmed or erased to an intended level within a range. A range is defined between range boundary levels and represents a logical value. Here, the range 22 between boundary levels Vo and VB represents a logical "0" and, the range 24 between boundary levels VB and V1 represents a logical"1". The threshold voltage Vt is initially programmed to be at Vs and drifts by the time t along curve 26. If no event applies to the memory cell 14 such as reprogramming, erasing or a defect, then the threshold voltage Vt finally approaches a natural value here indicated as natural voltage VN.

As the threshold voltage Vt drifts along curve 26 it passes the boundary voltage VB which constitutes a critical error as it is now interpreted as a different logical value. Such errors have to be prevented. The present invention introduces a monitoring of the threshold voltage Vt at an additional margin level VM. At this additional margin level VM the read circuit 16 reads, here at time TR, the range of the actual threshold voltage correctly to be range 24 as intended being correctly interpreted at its logical value"1". Reaching VM nevertheless

indicates that the boundary voltage VB might be reached soon. According to the present invention this indication is used for taking a measure to prevent reaching the boundary voltage VB. At time TR the identifying circuit 18 identifys this memory cell as having it's intended level in the predefined range 24 and has it's actual threshold voltage Vt shifted beyond the predetermined margin level VM within the range 24 different from the range boundary levels VB and V1.

An erased memory cell would in a two-level cell usually not need to be monitored because it would not change it's logical value on it's drift to the natural voltage VN. However, in the case of multi-level cells, to which the present invention applies also, several ranges can be monitored.

In the following, the invention will be described with embodiments wherein an MCU comprises a processing unit and an embedded NVM. Such an application of the present invention is especially advantageus for several reasons. MCUs are integrated in typical appliances designed to having a proposed lifetime of 10 to 15 years. The NVM contains usually MCU software as well as appliance data and it is a demand that during the lifetime no critical error as described above occurs. An example is an MCU for automotive motor control where a critical error in the MCU software might lead to erroneous instructions being carried out or the processor is halted, or where a critical error in the appliance data might lead to valves being opened or closed at a wrong timing leading to immediate motor damage.

FIG. 3 shows schematically a memory according to the invention in form of an MCU 30 comprising a processing unit processor 32 and an embedded NVM 34. The NVM 34 further comprises an array 35 of memory cells 36, a comparator 38 and a control logic 40 comprising an adjustable DC power supply for supplying the NVM 34. The memory cells of the array 35 are individually capable of having a threshold voltage programmed or erased to an intended level within a range, the range being between range boundary levels. The processor 32 controls control logic 40 that is adapted for applying an adjustable test read potential during a read operation to at least one of bit lines of memory cells of the array. The comparator 38 receives analogue signals on lines 42, preferably for several cells in parallel, compares each to an internal voltage, and outputs a digital signal on bus 44 that is coupled to processor 32.

The processor 32, the comparator 38 and the control logic 40 form both a read circuit for reading the range of an actual threshold voltage of memory cells ; and an identifying circuit for identifying any memory cells having an intended level in at least one predefined range that each has it's actual threshold voltage shifted beyond a predetermined margin level within the range different from the range boundary levels. In the the array 35 memory cells 36 are coupled by bit lines (not shown) that allow to selectively address an individual memory cell 34 by applying predefined voltages to selected bit lines for an intended operation such as a read operation.

The adjustable adjustable DC power supply within control logic 40 according to the invention allows to apply a normal read potential to the bit lines for performing a normal read operation. With respect to FIG. 1 and FIG. 2, the arrangement acts as read circuit, wherein the comparator 38 receives analog signals representing the actual threshold voltages Vt of the memory cells 34 read. Then, the comparator discriminates at boundary voltage VB to interpret logical values "0" or "1".

The adjustable adjustable DC power supply within control logic 40 according to the invention also allows to apply a test read potential to the bit lines for performing a test read operation. The arrangement acts as identifying circuit, wherein the comparator 38 receives analog signals representing the modified voltages lower than threshold voltages Vt of the memory cells 34. Then, the comparator discriminates at a discriminator voltage that is within the comparator still unchanged to equal VB but represents a threshold voltage discrimination at the margin level VM to interpret logical values "0" or "1".

Thus, by performing a test read operation under test read conditions different from normal read conditions and by reading the NVM with both the normal read potential and the test read potential and comparing the results, here in processor 32, it can be detected if the actual treshold voltages of the cells under inspection are in the range greater than VB but lower than VM.

FIG. 4 shows schematically another embodiment of a memory according to the invention in form of an MCU 50 comprising a processing unit processor 52 and an embedded NVM 54. The NVM 54 further comprises an array 55 of memory cells 56, a comparator 58 and a control logic 60. The memory cells of the array 55 are individually capable of having a threshold voltage programmed

or erased to an intended level within a range, the range being between range boundary levels. The processor 52 controls control logic 60 that controls comparator 58 via control lines 61 to compare the actual threshold voltage of memory cells to several different voltages, i. e. to a discrimination voltage VB Of normal read operations, and to two different test voltages VM1., VM2. different from a discrimination voltage VB of normal read operations. Both test voltages VM1., VM2. allowa discrimination like the discrimination to VM described above, yet this example describes also the additional advantages of two test voltages VM1., VM2.. These analogue voltages are fed to the comparator 58 by control logic 60.

The comparator 58 receives analogue signals on lines 62, preferably for several cells in parallel, compares each to an internal voltage, and outputs a digital signal on bus 64 that is coupled to the processor 52, and on bus 66 that is coupled to the control logic 60.

The processor 52, the comparator 58 and the control logic 60 form both a read circuit for reading the range of an actual threshold voltage of memory cells ; and an identifying circuit for identifying any memory cells having an intended level in at least one predefined range that each has it's actual threshold voltage shifted beyond a predetermined margin level within the range different from the range boundary levels. Moreover, the arrangement comprises several comparators comparing the signal of one memory cell in parallel to different test voltages to identify any memory cells having the actual threshold voltage shifted beyond one of several predetermined margins from its intended level. Here, several comparators compare the signal of several memory cells in parallel to each test voltage, with respect to the width of bus 62.

Now is describes an advantageous application of two different test voltages VM1., VM2. different from a discrimination voltage VB of normal read operations. The invention allows to evaluate the reliability of the memory.

Assuming in the following that VM1 is greater than VM2, i. e. referring to FIG. 2, as the threshold voltage Vt drifts along curve 26 it reaches the VM1 margin before it reaches VM2 margin. Then, the identifying circuit is adapted to define an event of an identification of an identified memory cell. The time between the event of reaching the VM1 margin and the event of reaching the VM2 margin can be measured and gives an indication of the reliability of the memory. This is important because the NVM cells can be reprogrammed or erased only a limited

number of times that can be reached very soon if a defective cell is reprogrammed every time an error is detected or anticipated. Measuring the time between the events of reaching the two margins allows to monitor the aging or other behavior of the memory and allows to determine when the memory chip or the MCU is to be exchanged.

Several implementation of the controller 60 and the compataror 58 are possible. In one implementation the controller 60 receives the compare results as digital data on the bus 66 from the compataror 58. The controller 60 detects differences between the data read with the VM1 margin and VM2 the data read with the margin and gives appropriate signals to the processor 52.

In another implementation the bus 66 is omitted and the processor 52 receives all compare results as digital data subsequently on the bus 64 from the compataror 58. Then the processor 52 detects differences between the data read with the VM1 margin and VM2 the data read with the margin and takes appropriate actions.

An alternative embodiment of the invention is explained also with respect to FIG. 4 with the modification that the controller 60 controls the compataror 58 to perform a read operation on a memory cell with a test read access time shorter than normal read durations. Advantageously, integration times during the compare are controlled. Changing the read access time has an effect similar to changing the read potential to the bit lines of the NVM as described in connection with FIG. 3.

FIG. 5 shows schematically another embodiment of a memory according to the invention in form of an MCU 70 comprising a processing unit processor 72 and an embedded NVM 74. The NVM 74 further comprises an array 75 of memory cells 76, a comparator 78 and an ADC 80. The memory cells of the array 75 are individually capable of having a threshold voltage programmed or erased to an intended level within a range, the range being between range boundary levels.

The comparator 78 receives analogue signals on lines 82, preferably for several cells in parallel, compares each to an internal voltage, and outputs a digital signal on bus 84 that is coupled to the processor 72. The processor 72 controls ADC 80 to measure an actual threshold voltage of several memory cells

according to the widths of lines 82. The processor 72 compares the output of the ADC to a value representing a test voltage.

In an additional embodiment a multiplexer (not shown) can multiplex actual threshold voltage of several memory cells to a single ADC.

All examples described with Figs. 1,3, 4 and 5 allow to implement additional advantageous features. Regardless of the number of test voltages the arrangement comprising patching means for patching identified memory cells.

That is a logical data error is detected and corrected by a mechanism known in the art. Preferably only memory arrays are patched that are checked with a cyclic redundancy check (CRC) previously.

The non-volatile can further comprise a memorizing means for memorizing the address of an identified memory cell. This is helpful for patching and allows patching without reserving a memory part for error correction used for redundancy data.

The non-volatile memory can further comprise a counter for counting the events of the same memory cell. This allows to estimate the end of life of the memory.

The identifying of cells can be advantageously performed for the complete memory outside times of data access, i. e. as part of a startup mode or of a power off mode of the non-volatile memory.

In case of the memory being integrated within an MCU the identifying of cells can be advantageously performed in idle cycles of the processor in time slots during normal operation of the non-volatile memory.

A detected error can advantageously be corrected by writing the threshold voltage of identified memory cells to the intended level with a writing means.

Preferably this is performed after a CRC validation. Advantageously a re-writing of a cell is performed after an event or a defined number of events have occurred. Advantageously, also a write protection of the memory can be disabled selectively for repair of identified cells upon an event or a defined number of events.

FIG. 6 summarizes the method for operating a non-volatile memory according to the invention with respect to the memory described above together with Figs. 1-5 in Flow diagram 90. The method starts in step 92 reading the range of an actual threshold voltage of memory cells. It continues with step 94

identifying any memory cells having an intended level in at least one predefined range that each has it's actual threshold voltage shifted beyond a predetermined margin level within the range different from the range boundary levels. Then the results of steps 92 and 94 can be compared for detection of differences. If differences are detected then appropriate measures can be taken, e. g. a validation with CRC or parity check or repair.

Those of skill in the art will understand that the method steps can be carried out in any order. Advantageous embodiments have been already described with the different embodiments of the memory together with Figs. 1-5.

Claims

Claims 1. A non-volatile memory comprising : an array of memory cells, the memory cells of the array being individually capable of having a threshold voltage programmed or erased to an intended level within a range, the range being between range boundary levels ; a read circuit for reading the range of an actual threshold voltage of memory cells ; and an identifying circuit for identifying any memory cells having an intended level in at least one predefined range that each has it's actual threshold voltage shifted beyond a predetermined margin level within the range different from the range boundary levels.
2. The non-volatile memory of claim 1, further comprising means for applying an adjustable test read potential during a read operation to at least one of bit lines of memory cells of the array.
3. The non-volatile memory of claim 1, adapted to perform a test read operation under test read conditions different from normal read conditions.
4. The non-volatile memory of claim 1, further comprising comparing means for comparing the actual threshold voltage of memory cells to a test voltage different from a discrimination voltage of normal read operations.
5. The non-volatile memory of claim 4, wherein the comparing means comprises a comparator that is fed with an analogue test voltage.
6. The non-volatile memory of claim 4, further comprising several comparators comparing the signal of one memory cell in parallel to different test voltages to identify any memory cells having the actual threshold voltage shifted beyond one of several predetermined margins from its intended level.
7. The non-volatile memory of claim 4, further comprising several comparators comparing the signal of several memory cells in parallel to the test voltage.
8. The non-volatile memory of claim 4, wherein the comparing means comprises an ADC for measuring an actual threshold voltage of a memory cell.
9. The non-volatile memory of claim 8, wherein, the output of the ADC is compared by the processing unit to a value representing a test voltage.

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10. The non-volatile memory of claim 8, further comprising a multiplexer for multiplexing actual threshold voltage of several memory cells.
11. The non-volatile memory of claim 1, adapted to check several memory cells in parallel.
12. The non-volatile memory of claim 1, further comprising timing means for performing a read operation on a memory cell with a test read access time shorter than normal read durations.
13. The non-volatile memory of claim 1, wherein the identifying is part of a startup mode of the non-volatile memory.
14. The non-volatile memory of claim 1, wherein the identifying is part of a power off mode of the non-volatile memory.
15. The non-volatile memory of claim 1, wherein the identifying is entered in time slots during normal operation of the non-volatile memory.
16. The non-volatile memory of claim 1, further comprising writing means for writing the threshold voltage of identified memory cells to the intended level.
17. The non-volatile memory of claim 1, further comprising patching means for patching identified memory cells.
18. The non-volatile memory of claim 1, further comprising a memorizing means for memorizing the address of an identified memory cell.
19. The non-volatile memory of claim 1, wherein the identifying circuit is adapted to define an event of an identification of an identified memory cell.
20. The non-volatile memory of claim 19, further comprising a time measuring means for measuring the time between two events of the same memory cell.
21. The non-volatile memory of claim 19, further comprising a counter for counting the events of the same memory cell.

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22. An MCU having an embedded NVM comprising a processing unit; an array of memory cells, the memory cells of the array being individually capable of having a threshold voltage programmed or erased to an intended level within a range, the range being between range boundary levels ; a read circuit for reading the range of an actual threshold voltage of memory cells ; and an identifying circuit for identifying any memory cells having an intended level in at least one predefined range that each has it's actual threshold voltage shifted beyond a predetermined margin level within the range different from the range boundary levels.
23. A method for operating a non-volatile memory, wherein the nonvolatile memory comprises an array of memory cells, the memory cells of the array being individually capable of having a threshold voltage programmed or erased to an intended level within a range, the range being between range boundary levels ; a read circuit for reading the range of an actual threshold voltage of memory cells ; and an identifying circuit; the method comprising the steps: reading the range of an actual threshold voltage of memory cells ; and identifying any memory cells having an intended level in at least one predefined range that each has it's actual threshold voltage shifted beyond a predetermined margin level within the range different from the range boundary levels.
24. The method of claim 23, wherein the step of identifying comprises the sub-step applying an adjustable read potential during a read operation to at least one of bit lines of memory cells of the array.
25. The method of claim 23, the step of identifying comprising the substep performing a test read operation under test read conditions different from normal read conditions.

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26. The method of claim 23, wherein performing the test read operation comprises comparing the actual threshold voltage of a memory cell to a test voltage different from a discrimination voltage of normal read operations.
27. The method of claim 26, wherein analogous signals are compared.
28. The method of claim 26, comprising the step of comparing the signal of one memory cell in parallel to different test voltages to identify any memory cells having the actual threshold voltage shifted beyond one of several predetermined margins from its intended level.
29. The method of claim 26, wherein test read operations for several memory cells are performed in parallel.
30. The method of claim 26, wherein performing the test read operation comprises measuring the actual threshold voltage of memory cells
31. The method of claim 30, wherein performing the test read operation comprises comparing a measurement value to a stored value representing a test voltage different from a discrimination voltage of normal read operations.
32. The method of claim 30, wherein performing the test read operation comprises multiplexing actual threshold voltage of several memory cells.
33. The method of claim 23, wherein several memory cells are checked in parallel.
34. The method of claim 23, wherein performing the test read operation comprises performing a read operation on a memory cell with a test read access time shorter than normal read durations.
35. The method of claim 23, wherein the memory check mode is part of a startup mode of the non-volatile memory.
36. The method of claim 23, wherein the memory check mode is part of a power off mode of the non-volatile memory.
37. The method of claim 23, wherein the memory check mode is entered in time slots during normal operation of the non-volatile memory.

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38. The method of claim 23, the non-volatile memory having writing means for writing the threshold voltage to the intended level ; further comprising the step re-writing the threshold voltage to an intended level within the range.
39. The method of claim 23, the non-volatile memory having patching means for patching the identified cell.
40. The method of claim 23, comprising the additional step memorizing the address of an identified memory cell.
41. The method of claim 23, comprising the additional step defining an event of an identification of an identified memory cell.
42. The method of claim 23, comprising the additional step measuring means for measuring the time between two events of the same memory cell.
43. The method of claim 23, comprising the additional step counting the events of the same memory cell.
44. The method of claim 23, comprising the additional step entering a memory check mode of the non-volatile memory.
45. A method for operating an MCU having an embedded NVM comprising a processing unit; an array of memory cells, the memory cells of the array being individually capable of having a threshold voltage programmed or erased to an intended level within a range, the range being between range boundary levels ; a read circuit for reading the range of an actual threshold voltage of memory cells ; and an identifying circuit; the method comprising the steps: reading the range of an actual threshold voltage of memory cells ; and identifying any memory cells having an intended level in at least one predefined range that each has it's actual threshold voltage shifted beyond a predetermined margin level within the range different from the range boundary levels.
46. The method of claim 45, further comprising the step controlling the identifying circuit by the processing unit.