GB2372916A - Dynamic bus arbitration for shared bus architecture - Google Patents

Abstract

A dynamic bus arbiter (400, fig. 4) and method of dynamic bus arbitration (300) for a shared bus architecture in which a multiplicity of master devices may request control of the shared bus uses a modified "least recently used" priority assignment scheme. The priority of a master device (340) which is granted control of the bus is reduced to a minimum level, and the priority of all other master devices, including those which are inactive, is increased by a single unit.

Description

DYNAMIC BUS ARBITER, AND METHOD OF DYNAMIC BUS ARBITRATION, FOR SHARED BUS ARCHITECTURE Field of the Invention This invention relates to bus arbitration schemes for shared bus architectures in real-time environments (e. g., multiplexed multi-processor environments). Such techniques are required in applications where more than one device can become the master of a shared bus, and priority needs to be assigned to each potential master device. Such a technique may be beneficial in both embedded multi-processor and development board applications.

Background of the Invention In the field of this invention it is known that existing techniques for bus arbitration fall into 4 categories: 1. Static Priority Algorithm.

This type of arbiter typically uses a bridge circuit to perform bus arbitration (e. g. , Intel 82372). Each bus master is allocated a fixed priority level. This method is the simplest way to implement bus arbitration.

However, such a static priority algorithm often leads to non-optimal performance in a real-time environment, and considerable risk of bus locking by the master with the highest priority (since a real-time environment implies a

guaranteed delay/response time, in granting of the shared bus to a bus master requesting access). In addition in a fixed priority bus arbitration scheme, increasing the number of possible bus masters makes the response time less and less predictable. This has the effect of reducing flexibility in the end application.

2. Dynamic Rolling Priority based on Round Robin Technique.

Many examples of prior art exist, which use this technique (e. g., U. S. patent no. 5,274, 785 and U. S. patent no. 5,640, 519). This technique is based on the bus master priorities being organized sequentially. The current active bus master will receive the lowest priority at the end of the bus transaction.

Simultaneously, all other devices will change priority according to their relative position, with respect to the active bus master. The effect is often analogised to a rotating drum. The priority change decision is in no way based upon any previous history of accesses by the different bus masters.

However, statistically it is very difficult to predict the response time for granting of the bus to any given bus master. Hence this technique of Dynamic Rolling Priority based on Round Robin cannot be used for realtime systems.

3. Time-Based Rolling Priority Technique.

Many examples of prior art exist for this technique (e. g., U. S. 5,778, 200 & patent publication WO9719410).

This technique is based on"Aging Counters", which try to store the previous history of transactions on the shared bus, and dynamically update the priorities according to the accumulated statistics.

However, the Time-Based Rolling Priority Technique usually involves a complex implementation, in that it is necessary to always assign unique priority numbers to bus masters, even if the aging counters have the same values stored. The decision is time-based rather than being transaction based, which usually does not take into account bus throughput. Although the method offers quite predictable response time, this is at the cost of a much more complex implementation in silicon.

4. Dynamic Rolling Priority based on Least Recently Used (LRU) Technique.

This technique (e. g. , as shown in U. S. patent no.

4,953, 081 and European patent no. 0,374, 521) is essentially similar to the Round Robin method described above. With this technique, as with the Round Robin technique, the current active bus master will receive the lowest priority level at the end of the transaction. At the same time all other bus masters requesting bus access will then have their own priorities re-determined.

However, in the Dynamic Rolling Priority based on Least Recently Used (LRU) technique all inactive (non requesting) masters, will be maintained at the same priority level. Thus, because in this known technique the bus access statistical analysis does not take into account all the bus masters, the technique has the disadvantage that the overall throughput of the system is compromised.

A need therefore exists for dynamic bus arbitration for shared bus architecture wherein the abovementioned disadvantage (s) may be alleviated.

Statement of Invention In accordance with the present invention there is provided dynamic bus arbiter, and method of dynamic bus arbitration, for shared bus architecture as claimed in claim 1.

Brief Description of the Drawings One dynamic bus arbiter, and method of dynamic bus arbitration, for shared bus architecture incorporating the present invention will now be described, by way of example only, with reference to the accompanying drawing (s), in which:

FIG. 1 shows a flowchart illustrating an initialization algorithm used in the present invention; FIG. 2 shows a flowchart illustrating a priority resolution algorithm used in the present invention; FIG. 3 shows a schematic diagram of a next priority calculator used in the present invention; FIG. 4 shows a schematic diagram of a priority resolution scheme used in the present invention; FIG. 5 shows a schematic diagram of a priority calculation scheme used in the present invention; and FIG. 6 shows a schematic diagram of bus arbitration state machine illustrating the bus arbitration

scheme of the present invention.

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Description of Preferred Embodiment (s) Referring firstly to FIGS. 1-3, a dynamic bus arbiter (which will be described in more detail below) incorporating the present invention is based on a novel dynamic bus arbiter algorithm, which (for ease of explanation) falls into three parts: Initialization, Priority Resolution and Next Priority Calculation.

INITIALIZATION Referring now particularly to FIG. 1, the initialization sequence is performed only after a RESET, in order to set up the starting conditions. The initial bus master priority assignments are arbitrary, since the bus arbiter algorithm will find the correct priorities very quickly.

This procedure takes place using concurrent flows in just one clock cycle. The process (100) consists of a number of straightforward steps. Following RESET (step 110), Pi is assigned (130) to each bus master i. The rule (140) followed is that each bus master must have a unique assigned priority. The bus master number (i) can be assigned from zero to N-1, and is incremented by one on each pass through the procedure (120). The bus arbiter is

then ready to commence the next stage, i. e., Priority Resolution.

PRIORITY RESOLUTION Referring now particularly to FIG. 2, the priority resolution sequence (200) is used to find the number of the device that has the highest priority, and then grant the bus to that device. After starting (step 210) the priority resolution sequence, the first step (220) is basically to poll round looking for bus requests. This fills up a'bus array' (not shown) in memory with values bi (bO... bn-1). If bi = 1, then a bus master is making a

bus request ; if bi = 0, there is no request, in which case the algorithm keeps on looking for requests (step 240). On each pass through the procedure, the bus master i is incremented by one (step 230), within a preset range

(0 to n-1). If (at step 250) a variable PRi (initially set to-1) is less than Pi (the priority level of the bus master i), then it will be assigned to Pi (step 260).

This process has the effect of simply finding the maximum value. If PRi ends with the value-1, this indicates that no masters are requesting the bus (step 270), and the process begins again at step 220 to collect bus requests.

The end result is that the variable PRi has the priority of the device that will be granted the bus.

At this point access will be granted to the bus master represented by PRi (step 280), i. e. , the device requesting bus access with the highest priority, and the bus arbiter is then ready to commence the next stage, i. e., Next Priority Calculation. As previously stated, the process of priority resolution is extremely fast, requiring only one clock cycle given an already initialized arbitration algorithm.

NEXT PRIORITY CALCULATOR Referring now particularly to FIG. 3, the priority of the device that has just been granted the bus is now reduced to zero (E). At the same time the priority of all other bus masters will be increased by one, with the exception of those whose priority was already higher than that which was just granted the bus. Thus, the next priority calculator sequence (300) is based on a loop in which a variable i is incremented by 1 in a range from 0 to n-1 (step 310). If the priority (Pi) of the ith bus master is less than that (Pri) of the bus master just granted the bus (step 320), the priority of (Pi) of the ith bus master

is incremented by 1. Additionally, the priority bus master just granted the bus is set to 0 (step 340). The next priority calculation sequence 300 then waits until the end of the bus transaction (step 350) before returning to the start of bus arbitration at the Priority Resolution sequence of FIG. 2.

Thus, it will be understood that the above bus

arbitration process relies on a modified'Least Recently Used'method, in order to determine the bus master priorities.

It will be appreciated that several advantages may be derived from this modified'Least Recently Used'method: 1. The response time is predictable and is guaranteed.

2. Any kind of bus lock condition is prevented.

3. This self-adjusting algorithm will always adapt to offer the good access to those devices that require it (i. e. , each device will get more or less sufficient access to meet its requirements, without one particular device occupying the bus for longer than appropriate).

It will be understood that although, as mentioned above, the above bus arbitration process takes one clock cycle, this process occurs concurrently to the granting of the bus.

DYNAMIC BUS ARBITER IMPLEMENTATION.

The algorithm described in the previous section has been successfully implemented in a field programmable gate array (FPGA) and thoroughly tested in a real application.

This provided an efficient and cost-effective integrated circuit implementation which is described below.

PRIORITY RESOLUTION IMPLEMENTATION This part of the description explains how the priorities of the different bus masters are determined, how the priority chain is enabled and ends up with the selection of one unique bus master, requesting the bus to be granted.

Referring now to FIG. 4, the implementation of the Priority Resolver 400 consists of the following main blocks: * a register file 410 with N registers (where N = number of bus masters). The bit width of the register is given as K = log2 (N) (e. g. , for N = 8 bus masters, K = 3 bits. ) Bus master numbers are represented in BCD format, as will be explained in greater detail below; "N-l comparators (420), each having 2 inputs of K bits;

* N multiplexers, each N bits wide, with N requests (430).

A synchronous clock (CLK) signal is used for all the blocks. Synchronous write enable signal (ENA), used to

overwrite the register file, is an active high input, clocked on the rising edge. The registers are assigned addresses Rl up to RN, where RN corresponds to the highest priority. In effect the different system bus master priorities are assigned to these registers.

Following the granting of the bus to a particular bus master, all the priorities will be shifted up by 1. This is except in the case where a device with a lower priority has requested and is granted the bus. This approach provides a very simple and low cost method for the priority calculator.

The principle is illustrated by the example shown in Table 1.

Pri Transaction Transaction Transaction Level 1 2 3 7 H H G 6 G G E 5 E E F 4 D F A 3 F A C 2 A C B 1 C B D 0 B # D # H Table 1: Priority Resolution Example In this example, the arbitrary order represents the initial priority levels for the different bus masters. In transaction 1, bus masters H, G, & E are not requesting the bus, therefore bus master D is granted the bus and then has its priority reduced to the lowest position. In transaction 2, bus master H takes priority over all the others.

It will be understood that the guaranteed response time r, taken to grant the bus to a requesting bus master, satisfies the following relation to the individual transaction times T for the N bus masters.

A-I Response Time :-r < T (Transaction) < =t NEXT PRIORITY CALCULATOR IMPLEMENTATION The implementation of the Next Priority Calculator (500) consists of the following main blocks : 'N Priority Request Multiplexer files (510) ; 'N-1 Priority Comparators with N inputs. (N binary input comparators) (520) The principle of this block is that the multiplexers (510) are always attempting to commutate a request from the corresponding bus master having the equivalent priority. Regarding the Priority Comparator logic, RN is the highest priority, so this passes directly through. At each stage all other devices, excepting the former, must be a '0', in order for that device to be selected.

Therefore only one output from the Priority Comparator can be a'1'.

The priority comparator output is converted into HEX and this hexadecimal number becomes an input to the register file of the priority resolver. It is also used to physically select the bus.

Table 2 shows an illustration of how the bus arbitration algorithm works using rolling priorities.

Phase Priority Granted 0 1 2 3 Bus Init. - 3 1 0 2 1 1 1 3 0 2 2 0 0 1 3 2 3 2 2 0 1 3 Table 2: Next Priority Calculation Example In the left column, sequential numbers show the steps of the priority roller. From this example it is apparent that the current bus master is always pre-empted on the following cycle by an active device with a higher priority. However for the next cycle, the lowest priority will be assigned to this active bus master.

BUS ARBITRATION STATE MACHINE In order to control and monitor activity on the bus, a state machine as shown in FIG. 6 is used.

It will be understood that the state machine (600) may be in one of several states. The default condition is IDLE (610). The state machine collects all bus requests. When a bus request is received, the next stage is to grant (620) the bus to the device selected by the priority resolution block. This, in turn, enables the priority chain and resolves the unique bus master. The priority calculator is then enabled, to be ready for the next cycle.

The last state is the WAIT state (630) for the end of the current cycle. If the bus is not busy and there are no active bus requests, it reverts to the IDLE state (610).

If the bus is busy, it will remain polling in the WAIT state (630) until the bus is free. If the bus is free and there is at least one bus request, it jumps to the GRANT state (620). Optionally the IDLE state could be used on a development board in order to isolate the bus. However for System-on-Chip implementation it is possible to use 'Zero-Bus-Turnaround'technology or bus multiplexing, thus avoiding redundant clock cycles. The RESET state (640) is used to force the state machine into the IDLE state (610), for instance at start up.

It will be appreciated that the present invention is based on a modification of the known Dynamic Rolling Priority based on Least Recently Used (LRU) technique.

However, in the known technique all inactive (nonrequesting) masters will be maintained at the same priority level. This is significantly different from the present invention, where in this case all bus masters at a level below that of the current active master will have their priority level incremented by one. This is the case, whether these masters are requesting bus access or not. Thus the disadvantage of the standard LRU technique, that the bus access statistical analysis does not take into account all the bus masters (including inactive ones), is overcome in the present invention in such a way as to improve the overall statistics, and increase the throughput of the system.

It will be understood that the dynamic bus arbiter, and method of dynamic bus arbitration, for shared bus architecture described above provides the following advantages: 'Provides an easily scalable solution for multiple bus master architectures, adaptable to any number of bus masters.

* Provides a flexible implementation without sacrificing real-time performance, unlike the static priority algorithm.

* Provides a predictable time slot or response time guaranteed for devices needing to have access to the shared bus, as in the case of the best time-based rolling priority schemes using the'aging counters' method, but not with other techniques.

* Avoids any kind of bus lock condition from occurring.

* Highly efficient (low cost) implementation in silicon. (e. g., since it does not require counters).

* Provides concurrent priority resolution, since it is not necessary to use up additional clock cycles to perform this calculation.

* Preferred implementation has HEX (hexadecimal) format of bus master representation which significantly reduces number of triggers.

Claims (10)

1. Claims 1. A method for dynamic bus arbitration in a system in which a multiplicity of master devices may request control of shared bus, the method comprising re-assigning the priority of the master devices using a'last recently used'priority assignment scheme, characterized by the priority of a master device granted control of the bus being reduced and the priority of other master devices being increased.
2. 2. The method of claim 1 wherein the priority of the master device granted control of the bus is reduced to a minimum level, and the priority of all of the other master devices with priority no higher than that of the master device granted control of the bus is increased by a single unit.
3. 3. The method of claim 1 or 2 further comprising a step, before re-assigning priority of the master devices, of initializing priorities of the master devices.
4. 4. A dynamic bus arbiter for use in a system in which a multiplicity of master devices may request control of shared bus, the dynamic bus arbiter comprising: means for re-assigning the priority of the master devices using a'last recently used'priority assignment scheme, characterized by the priority of a master device granted control of the bus being reduced and the priority of other master devices being increased.
5. 5. The dynamic bus arbiter of claim 4 wherein the priority of the master device granted control of the bus is reduced to a minimum level, and the priority of all of the other master devices with priority no higher than that of the master device granted control of the bus is increased by a single unit.
6. 6. The dynamic bus arbiter of claim 4 or 5 further comprising means for, before re-assigning priority of the master devices, of initializing priorities of the master devices.
7. 7. The dynamic bus arbiter of claim 4,5 or 6 wherein the means for re-assigning priority of the master devices comprises: multiplexer means for receiving a signal representative . of a value identifying the bus master granted control of the bus, and comparator means for comparing outputs of the multiplexer means with the signal representative of a value identifying the bus master granted control of the bus.
8. 8. The dynamic bus arbiter of claim 7 further comprising: register means for holding assigned priorities of respective ones of the bus masters; and comparator means coupled to the register means for comparing the assigned priority values to determine a maximum priority value therefrom for granting control of the bus.
9. 9. A method for dynamic bus arbitration substantially as hereinbefore described with reference to the accompanying drawings.
10. 10. A dynamic bus arbiter substantially as hereinbefore described with reference to the accompanying drawings.