JPH07114496A - Shared memory control circuit - Google Patents

Abstract

PURPOSE:To allocate a memory using right with high efficiency by providing a memory use permission decision circuit which inputs a memory use request and a response signal and supplies the memory using right to a specific request origin when no memory use request in accordance with the response signal exists. CONSTITUTION:The memory use permission decision circuit 43 which inputs the output of a decoder 42 and the memory use requests 2r, 3r from the request origin is provided. The memory use permission decision circuit 43 generates new response signals 20a, 30a by detecting the superposition of two signals from the response signal 2a and the memory use requests 2r, 3r, and sets a period other than that of the response signals 20a, 30a as the response signal 10a. In this way, since more response time can be allocated to the request origin with a high memory use frequency with a simple constitution, memory working efficiency can be improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a shared memory control circuit used in a microcomputer device or the like.

[0002]

2. Description of the Related Art A conventional shared memory control circuit is shown in FIGS.
This will be described with reference to 10. FIG. 6 is a block diagram of a device such as a microcomputer that controls a conventional time-shared shared memory.

Reference numeral 1 is a request source (for example, a microprocessor) that generates a memory use request right, 2 and 3 are request sources having similar functions (for example, a transmission control circuit and a control circuit of an external storage device), and 4 is a request source 1 Shared memory control circuits 5 for arbitrating the memory use request rights 3 to 5 are memories. Here, three request sources will be described.

FIG. 7 is a block diagram of the shared memory control circuit 4. Reference numeral 41 is a counter, and 42 is a decoder. The output of the decoder 42 is response signals 1a to 3a to the request sources 1 to 3.
Becomes This timing is shown in FIG.

The operation when the memory use requests 1r and 3r are generated from the request sources 1 and 3 will be described with reference to FIG. The request source 1 is a right of use 1 in which the request source 1 may use the memory 4 in the overlapping portion of the own memory use request 1r and the response signal 1a.
p is generated, and the memory 4 is accessed in the period of 1p. Similarly, the request source 3 also generates a usage right 3p from the memory usage request 3r and the response signal 3a, and accesses the memory 4 during the period of 3p.

As another example of the shared memory control circuit, there is a request arbitration system shown in FIG. This is the shared memory control circuit 4
The memory use requests 1r to 3r of the respective request sources 1 to 3 are fetched into and the response signals 1a to 3a are generated in accordance with a predetermined priority order. The request sources 1 to 3 use the same as the usage rights 1p to 3p as they are. There is a daisy chain system as a typical circuit configuration.

[0007]

In the shared memory control circuit of the time division system shown in FIG. 6, time t shown in FIG.
_{Since 1} is assigned to the request source 2, even if the request source 1 or the request source 3 issues a memory use request, the memory 4 cannot be used during the period of time t ₁ . Therefore, the operation of the request source 1 or 3 is delayed, which is a factor of performance degradation.

Further, in the shared memory control circuit of the request arbitration system shown in FIG. 10, since the response signals 1a to 3a are generated at the time when the memory use requests 1r to 3r are generated, there is no blank as in the time division system. There is no performance degradation due to time,
The following problems arise due to the need to generate a response signal in response to a request generated at an arbitrary timing.

1 Since arbitration is required so that a specific request source does not monopolize a memory, the circuit configuration becomes complicated. 2 Since it is necessary to perform circuit verification for a request generated at an arbitrary timing, it is necessary to consider many combinations. In particular, when a gate array is used, the amount of test data increases, the verification time becomes longer, and the verification accuracy decreases. The object of the present invention is to efficiently use the memory usage right,
To obtain a shared memory control circuit that can be assigned.

[0010]

In order to achieve the above object, in the present invention, in response to a memory request from a plurality of request sources, a response signal generated at its own timing is assigned to the request source and the memory is used. In the shared memory control circuit for determining the right, the memory use request and the response signal are input, and when there is no memory use request corresponding to the response signal, the memory use permission is given to the specific request source. Provided is a shared memory control circuit having a decision circuit.

[0011]

In the circuit thus constructed, more response time can be allocated to a specific requester having a high memory usage frequency.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. Here, the request sources 1 to 3 shown in FIG.
It is assumed that the memory usage frequency of the request source 1 is higher than those of the other two.

In FIG. 1, in addition to the configuration described with reference to FIG. 7, a memory use permission decision circuit 43 for inputting the output of the decoder 42 and the memory use requests 2r, 3r from the request sources 2, 3 is provided.

The operation of the embodiment will be described with reference to FIGS. The memory use permission decision circuit 43, as shown in FIG.
A new response signal is detected from the response signal 2a and the memory use request 2r, and 3a and 3r when the two signals overlap.
20a and 30a are generated, and the period other than 20a and 30a is set to 10a.

Now, as in FIG. 9 of the prior art, request sources 1 and 3
Consider the operation when the memory use requests 1r and 3r are generated. The response signals 10a to 30a at this time are as shown in FIG. 3, and the response signal when there is no memory use request 2r (period of t ₁ ) is the response signal to the request source 1 having a high memory use frequency.
It is assigned to 10a. The memory usage right at this time is
As shown in FIG. 4, since the request source 1 uses the memory 4 by the memory usage right 1p during the period of t ₁ and the blank time is eliminated, the memory usage efficiency is improved.

FIG. 5 is a circuit configuration example of the memory use permission decision circuit 43. Since the request sources 2 and 3 are permitted to access the memory at a fixed time based on the response signals 2a and 3a, there is no asynchronous factor such as the arbitration method shown in FIG. Therefore, it is not necessary to consider various combinations for circuit verification.

[0017]

As described above, according to the present invention, a large amount of response time can be allocated to a requester having a high memory usage frequency with a simple circuit configuration, so that the memory usage efficiency can be improved.

[Brief description of drawings]

FIG. 1 is a block configuration diagram of an embodiment of a shared memory control circuit of the present invention.

FIG. 2 is a timing chart illustrating the operation of the embodiment.

FIG. 3 is a timing chart illustrating the operation of the embodiment.

FIG. 4 is a timing chart illustrating the operation of the embodiment.

FIG. 5 is a configuration diagram of a memory use permission decision circuit according to an embodiment.

FIG. 6 is a block configuration diagram of a microcomputer or the like including a conventional shared memory control circuit.

FIG. 7 is a block configuration diagram of a conventional shared memory control circuit.

FIG. 8 is a timing chart illustrating an operation of a conventional shared memory circuit.

FIG. 9 is a timing chart for explaining the operation of the conventional shared memory circuit.

FIG. 10 is a block diagram of a microcomputer or the like including a conventional shared memory control circuit.

[Explanation of symbols]

1, 2, 3 ... Request source, 4 ... Shared memory control circuit, 5 ... Memory, 41 ... Counter, 42 ... Decoder, 43 ... Memory use permission decision circuit, 1a to 3a ... Response signal, 1p to 3p ... Use right ( Signal), 1r to 3r ... memory use request (signal), 10
a to 30a ... Response signal.

Claims (1)

[Claims] 1. A memory request from a plurality of request sources,
In a shared memory control circuit that allocates a response signal generated at its own timing to the request source and determines a memory use right, inputs the memory use request and the response signal,
A shared memory control circuit comprising a memory use permission decision circuit which gives a memory use right to a specific request source when there is no memory use request corresponding to the response signal.