GB2340686A

GB2340686A - A bidirectional open-drain bus driver in a television receiver

Info

Publication number: GB2340686A
Application number: GB9917194A
Authority: GB
Inventors: Andrew Benford
Original assignee: Mitel Semiconductor Ltd
Current assignee: Microsemi Semiconductor Ltd
Priority date: 1998-08-07
Filing date: 1999-07-23
Publication date: 2000-02-23
Also published as: FR2782179A1; GB9817193D0; JP2000115209A; GB9917194D0; DE19937259A1

Abstract

Reverse data transmission in a bidirectional open-drain bus driver is inhibited by use of clocked multiplexers 23,24 which direct a non-asserted high logic input 35,27 to one of the drivers 42,44 when the other driver is active. The OR gates 50,52 prevent lock-up by inhibiting both drivers when the buses 16 and 17 are both being pulled low by external devices. The bus 16 may be a microprocessor controlled bus in a television receiver, and the branch bus 17 may be coupled to a tuner. The buses may be isolated by a control signal 22 from a register (19,figure1) which is loaded under microprocessor control. The register may acknowledge commands from the microprocessor via the line 21. The technique may be applied to wired-AND and wired-OR buses.

Description

2340686 CIRCUITS FOR PROVIDING BI-DIRECTIONAL COMMUNICATION, BUS SYSTEM

AND TELEVISION RECEIVER The present invention relates to circuits for providing bi-directional data communication and in particular, although not exclusively, to circuits for providing bi-directional data communication between primary and secondary buses of a wired-AND bus system. The present invention also relates to bus systems and television receivers.

Data communication between devices of a television receiver is commonly effected with the use of a bus. Tens of devices may be connected to a common bus, with each device having a unique address to distinguish it from other devices connected to the bus. One type of bus system utilises a clock line and a single data line. Although the clock line is unidirectional, the data line is required to carry working data and address data in both directions and can therefore be described as bidirectional. The data line is permanently connected to a supply potential by a pull up resistor and is selectively connected to ground potential by a transistor pull-down circuit arrangement present in each device. Control of the pull-down arrangement of any one of the devices to pulldown the data line causes the whole of the data line to be grounded. For this reason, bus systems of this type are commonly referred to as wired-AND bus systems.

It is becoming more common to connect to buses devices which only seldom cornmunicate with other devices on the bus. In the interest of power conservation and reduced bus line capacitance, such secondary devices are often connected onto a secondary bus which is then selectively connected to the primary bus, as the first referred to bus is known, by an addressable device which is a slave to the microprocessor device controlling communication on the bus. Where the secondary device is a tuner or the like, isolation from the primary bus is further desirable as it removes a source of noise from the area of the chip on which the tuner is placed. Selectable isolation of lines of the primary bus from the associated lines of the secondary bus is usually carried out by transistors connected in an analogue transmission gate arrangement. Such arrangements are satisfactory for most bus connections but are not, susceptible for inclusion into digital cell libraries, which is a 2 highly sought after feature of modem bus devices, and have to be redesigned for operation at a different bus voltage.

WO 93/09503 discloses a circuit for providing bi-directional data communication. This circuit uses two multiplexors which are effectively connected in opposite directions between first and second buses. The output of each multiplexor is fed to one of the inputs of the other multiplexor and the multiplexor switching arrangements are controlled by control signals derived elsewhere in the circuit.

According to a first aspect of the invention, there is provided a circuit for providing bidirectional data communication between a first bus line and a second bus line, comprising first and second multiplexors each having first and second inputs, a switching input and an output, the first inputs of the first and second multiplexors being respectively connected to the first and second bus lines, the second inputs of the first and second multiplexors being connected to a predetermined logic state source, the output of the first multiplexor being connected to a first node, the first node being connected to a second bus line by a first pull-down or pull-up device and to the second multiplexor switching input, and the output of the second multiplexor being connected to a second node, the second node being connected to the first bus line by a second pulldown or pull-up device and to the first multiplexor switching input.

The circuit may comprise first and second clocked buffers connected between respective ones of the first and second multiplexor outputs and the first and second nodes. Each of the first and second clocked buffers may comprise a D-type flip-flop.

The circuit may comprise: first and second logic devices connected to the outputs of the first and second multiplexors, respectively, each logic device having a logic device output and a logic device inverted output; and first and second OR gates each having first and second inputs and an output, in which the first OR gate first input is connected to the second logic device output, the first OR gate second input is connected to the first logic device inverted output, the first OR gate output is connected to the second node, the second OR gate first input is connected to the first logic device output, the second 3 OR gate second input is connected to the second logic device inverted output, and the second OR gate output is connected to the first node. The first and second logic devices may be clocked buffers. The clocked buffers may comprise D-type flip-flops.

The first and second D-type flip-flops may be arranged to provide signals on their output or outputs in response to a clock signal response received at clock inputs thereof Each of the first and second D-type flip-flops may further comprise a control input, by which the circuit can be enabled or disabled.

The circuit may comprise an AND gate having a first input connected to the second node, an output connected to the first bus line and a second input connected to a data source.

The first and second inputs of the first and second multiplexors may be connected to the first and second bus lines by first and second nonclocked buffers, respectively. Each of the first and second non-clocked buffers may comprise a Schmitt trigger.

According to a second aspect of the invention, there is provided a bus system having a circuit in accordance with the first aspect of the invention.

The bus system may be a wired-AND or wired-OR bus system.

According to a third aspect of the invention, there is provided a television receiver having a bus system according to the second aspect of the invention.

Embodiments of the present invention will now be described by way of example only with reference to the accompanying drawings in which:

Figure I shows schematically a wired-AND bus system in a television receiver incorporating a circuit in accordance with the present invention; 4 Figure 2 shows in detail part of the Figure 1 circuit; Figure 3 shows a modified version of the Figure 2 circuit; and Figure 4- shows a modified version of the Figure 2 circuit for a wired-OR bus system.

Referring to Figure 1, a television receiver I has a primary bus 10 connected to a secondary bus I I by a device 12. The primary bus comprises a clock line 13 and a data line 14, which correspond to a clock line 15 and a data line 16 of the secondary bus 11. Connection of the device 12 to the primary bus 10 is made by a device data input line 17, hereinafter referred to as the first bus line 17, and a device clock input line 18. The first bus line 17 and the device input clock line 18 are connected to each of a device register bank 19 and a connection/isolation circuit 20. The device register bank 19 acts as a slave to a microprocessor (not shown), which is connected on the primary bus 10. The device register bank 19 is accessed by transmission by the microprocessor of its unique address on the primary bus data line 14. The connections between the lines of the primary bus 10 and the device register bank are uni-directional. The device register bank 19 is able to provide data signals back to the primary bus data line 14 by way of a data line 21 into the connection/isolation circuit 20. A uni-directional set or control line 22 is also provided between the device register bank 19 and the connection/isolation circuit 20.

In use, the microprocessor is able to access a device connected to the secondary bus 11, hereinafter referred to as the secondary device, by addressing the device register bank 19 on the primary bus data line 14. The device register bank 19, on detection of its address, transmits acknowledgement data to the microprocessor by way of the data line 21, the first bus line 17 and the primary bus data line 14. The device register bank 19 then enables the connection/isolation circuit 20 to allow data from the microprocessor to travel from the primary bus data line 14 through the first bus line 18 onto the secondary bus data line, hereinafter referred to as the second bus line 16, where it can be received by the secondary device.

The device register bank 19 also allows the clock signal from the primary bus clock line 13 to appear on the secondary bus clock line 15, for use by the secondary device.

The secondary device will usually then acknowledge that the data has been received by transmitting acknowledgement signals on the second bus line 16 through the connection/isolation circuit 20 and the first bus line 18 to the primary bus data line 14. Further data may be transmitted by the secondary device to the primary bus data line 14 in this way if desired.

The connection/isolation circuit 20 will now be described with reference to Figure 2.

In Figure 2, first and second logic devices 23 and 24 are connected to provide bidirectional data communication between the first bus line 17 and the second bus line 16, which are provided with pull-up resistors RI and R2, respectively. The first logic device 23 comprises a multiplexor (WX) 25 having first and second inputs 26 and 27, a switching input 28 and an output 29, and a clocked buffer in the form of a D-type flipflop (D-FF) 25A having a clock input 30, a signal input 3 1, a set input 32 and an output 33. Ile clock inputs of the D-type flip-flops are connected to a high frequency on-chip clock 47. The second logic device 24 also comprises a multiplexor 24A and D-type flip-flop 24B. As the logic devices 23 and 24 are the same, only the operation of the logic device 23 needs to be described for operation of the connection/isolation circuit 20 to be understood.

The logic device 23 is enabled only when the control signal on the control line 22 from the device register bank 19 is high. The multiplexor 25 passes to the D-type flip-flop input 31 the signal present at the first input 26 when the signal applied to the switching input 28 is high and a logic one ("I") signal applied permanently by a predetermined logic state source (in the form of a power supply line vcc) to the second input 27 when the signal applied to the switching input 28 is low. The D-type flip-flop 25A operates as follows. When the signal present on the control line 22 is low, a logic one signal is driven onto the output 33. This signal is maintained on the output 33 until the first rising edge of the clock signal from the clock 47 following the control signal going 6 high, when the output signal becomes dependent on signals present at the input 3 1. For as long as the set signal on the line 22 is high, the signal present at the input 31 just before the rising edge of the clock signal is clocked through to and held on the logic device output 33 by the rising edge. The inputs 34 to 38 and the output 39 of the second logic device 24 correspond to the inputs 26 to 28, 30 and 32 and the output 33, respectively, of the first logic device 23.

The first bus line 17 is connected to the first multiplexor first input 26 by a first nonclocked buffer 40, such as a Schmitt trigger. The second bus line 16 is connected to the second multiplexor first input 34 by a second non-clocked buffer 41, such as a Schmitt trigger. The first multiplexor output 33 is connected to a node NI which is connected both to the second multiplexor switching input 36 and, by a first open drain circuit 42, to the second bus line 16. The second logic device output 30 is connected to a second node N2 which is connected both to the first multiplexor switching input 28 and, by a first input of a first AN.D gate 43 and a second open drain circuit 44, to the first bus line 17. The open drain circuits 42 and 44 each comprise an inverter 42A, 44A and a field effect transistor 42B, 44B arranged so that a logic zero input signal causes the output to be pulled down to ground and a logic one input signal causes the output to go tri-state, that is causes the output to show a high impedance. Any signal present at the open drain circuit output thus remains unchanged when anything other than a logic zero is applied to the open drain circuit input. Also, signals present at the open drain circuit output do not affect the open drain circuit input. The open drain circuits 42 and 44 can thus each be described as a pull-down device, another example of which is an open collector circuit. The name pull-down stems from the fact that they pull the voltage on a line to or near to a predetermined voltage. The first multiplexor second input 27 and the second multiplexor second input 35 are each connected permanently to the predetermined logic state source, here being a logic one signal source. The first AND gate 42, as well as having its first input connected to the second multiplexor output 39, has a second input connected to the data line 21 to receive data signals from the device register bank.

7 A second AND gate 45 is connected to allow clock signals from the primary bus clock line 13 onto the secondary bus clock line 15 only when a logic one signal is provided by the data register bank 19 on the control line 22. This helps to reduce the amount of noise in the area of the chip around the secondary device when connection between the primary and secondary buses 10 and I I is not needed.

The logic one signals which are provided on the first and second logic device outputs 33 and 39 for the first clock period of the clock 47 following the set signal applied to the inputs 32 and 38 going high are fed through to the respective one of the second multiplexor switching input 36 and the first multiplexor switching input 28. Thus, an initial state is set up where the outputs 33 and 39 are at a logic one, regardless of the state of the first and second bus lines 17 and 16. The communication of data, either from the first bus line 17 to the second bus line 16 or from the second bus line 16 to the first bus line 17, can be made at any time after this first clock pulse following the control signal on the control line 22 going high, as will now be described.

If the primary bus data line 14 is pulled down by the microprocessor so that the first bit line 17 shows a logic zero, a logic zero will be passed from the first multiplexor first input 26, because the signal present at the first multiplexor switching input 28 is high, to the first logic device output 33. This is then passed to the node NI which is connected both to the second multiplexor switching input 36 and to the open drain circuit 42. The presence of a logic zero at the second multiplexor switching input 36 causes the logic one signal from the second multiplexor second input 35 to be passed to the second logic device output 39. The open drain circuit 42 then pulls down the second bus line 16 to logic zero, thereby communicating the logic zero signal to the second bus line 16. This logic zero signal is then fed back by the buffer 41 to the second multiplexor first input 34 but, because the second multiplexor switching input 36 is at a logic zero, the second multiplexor output 39 is maintained at a logic one. This does not affect the first bus line 17 because the output of the open drain circuit is tri- state.

When the logic signal on the first bus line 17 goes high, it is seen at the first multiplexor first input 26 through the first buffer 40 which, because the signal present at the first 8 multiplexor switching input 28 is still high, is clocked through to the first logic device output 33. This logic one signal is then passed -to the node NI and from there to the second multiplexor switching input 36 and to the first open drain circuit 42. The connection/isolation bus 20 thus resumes its initial state, with each of the first bus line 17 and the second bus line 16 showing a logic one.

Data communication from the second bus line 16 to the first bus line is effected as follows.

When the second bus line 16 is pulled down to a logic zero by the secondary device, a logic zero is seen at the second multiplexor first input 34, via the second buffer 41, and is clocked through to the second logic device output 39 at the next rising edge of the clock signal. A logic zero signal is thus provided to node N2 and from there to the first multiplexor switching input 28 and, through the first AND gate 43 and the open drain circuit 44, to the first bus line 17. The appearance of the logic zero signal at the first multiplexor switching input 28 causes the logic one signal present at the first multiplexor second input 27 to be clocked through to the first logic device output 33. A logic one signal is thus applied to the node N1 and from there to the second multiplexor switching input 36 and to the input of the open drain circuit 42. As the open drain circuit 42 does not pull-down the second bus line 16 to logic zero, the logic zero signal present on the second bus line 16 remains unchanged.

When the second bus line 16 is made to go high by the secondary device, a logic one is seen at the second multiplexor first input 34 through the second buffer 41 which, because the signal present at the second multiplexor switching input 36 is still high, is clocked through to the second logic device output 39. This logic one is then passed to the node N2 and from there to the first multiplexor switching input 28 and to the second open drain circuit 44. The initial state is thus resumed, with each of the first and second bus lines 17 and 16 showing a logic one.

As the open drain circuit is responsive to logic zero signals on its input, it is necessary to arrange for the data line 21 to be held at logic one whilst data is being communicated I 9 between the second bus line 16 and the first bus line 17. Similarly, it is necessary to arrange for the second logic device output 38 to be held at logic one whilst data is communicated from the device data register 19 to be the first bus line 17.

In bus systems where it can be guaranteed that both of the first bus line 17 and the second bus line 16 will not be pulled-down to logic zero at the same time, the Figure 2 connection/isolation circuit 20 will be able to handle any sequences or combinations of data without ever entering a frozen or locked up state. However, where this is not guaranteeable, the presence of logic zero signals on both of the first bus line 17 and the second bus line 16 will cause the open drain circuits 42 and 44 to lock up or freeze the circuit 20 such that it will have to be reset by applying a suitable signal to the control line 22. The modified connection/isolation circuit 20 of Figure 3 seeks to overcome this problem.

Figure 3 shows a modification of the Figure 2 connection/isolation circuit 20. Items which are the same as those of the Figure 2 device are shown having the same reference numerals. A first OR gate 50 has a first input connected to the second logic device output 39 and a second input connected to a first logic device inverted output 51. The first OR gate output is connected to the second node N2 as in Figure 2. A second OR gate 52 is connected to have its first input connected to the first logic device output 33 and its second input connected to a second logic device inverted output 53. The second OR gate output is connected to the second node N2 as in Figure 2.

The signals provided on the first logic device inverted output 51 and the second logic device inverted output 53 are of the opposite type to the signals provided on the first logic device output 33 and the second logic device output 39, respectively. If a logic zero signal is applied to both of the first bus line 17 and the second bus line 16 at the same time, a logic zero will be clocked onto both the first logic device output 33 and the second logic device output 39, on the rising edge of the next clock signal. However, as both the first logic device inverted output 51 and the second logic device inverted output 53 will provide a logic one, the OR gate 50 and the OR gate 52 will provide a logic one signal to the second multiplexor switching input 36 and the first multiplexor switching input 28, respectively. The open drain circuits 42 and 44 will thus each provide a high impedance output, and the connection/isolation circuit 20 will not become frozen or locked up. Application of a logic one signal to either of the first bus line 17 and the second bus line 16 will then cause normal operation to be resumed.

If operation in a bus system where bus lines are permanently pulled down to ground and devices connected to the bus comprise means selectively to pull the bus line high is desired, some modification to the Figures 2 and 3 circuits will be required. Figure 4 illustrates a modified version of the circuit of Figure 2 for such operation. The predetermined logic state source provides permanently a logic zero ("0") signal to the multiplexor inputs 27 and 35 by a connection to ground gnd. The pull-down devices 42 and 44 are replaced by pull-up devices responsive only to logic one signals on their respective input to pull their respective outputs to a logic one. This can easily be achieved by using transistors 42B, 44B of opposite conductivity type. The resistors R1 and R2 are connected as pulldown resistors. The switching inputs 28 and 36 are inverted and the inputs 32 and 38 are reset inputs.

Claims

CLAIMS:

1. A circuit for providing bi-directional data communication between a first bus line and second bus line, comprising first and second multiplexors each having first and second inputs, a switching input and an output, the first inputs of the first and second multiplexors being respectively connected to the first and second bus lines, the second inputs of the first and second multiplexors being connected to a predetermined logic state source, the output of the first multiplexor being connected to a first node, the first node being connected to the second bus line by a first pull-down or pull-up device and to the second multiplexor switching input, and the output of the second multiplexor being connected to a second node, the second node being connected to the first bus line by a second pull.-down or pull-up device and to the first multiplexor switching input.

2. A circuit as claimed in claim 1, comprising first and second clocked buffers connected between respective ones of the first and second multiplexor outputs and the first and second nodes.

3. A circuit as claimed in claim 2, in which each of the first and second clocked buffers comprises a D-type flip-flop.

4. A circuit as claimed in claim 1, comprising: first and second logic devices connected to the outputs of the first and second multiplexors, respectively, each logic device having a logic device output and a logic device inverted output; and first and second OR gates each having first and second inputs and an output, in which the first OR gate first input is connected to the second logic device output, the first OR gate second input is connected to the first logic device inverted output, the first OR gate output is connected to the second node, the second OR gate first input is connected to the first logic device output, the second OR gate second input is connected to the second logic device inverted output, and the second OR gate output is connected to the first node.

12

5. A circuit as claimed in claim 4, in which the first and second logic devices are clocked buffers.

6. A circuit as claimed in claim 5, in which the clocked buffers comprise D-type flip-flops.

7. A circuit as claimed in claim 3 or 6, in which the first and second Dtype flipflops are arranged to provide signals on their output or outputs in response to a clock signal received at clock inputs thereof

8. A circuit as claimed in claim 3, 6 or 7, in which each of the first and second Dtype flip-flops further comprises a control input, by which the circuit can be enabled and disabled.

9. A circuit as claimed in any preceding claim, comprising an AND gate having a first input connected to the second node, an output connected to the first bus line and a second input connected to a data source.

10. A circuit as claimed in any one of the preceding claims, in which the first inputs of the first and second multiplexors are connected to the first and second bus lines by first and second non-clocked buffers, respectively.

11. A circuit as claimed in claim 10, in which each of the first and second nonclocked buffers comprises a Schmitt trigger.

12. A bus system having a circuit as claimed in any preceding claim.

13. A bus system as claimed in claim 12, in which the bus system is a wired-AND or wired-OR bus system.

14. A television receiver having a bus system as claimed in claim 12 or claim 13.