GB2127652A - Bidirectional in-line signal compensation circuit - Google Patents
Bidirectional in-line signal compensation circuit Download PDFInfo
- Publication number
- GB2127652A GB2127652A GB08320193A GB8320193A GB2127652A GB 2127652 A GB2127652 A GB 2127652A GB 08320193 A GB08320193 A GB 08320193A GB 8320193 A GB8320193 A GB 8320193A GB 2127652 A GB2127652 A GB 2127652A
- Authority
- GB
- United Kingdom
- Prior art keywords
- amplifying circuit
- data signal
- transistor
- terminal station
- terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L5/00—Arrangements affording multiple use of the transmission path
- H04L5/14—Two-way operation using the same type of signal, i.e. duplex
- H04L5/1461—Suppression of signals in the return path, i.e. bidirectional control circuits
Description
1 GB 2 127 652 A 1
SPECIFICATION
Signal level compensation in an in-line data 65 communication system Background and summary of the invention
The present invention relates to an in-line data communication system, wherein terminal stations are connected to each other via a bidirectional communication cable.
In such an in-line data communication system, signal attenuation creates a serious problem when a long communication cable is used to connect long-distanced terminal stations. The signal attenuation is mainly caused by the impedance of the communication cable. To reduce the signal attenuation, one approach of the conventional system is to employ a communication cable of low impedance. Such a communication cable makes the system expensive. Another approach in the conventional system is to employ two communication cables, one for data transmission and the other for data reception. Amplifying circuits are connected to the transmission cable and the reception cable, respectively. This complicates the construction of the data communication system.
Accordingly, an object of the present invention is to provide an in-line data communication 90 system which ensures accurate data communication.
Another object of the present invention is to provide a signal level compensation system disposed in a bidirectional communication cable 95 which connects terminal stations.
Other objects and further scope of applicability of the present invention will become apparent from the detailed description given hereinafter. It should be understood, however, 100 that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.
To achieve the above objects, pursuant to an embodiment of the present invention, a bidirectional communication cable (coaxial cable) 110 is employed to connect terminal stations with each other. A signal level compensation circuit is disposed between the terminal stations and is connected to the bidirectional communication cable. The signal level compensation circuit includes first and second amplifying circuits. The first amplifying circuit is enabled and the second amplifying circuit is disabled when a data signal is transmitted in one direction within the bidirectional communication cable, thereby 120 compensating for the signal attenuation in one direction. The first amplifying circuit is disabled and the second amplifying circuit is enabled when the data signal is transmitted in the opposing direction within the bidirection cable, thereby compensating for the signal attenuation in the opposing direction. The first and second amplifying circuits are disposed in the signal level compensation circuit in a parallel fashion with each other so that the signal level compensation circuit has a pair of terminals connected to the bidirectional communication cable.
Brief description of the drawings
The present invention will be better understood from the detailed description given hereinbelow and the accompanying drawings which are given by way of illustration only, and thus are not limitative of the present invention and wherein:
Figure 1 is a schematic block diagram of a conventional data communication system; Figure 2 is a schematic block diagram of an embodiment of a data communication system of the present invention; Figure 3 is a circuit diagram of a signal level compensation circuit of the present invention included in the data communication system of Figure 2; and Figure 4 is a time chart for explaining an operational mode of the signal level compensation circuit of Figure 3.
Description of the preferred embodiments
Figure 1 shows a general construction of the conventional data communication system. The data communication system generally includes a plurality of terminals 11, 12, - - -, and 1 n.
Interfaces 21, 22, - - -, and 2n are connected to each of the terminal stations 11, 12, - - -, and 1 n.
The interfaces 21, 22, - - -, and 2n are connected to each other via a communication cable 3 such as a coaxial cable.
An example of the above-mentioned data communication system is disclosed in U.S. Patent 4,063,220, "Multipoint Data Communication System With Collision Detection-, issued on December 13,1977, and U.S. Patent 4,099,024, "Communications Network Repeater-, issued on July 4,1978.
In such a system, attention should be directed to the fact that the impedance of the communication cable 3 becomes large as the communication cable 3 becomes long. That is, the data signal transmitted in the communication cable 3 considerably attenuates when the terminal stations are spaced apart from each other by a long distance. The attenuation of the data signal may cause an erroneous data transmission.
The present invention is to provide a data communication system which ensures an accurate data transmission even when the terminal stations are long distanced from each other.
Figure 2 shows an embodiment of a data communication system of the present invention. The data communication system of the present invention includes a plurality of terminal stations 41, 42, - - -, and 4n such as electronic cash registers. Each of the terminal stations 41, 42, and 4n includes a main body 41 b, 42b, - - -, or 2 GB 2 127 652 A 2 4nb, and an interface 41 a, 42a, - - -, or 4na. The terminal stations 41, 42, - - -, and 4n are connected to each other via a communication cable 5 such as a coaxial cable.
Between the terminal stations 41 and 42, a signal level compensation circuit 61 is connected to the communication cable 5. Between the terminal stations 42 and 43, a signal level compensation circuit 62 is connected to the communication cable 5. Between the terminal stations 4(n-1) and 4n, a signal level compensation circuit 6(n-1) is connected to the communication cable 5. Each of the signal level compensation circuits 61, 62, - - -, and 6(n-1) includes a first amplifying circuit 61 a, 62a, - - -, or 6(n-1)a, and a second amplifying circuit 61 b, 62b, - - -, or 6(n-1)b.
Since the signal level compensation circuits 61, 62, - - -, and 6(n-1) have the same constructions, the following explanation will be limited to the signal level compensation circuit 61 for the purpose of simplicity. As already discussed above, the signal level compensation circuit 61 includes the first amplifying circuit 61 a and the second amplifying circuit 61 b. The first amplifying circuit 61 a and the second amplifying circuit 61 b are connected, in the signal level compensation circuit 6, to each other in a parallel fashion. The first and second amplifying circuits 61 a and 61 b have the opposing signal transfer directions to each other. More specifically, the first amplifying circuit 61 a is enabled when the data signal is transmitted in the bidirectional communication cable 5 in one direction shown by an arrow A in Figure 2. At this moment, the second amplifying circuit 61 b is disabled so as not to perform its operation. Contrarily, when the data signal is transmitted in the bidirectional communication cable 5 in the opposing direction as shown by an arrow B, the second amplifying circuit 61 b is enabled, and the first amplifying circuit 6 1 a is disabled.
Figure 3 shows an embodiment of the signal level compensation circuit 61. As already discussed above, the signal level compensation circuits 62, - -, and 6(n-1) have the same construction as the signal level compensation circuit 6 1. The signal level compensation circuit 61 includes the first amplifying circuit 61 a and the second amplifying circuit 61 b. The first amplifying circuit 61 a is connected between a first terminal 7 1, which is connected to the terminal station 41 via the bidirectional ' communication cable 5, and a second terminal 72, which is connected to the terminal station 42 120 via the bidirectional communication cable 5. The second amplifying circuit 61 b is connected between the first terminal 71 and the second terminal 72. That is, the first amplifying circuit 61 a and the second amplifying circuit 61 b are connected to each other in the parallel fashion within the signal level compensation circuit 6 1.
The first amplifying circuit 61 a includes first through fourth transistors TR1, TR2, TR3 and TR4.
The base of the first transistor TR1 isconnectedto the first terminal 71 via a resistor R l. The collector of the first transistor TR1 is connected to the base of the second transistor TR2 via a resistor R2. The emitter of the first transistor TR1 is connected to the emitter of the second transistor TR2. The collector of the second transistor TR2 is connected to the base of the third transistor TR3. The emitter of the second transitor TR2 is grounded via a resistor R3. The emitter of the third transistor TR3 is connected to the base of the fourth transistor TR4 via a resistor R4. The emitter of the third transistor TR3 is further connected to the second terminal 72 via a first diode D 1. The collector of the fourth transistor TR4 is connected to the collector of the first transistor TR 1 via a second diode D2 and a third diode D3. The emitter of the fourth transistor TR4 is grounded. The collectors of the first and second transistors TR 1 and TR2 are connected to a first power supply terminal B1 via resistors R5 and R6, respectively. The collector of the third transistor TR3 is connected to a second power supply terminal B2 via a resistor R7. A resistor R8 is connected between the base and the emitter of the fourth transistor TR4.
The second amplifying circuit 61 b has the same construction as the first amplifying circuit 61 a, but is constructed in the reverse direction. An apostrophe C) is added to each element in the second amplifying circuit 61 b in order to identify the relationship between the elements in the first amplifying circuit 61 a. The node provided between the second and third diodes D2 and D3 is connected to a node provided between a resistor R 1' and the base of a first transistor TRV of the second amplifying circuit 61 b. A node provided between second and third diodes D2' and DX of the second amplifying circuit 61 b is connected to the node formed between the resistor R 'I and the base of the first transistor TR1. Resistors R9 and R1 0 are provided for impedance matching purposes. The first power supply terminal B1 and the second power supply terminal B2 in the second amplifying circuit 61 b are the same terminals as the first power supply terminal B 1 and the second power supply terminal B2 of the first amplifying circuit 61 a, respectively.
An operational mode of the signal level compensation circuit 61 will be described with reference to Figure 4. Now assume that a data signal is transmitted from the terminal station 41 to the signal level compensation circuit 61 via the bidirectional communication cable 5 in the direction shown by an arrow A.
A data signal as shown in Figure 4-0) is applied to the first amplifying circuit 61 a via the first terminal 71 at a time fl. Even though the signal level is attenuated, the data signal takes a level, at a time t2, sufficient to turn on the first transistor TR 1. Accordingly, the collector voltage of the first transistor TR1 bears the logic low at a time t2 as shown in Figure 4-(2). In response to the switching operation of the first transistor TR1, the second transistor TR2 is turned off at a time 1 3 GB 2 127 652 A 3 t3 with a time delay determined by the turn-on time period of the transistor. That is, the collector voltage of the second transistor TR2 bears the logic high at a time t3 as shown in Figure 4-0. In response to the switching operation of the second transistor TR2, with a time delay determined by the turn-on time period of the transistor, the third transistor TR3 turns on at a time t4. Therefore, the emitter voltage of the third transistor TR3 bears the logic high at a time t4 as shown in Figure 4-(4). The thus obtained emitter voltage of the third transistor TR3 is a data signal which is amplified and shaped from the data signal applied to the first terminal 7 1. The emitter voltage of the third transistor TR3 is applied to the second terminal 72 via the first diode D 1, thereby being transferred to the terminal station 42 via the bidirectional communication cable 5. Figure 4-M shows the data signal developed from the second terminal 72.
Since the bidirectional communication cable 5 is employed, the data signal may cycles between the first and second amplifying circuits 61 a and 61 b if the second amplifying circuit 61 b is not disabled. That is, the second amplifying circuit 61 b must be disabled before the data signal is developed at the emitter of the third transistor TR3.
In accordance with the signal level compensation circuit 61 of Figure 3, the collector 95 voltage of the first transistor TR1 is applied to the base of the first transistor TRIl' of the second amplifying circuit 61 b via the third diode D3.
Thus, when the collector voltage of the first transistor TR1 bears the logic low at the time t2, 100 the base voltage of the first transistor TRIl' is held at the low level as shown in Figure 4-(7). That is, the first transistor TR1 ' in the second amplifying circuit 61 b is placed in the off state before the data sigQal is developed at the emitter of the third transistor TR3 at the time t4. Accordingly, even 105 when the high voltage is developed at the second terminal 72 at the time t4 as shown in Figure 4 (6), the base voltage of the first transistor TRV of the second amplifying circuit 61 b is maintained at the above-mentioned low level so as to maintain 110 the off state of the first transistor TR1 '.
As long as the first transistor TFIV is held in the off state, the second transistor TR2' in. the second amplifying circuit 61 b is held in the off state. Accordingly, the collector voltage of the second transistor TR2' is maintained at the low level as shown in Figure 4-(8). The low level of the collector voltage of the second transistor TR2' is applied to the base of the third transistor TFIX in the second amplifying circuit 61 b so as to maintain the third transistor TR3' in the off state. While the third transistor TR3' is held in the off state, the emitter voltage of the fflird transistor TR3' is held at the low level as shown in Figure 4(9). Thus, the first diode D l' is maintained in the off state, the cathode of the first diode DV being 125 supplied with the data signal shown in Figure 4(1). In this way, the second amplifying circuit 61 b is precluded from performing its function. That is, the data signal developed from the emitter of the third transistor TR3 in the first amplifying circuit 61 a will not be returned to the first amplifying circuit 61 a via the second amplifying circuit 61 b because the second amplifying circuit 61 b is placed in the non-operating condition.
When the data signal applied to the first terminal 71 begins to change to the logic low at a time 15 as shown in Figure 4-(1), the first transistor TR1 is turned off at a time t6. That is, the collector voltage of the first transistor TR 1 bears the logic high at the time t6 as shown in Figure 4-(2). With predetermined time delays, the second and third transistors TR2 and TR3 are placed in the off states at times t7 and t8, respectively. The collector voltage of the second transistor TR2 and the emitter voltage of the third transistor TR3 change as shown in Figures 4-(3) and 4-(4), respectively. Then, the fourth transistor TR4 is placed in the off state at a time tg. That is, the fourth transistor TR4 is maintained in the on state till the time t9. Accordingly, the collector voltage of the fourth transistor TR4 is maintained at the low level till the time tg as shown in Figure 4-(5). While the collector voltage of the fourth transistor TR4 is maintained at the low level, (till the time t9), the base voltage of the first transistor TR1' is held at the low level via the second diode D2 as shown in Figure 4-(7), whereby the first transistor TR 1' in the second amplifying circuit 61 b is held in the off state. That is, at the trailing edge of the data signal applied to the first terminal 7 1, the second amplifying circuit 61 b will not erroneously operate.
In a preferred form, the voltage level applied to the first power supply terminal B1 is 8V, and the voltage level applied to the second power supply terminal B2 is 12V.
When the data signal is applied from the terminal station 42 to the second terminal 72, the amplified and shaped data signal is developed from the emitter of the third transistor TR3' of the second amplifying circuit 61 b and applied to the first terminal 7 1. The first transistorTR1 of the first amplifying circuit 61 a is held in the off state to preclude the cycling of the data signal betweeh the first and second amplifying circuits 61 a and 61 b.
The invention being thus described, it will be obvious that the same may be varied in many ways. Such variations are not to be regarded as a departure from the spirit and scope of the invention, and all such modifications are intended to be included within the scope of the following claims.
Claims (6)
1. An in-line data communication system comprising:
a first terminal station; a second terminal station; a bidirectional communication cable for connecting said first terminal station with said second terminal station; and 4 GB 2 127 652 A 4 a signal level compensation circuit interposed in said bidirectional communication cable, said signal level compensation circuit comprising:
a first amplifying circuit for amplifying a data signal transmitted in one direction from said 40 first terminal station; a second amplifying circuit connected to said first amplifying circuit in a parallel fashion, said second amplifying circuit amplifying a data signal transmitted in the opposing direction from said second terminal station; enabling means for enabling said first amplifying circuit when the data signal is transmitted in said on e direction, and for enabling said second amplifying circuit when 50 the data signal is transmitted in said opposing direction; and inhibition means for disabling said second amplifying circuit when the data signal is transmitted in said one direction, and for disabling said first amplifying circuit when the data signal is transmitted in said opposing direction.
2. The in-line data communication system of claim 1, further comprising:
a first interface means disposed between said first terminal station and said bidirectional communication cable for performing data communication; and a second interface means disposed between said second terminal station and said bidirectional communication cable for performing data communication.
3. The in-line data communication system of claim 1, said signal level compensation circuit further comprising:
a first input/output terminal communicated to said first terminal station via said bidirectional communication cable; and a second input/output terminal communicated to said second terminal station via said bidirectional communication cable.
4. The in-line data communication system of claim 3, wherein:
said first ampi.ifying circuit includes an input stage connected to said first input/output terminal, and an output stage connected to said second input/output terminal; and said second amplifying circuit includes an input stage connected to said second input/output terminal, and an output stage connected to said first input/output terminal.
5. The in-line data communication system of claim 4, wherein said inhibition means disables said input stage of said second amplifying circuit before an amplified data signal is developed from said output stage of said first amplifying circuit when the data signal is transmitted in said one direction, and said inhibition means disables said input stage of said first amplifying circuit before an amplified data signal is developed from said output stage of said second amplifying circuit when the data signal is transmitted in said opposing direction.
6. A communication system substantially as herein described with reference to Figures 2 to 4 of the accompanying drawings.
Printed for Her Majesty's Stationery Office by the Courier Press, Leamington Spa, 1984. Published by the Patent Office, 25 Southampton Buildings, London, WC2A 'I AY, from which copies maybe obtained.
1 % J
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57133997A JPS5925450A (en) | 1982-07-31 | 1982-07-31 | In-line data communication device |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| GB8320193D0 GB8320193D0 (en) | 1983-09-01 |
| GB2127652A true GB2127652A (en) | 1984-04-11 |
| GB2127652B GB2127652B (en) | 1986-02-05 |
Family
ID=15117964
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB08320193A Expired GB2127652B (en) | 1982-07-31 | 1983-07-27 | Bidirectional in-line signal compensation circuit |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US4621367A (en) |
| JP (1) | JPS5925450A (en) |
| DE (1) | DE3327488A1 (en) |
| GB (1) | GB2127652B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2185666A (en) * | 1986-01-16 | 1987-07-22 | Gen Electric Co Plc | A data bus coupler |
| GB2340686A (en) * | 1998-08-07 | 2000-02-23 | Mitel Semiconductor Ltd | A bidirectional open-drain bus driver in a television receiver |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4725836A (en) * | 1986-01-27 | 1988-02-16 | Snap Systems, Inc. | Series port connection of a plurality of terminals to a master processor |
| JPH0644742B2 (en) * | 1987-03-19 | 1994-06-08 | 和泉電気株式会社 | Multiplex transmission system |
| JPH0683108B2 (en) * | 1987-11-20 | 1994-10-19 | 日本電気株式会社 | Signal control method |
| US5051980A (en) * | 1988-08-11 | 1991-09-24 | El Paso Natural Gas Company | Data communication interface device |
| DE19644772C2 (en) * | 1996-10-28 | 1999-08-05 | Siemens Ag | Bidirectional level adjustment |
| DE19725917A1 (en) * | 1997-06-19 | 1999-01-07 | Telefunken Microelectron | Transmitting and receiving device, in particular for peripheral modules of a control system with a central unit controlling the modules |
| KR100386763B1 (en) * | 1999-08-19 | 2003-06-09 | 마쯔시다덴기산교 가부시키가이샤 | Bidirectional signal transmission system |
| DE10219056A1 (en) * | 2002-04-24 | 2003-11-13 | Demag Cranes & Components Gmbh | Bus driver for bidirectional two-wire bus systems |
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| GB1577667A (en) * | 1976-05-19 | 1980-10-29 | Western Electric Co | Time sampled or time division switching systems |
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| US3237164A (en) * | 1962-06-29 | 1966-02-22 | Control Data Corp | Digital communication system for transferring digital information between a plurality of data processing devices |
| US3308392A (en) * | 1965-02-04 | 1967-03-07 | Esso Production Company | Seismic amplifier having means for changing the amplification of the seismic signal by discrete steps proportional to a given power of two |
| US3499985A (en) * | 1967-03-02 | 1970-03-10 | Us Navy | Two-way pulse repeater |
| US3586793A (en) * | 1968-06-21 | 1971-06-22 | John C Neal | Two way repeater |
| US3660599A (en) * | 1969-07-16 | 1972-05-02 | Int Standard Electric Corp | Method of and circuit arrangement for picture transmission using multiplex techniques |
| US3827026A (en) * | 1971-01-04 | 1974-07-30 | Honeywell Inf Systems | Encoding technique for enabling a device to process different types of digital information transmitted along a single information channel |
| DE2131019A1 (en) * | 1971-06-23 | 1972-12-28 | Wandel & Goltermann | Bidirectional switching amplifier |
| DE2134090B2 (en) * | 1971-07-08 | 1975-10-30 | Wandel U. Goltermann, 7410 Reutlingen | Bidirectional digital amplifier for binary data signals - has logic circuit controlling data direction in response to input data signals |
| JPS50103917A (en) * | 1974-01-16 | 1975-08-16 | ||
| CA1063717A (en) * | 1975-03-12 | 1979-10-02 | Chih C. Yu | Programmable binary amplifier |
| US4063220A (en) * | 1975-03-31 | 1977-12-13 | Xerox Corporation | Multipoint data communication system with collision detection |
| US3969683A (en) * | 1975-04-21 | 1976-07-13 | Bell Telephone Laboratories, Incorporated | Automatic level control circuit |
| US3988675A (en) * | 1975-11-10 | 1976-10-26 | Motorola, Inc. | Transmit-receive switching circuit with audio muting |
| US4101734A (en) * | 1976-11-15 | 1978-07-18 | Signetics Corporation | Binary to multistate bus driver, receiver and method |
| US4095183A (en) * | 1977-01-25 | 1978-06-13 | Cybernet Electronic Corporation | Tuning circuit |
| US4099024A (en) * | 1977-02-16 | 1978-07-04 | Xerox Corporation | Communications network repeater |
| US4154978A (en) * | 1977-12-08 | 1979-05-15 | Operating Systems, Inc. | Self-contained bidirectional amplifying repeater |
| JPS6041898B2 (en) * | 1977-12-31 | 1985-09-19 | 株式会社リコー | Transmission/reception circuit |
| JPS5696562A (en) * | 1979-12-28 | 1981-08-04 | Fujitsu Ltd | Connection circuit for transmission line |
| US4404672A (en) * | 1980-03-28 | 1983-09-13 | Nippon Electric Co., Ltd. | Subscriber terminal for use in a time shared bidirectional digital communication network |
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-
1982
- 1982-07-31 JP JP57133997A patent/JPS5925450A/en active Pending
-
1983
- 1983-07-26 US US06/517,275 patent/US4621367A/en not_active Expired - Lifetime
- 1983-07-27 GB GB08320193A patent/GB2127652B/en not_active Expired
- 1983-07-29 DE DE19833327488 patent/DE3327488A1/en active Granted
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1058556A (en) * | ||||
| GB1313304A (en) * | 1969-10-06 | 1973-04-11 | Honeywell Inc | Digital data handling device |
| US3673326A (en) * | 1970-08-17 | 1972-06-27 | Francis F Lee | Communication system |
| GB1476455A (en) * | 1973-07-28 | 1977-06-16 | Kokusai Denshin Denwa Co Ltd | Two-way signal transmission system |
| GB1542700A (en) * | 1975-06-30 | 1979-03-21 | Int Standard Electric Corp | Loudspeaking telephone |
| GB1577667A (en) * | 1976-05-19 | 1980-10-29 | Western Electric Co | Time sampled or time division switching systems |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2185666A (en) * | 1986-01-16 | 1987-07-22 | Gen Electric Co Plc | A data bus coupler |
| GB2185666B (en) * | 1986-01-16 | 1989-10-25 | Gen Electric Plc | A data bus coupler |
| GB2340686A (en) * | 1998-08-07 | 2000-02-23 | Mitel Semiconductor Ltd | A bidirectional open-drain bus driver in a television receiver |
Also Published As
| Publication number | Publication date |
|---|---|
| GB2127652B (en) | 1986-02-05 |
| GB8320193D0 (en) | 1983-09-01 |
| DE3327488C2 (en) | 1987-02-05 |
| DE3327488A1 (en) | 1984-04-05 |
| US4621367A (en) | 1986-11-04 |
| JPS5925450A (en) | 1984-02-09 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 20020727 |