GB2331833A - Asynchronous data detection apparatus for use in a magnetic playback system - Google Patents

Abstract

The apparatus comprises an AD converter 200 for converting an analog playback signal into digital form, using a system clock signal CLK, to provide a sample, means 300 for interpolation filtering the sample using a phase error signal and generating a hold signal H if a predetermined hold condition is satisfied, means 400 for equalizing the sample, means 600 for performing maximum likelihood sequence detection on the equalized sample, means 800 for obtaining a phase error signal for supplying to the interpolation filtering means, means 700 for controlling data output using the system clock signal CLK, a data output clock signal CLK1 (having a frequency lower than CLK) and the hold signal H to provide final output data to a codec system.

Description

t is 2331833 ASYNCHRONOUS DATA DETECTION APPARATUS FOR USE IN A MAGNETIC

RECORDING/PLAYBACK SYSTEM The present invention relates to a data detection apparatus for use in a magnetic recording /p 1 ayback system; and, more particularly, to an asynchronous data detection apparatus for use in a magnetic recording/playback system.

An analog-based recording /p 1 ayback technique has long been used in a conventional magnetic recording/ reproducing system such as a video cassette recorder (VCR). When images are recorded in an analog form, which is then played back by using a conventional magnetic recording/ reproduc ing system, the image quality may be markedly deteriorated.

For example, when a conventional VCR utilizing an analog based. rec:crd-..,-g/pla-,.-back technique is in a playback mode, signals distorted due to noises and jitters are directly delivered from the VCR. Moreover, if the signals are edited or other operation is performed on the signa 1 is, distortions tend to accumulate, thereby resulting in further deterioration of the played back image quality. Therefore, development of a VCR utilizing a digital-based record i ng/pl ayback technique capable of overcoming the above-mentioned shortcomi-..lgs of the analog VCR has been proposed.

1 Y It is well known in the art that in the recording mode of a digital VCR, an analog video and an analog audio signals which have been coded and modulated are sampled and converted into discrete quantized digital values, and then these digital values are recorded on a magnetic tape at a predetermined recording frequency, wherein the magnetic tape is used by the digital VCR as a typical data storage medium.

In the playback mode of a conventional digital VCR, magnetic flux transitions are induced in a read element of a magnetic head and supplied over a path to a preamplifier as an analog signal. The preamplifier amplifies the anaLog signal to a predetermined level to thereby provide an analog playback signal.

And then, an analog to digital (A/D) converter of the digital VCR converts the analog playback signal at a predetermined channel rate into a digital playback signal. The digital playback signal is transmitted to a digital data processin,7 channel of _he digital VCR, wherein the digita'playback signal is detected and processed.

But, in the process of digital data detection and transmission thereof, there may occur a channel -induced signal distortion, such as intersymbol interference (ISI) due to a high speed data transmission over channels of limited bandwidt'n, which causes obstruction in data transmLssion thereof, thereby entailing transmission errors. It is well known in the art that partial response maximum likelihood - 2 t) is (PRML) method is effective to correct ISI incurred therein.

Therefore, a conventional digital VCR usually comprises a data detection apparatus including an equalization circuit having filters to equalize a digital playback signal to an equalized signal, e.g., a partial response class 4 (PR4) signal. For example, a discrete time finite impulse response (FIR) filter receives and equalizes sample values of a digital playback signal to a predetermined spectrum by using a so called PRML method, wherein the discrete time transfer function for use in the PRML technique is typically (1-D 2) wherein D represents a unit-time delay operator.

In a PRML method, the output from a noisy partial response channel is sampled at a predetermined channel rate and detected by using a PRM detector. Typically, a viterbi detector is used in a maximum likelihood sequence detection (MLSD) of the sampled partial response channel. It is well known in the art that a viterbi algorithm is an iterative pro.:es of keeping track of the path with the, smallest accumulated metric leading to each state in the trellis.

In detail, the metrics of all of the paths leading to a particular state are calculated and compared in the viterbi algorithm. Then, the path with the smallest metric is selected as a survivor path. In this manner, all paths which can be part of the minimum metric paths through the trellis are stored in a path memory.

Given that the path memory is sufficiently long, all of is the survivor paths represented as corresponding decision values will diverge from a single path within the span of the path memory. The single path from which all the curren't survivor paths diverge is a minimum metric path as a final survivor path. An input sequence associated with the minimum metric path appears as a binary data value (BD) in all the outputs of the Viterbi detector.

The structure and function of a conventional asynchronous data detection apparatus for use in a magnetic recording/playback system can be explained with reference to Fig. 1. Fig. 1 provides a block diagram of an asynchronous data detection apparatus 30 for use in a magnetic recording/playback system. The data detection apparatus 30 comprises an analog to digital (A/D) converter 31, an interpolation circuit 32, an equalizer 33, a data detector 34, a timing recovery circuit 36 and a system clock signal (CLK) generator 37.

he magnetic recording/playback system is,.-.rovidE-d a magnetic head (not shown) having a read element (not shown).

The data detection apparatus 30 detects binary data values from analog playback signals being obtained through preamplifying magnetic flux transitions induced by the read element of the magnetic head from a magnetic recording medium to a predetermined level.

lt should be noted that digiL-al data have been prerecorded on the magnetic recording medium to a prede?--ermined 4 is level in accordance with a predetermined recording frequency (PRF), e.g., 41.85 MHz.

In the data detection apparatus 30, an analog playback signal is first inputted to the A/D converter 31. The A/D converter 31 samples and converts the analog playback signal into a digital playback data as a sample value (S) in accordance with a CLK inputted thereto from the CLK generator 37, e.g., a memory control unit in the magnetic recording /playback system. The S is fed to the interpolation circuit 32 via a line L2. The CLK is also fed to the interpolation circuit 32, the equalizer 33, the data detector 34 and the timing recovery circuit 36.

It should be noted that in the data detection apparatus 30, if a S is generated at the A/D converter 31 under the condition that the frequency of the CLK is greater than the PRF, the interpolation circuit 32 operates in an asynchronous mode and hence, the S is regarded as asynchronous data and i a S is generated at the A/D converter 31 under the condition that the frequency of the CLK is equal to the PRF, the interpolation circuit 32 operates in a synchronous mode and hence, the S is regarded as synchronous data.

The interpolation circuit 32 performs interpolation filtering on the S based on a previously obtained phase error signal (PE) fed thereto from the tirm-ing recovery circuit 36 in accordance with the CLK via a line L8 to thereby provide an interpolated sample value (IS) to the equalizer 33 through - 5 a line L3 And the interpolation circuit 32, with reference to the previously obtained PE, also generates a hold signal (H) in accordance with the CLK if a predetermined hold condition is satisfied. It should be noted that in case that the data detection apparatus 30 is operated in the asynchronous mode thereof, the interpolation circuit 32 generally generates the H.

In detail, in the synchronous mode, the interpolation circuit 32 mrovides the S as an interpolated sample value (IS) based on the previously obtained PE in accordance with the CLK to the equalizer 33 via the line L3. And, in the interpolation circuit 32, the IS is delayed by one datadetection delay time interval (DDTI) and then a previously stored!S in a memory thereof is replaced by the one DDTI delayed IS.

In the asynchronous mode, the interpolation circuit 32 "--,:)nol.is data based on the first determines the 5 as async.. previously obtained PE to thereby retrieve the prestored IS J n the memory thereof as an IS in accordance with the CLK and - l- then provide the IS to the equalizer 33 via the line L3. And at the same time, the interpolation circuit 32, with reference - c) the previously obtained PE, if a predetermined hold condition is satisfied, generates a hold signal (H) and -L-1-1-en supplies same to the equalizer 33, the data detector 34 and the timincr recovery circuit 36.

6 The equalizer 33 performs an equalization on the IS in accordance with the CLK inputted thereto from the CLK generator 37 by using a predetermined equalization technique to thereby provide an equalized sample value (ES) to the data detector 34 via a line LS. And the equalizer 33 supplies an error signal (E) to the timing recovery circuit 36 through a line L4, wherein the E represents an error between a filtered data obtained by carrying out a finite response filtering on the IS and a level decision value obtained by performing a conventional level determination on the filtered data therein.

The data detector 34 having a viterbi detector (not shown) performs a MLSD on the ES by using the CLK to detect survivor maths thereof, thereby supplying a binary data value (BD) representing a final survivor path detected therein to is a codec system (not shown) for further processing thereof through a line L6. And at the same time, the data detector 34 provides a predetermined number, e.g., 2 or 3, of decision ,,al.u,es as a decision value set (<DV>) representing survivor paths detected therein to the timing recovery circuit 36 via a line L7.

The timing recovery circuit 36 carries out a tim-ing recovery process to obtain a PE based on the <DV> by using a predetermined PE generation technique to thereby supply a PE to the interpolation circuit 32 through a line L8.

It should be noted that in each of the equalizer 33, the data detector 34 and the timing recovery circuit 36, if the - 7 H is inputted therein, the operation thereof is held for the one DDTI, e. g., one clock time interval of the CLK.

A conventional asynchronous data detection apparatus such as the one described above, however, has certain problems. In detail, in the conventional asynchronous data detection apparatus, the output frequency of the binary data sequence from the data detector does not coincide with the PRF.

In other words, the conventional asynchronous data detection apparatus entails a discord between the data sequence feeding frequency toward the codec system and the data processing frequency therein. This leads to an unnecessary output data accumulation in the data detector to thereby deteriorate the performance of the data detection apparatus.

is Further, if a lot of hold signals are generated during a short time interval at the interpolation circuit, the performance of the equalizer is deteriorated.

As described above, the conventional asynchronous data detection apparatus has limitations on both suppressing unnecessary output data accumulation therein and enhancing the equalization performance thereof.

!t is, therefore, an object of -the present invention to provide an asynchronous data detection apparatus capable of suppressing unnecessary cult,-put data accumulation for use in - 8 a magnetic recording/playback system.

Another object of the present invention is to provide an asynchronous data detection apparatus to enhance the equalization performance thereof for use in a magnetic recording/playback system.

According to the present invention, there is provided an asynchronous data detection apparatus for use in a magnetic recording/playback system provided with a magnetic head having a read element to detect binary data values from analog playback signals being obtained through preamplifying magnetic flux transitions induced by the read element ofthe magnetic head from a magnetic recording medium to a predetermined level, wherein digital data have been pre-recorded on the magnetic recording medium to a predetermined level at a predetermined recording frequency, the apparatus comprising:

means for generating a system clock signal (CLK) wherein the frequency of the CLK is greater than the predetermined recording frequency (PRF); means for generating a data output clock signal (CLK1), wherein the frequency of the CLK1 is equal to the PRF; means for analog to digital (A/D) converting to analog playback signal into digital playback data in accordance with the CLK to thereby provide a sample value (S); means, based on a previously obtained phase error signal, for performing interpolation filtering on the S in accordance with the CLK to thereby provide an interpolated sample value (IS) and at the same time, if a predetermined hold condition is satisfied, generate a hold signal (H); means for performing equalization on the IS in accordance with the CLK to thereby supply an equalized sample value (ES) and at the same time provide an error - 9 signal (E), wherein the E represents an error between filtered data obtained by carrying out a finite response filtering on the IS therein and a level decision value obtained by performing a level determination on the filtered data therein; means for performing a data detection on the ES by using a maximum likelihood sequence detection (MLSD) technique to detect survivor paths in accordance with the CLK, thereby supplying a binary data value (BD) representing a final survivor path obtained therein and a predetermined number of decision values as a decision value set (<DV>) representing survivor paths detected therein; means for carrying out a timing recovery process to obtain a phase error signal (PE) based on the <DV> and E in accordance with the CLK to thereby supply the PE to said interpolation filtering means; and means for executing an output control on the BD by using the H, CLK and CLK1 to thereby provide final output data (FD).

- The above and other objects and features of the present invention will become apparent from the following description of preferred embodiments given in conjunction with the accompanying drawings, in which:

Fig. I provides a block diagram of a conventional asynchronous data detection apparatus for use in a magnetic recording/playback system; Fig. 2 illustrates a block diagram of an asynchronous data detection apparatus for use in a magnetic recording/playback system in accordance with a preferred embodiment of the present invention; Fig. 3 depicts a detailed block diagram of an output control circuit within the data detection apparatus illustrated in Fig. 2; Figs. 4A to 4K exhibit diagrams representing wave forms of clock signals and output data sequences for use in describing the operation of the output control circuit depicted in Fig. 3; and Fig. 5 shows a detailed block diagram of a weight control circuit within the data detection apparatus illustrated in Fig. 2.

Referring to Fig. 2, there is illustrated a block diagram of an asynchronous data detection apparatus 100 for use in a magnetic recording/playback system, e.g., a digital video cassette recorder (DVCR) in accordance with a preferred embodiment of the present invention.

The magnetic recording/playback system is provided with a magnetic head (not shown) having a read element (not shown).

The data detection apparatus 100 detects binary data values from analog playback signals being obtained through preamplifying magnetic flux transitions induced by the read element of the magnetic head from a magnetic recording medium e.g., a magnetic tape to a predetermined level. It should be noted that digital data have been pre-recorded on the magnetic recording medium to a predetermined level at a predetermined recording frequency (PRF), e.g., 41.85 MHz.

In accordance with a preferred embodiment of the present invention, the data detection apparatus 100 comprises an is analog to digital (A/D) converter 200, an interpolation circuit 300, an equalization circuit 400, a data detection circuit 600, an output control circuit 700 and a timing recovery c-Jrc.uit,. 800.

The data detection apparatus 100 also comprises a system clock signal (CLK) generator 900, e.g., a memory control unit in the system to generate a CLK and a data output clock signal (CLK1) generator 950, e.g., a central processing unit (CPU) in the system to generate a CLK1. it should be noted that the frequency of the CLEK, e.g., 41. 85 + a MHz (ce > 0), is greater than that of the CLK1 and the f requency of the CLK1 is equal to the PRF.

12 In accordance with another embodiment of the present invention, the data detection apparatus 100 further comprises a weight control circuit 500.

The CLK is fed to the A/D converter 200, the interpolation filter 300, the equalization circuit 400, the data detection circuit 600, the output control circuit 700 and the timing recovery circuit 800. The CLK1 is inputted to the output control circuit 700. And in accordance with a preferred embodiment of the present invention, the CLK1 is also fed to a codec system (not shown) for further processing thereof.

The A/D converter 200 converts an analog playback signal into digital playback data in accordance with the CLK to thereby provide a sample value (S) to the interpolation circuit 300 via a line L10.

The interpolation circuit 300 performs an interpolation filtering on the S based on a previously obtained phase error signal fed tlhereto from the timing recovery circuit 8C0 j!-a a line L20 in accordance with the CLK to thereby provide an interpolated sample value (IS) to the equalization circuit 400 through a line L11 and at the same time, if a predetermined hold condition is satisfied, generates a hold signal (H).

It should be noted that if the -H is generated by the interpolation circuit 300, the H is fed to the equalization circuit 400, the weight control circuit 500, the data detection circuit 600, the output control circuit 700 and the is 13 timing recovery circuit 800.

The equalization circuit 400 performs an equalization on -ion the IS based on the CLK by using a predetermined equalizat technique to thereby supply an equalized sample value (ES) to the data detection circuit 600 via a line L13 and at the same time provide an error signal (E) to the timing recovery circuit 800 via a line 1,12. It should be noted that the E represents an error between filtered data obtained by carrying out a finite response filtering on the IS therein and a level decision value obtained by performing a level determination on the filtered data therein.

The data detection circuit 600 performs a data detection on the ES by using a maximum likelihood sequence detection (MLSD) technique to detect survivor paths in accordance with the CLK, thereby supplying a binary data value (BD) representing a final survivor path obtained therein to the output control circuit 700 through a line L16 and a number of decpiede.-erTn- ision values as a decision v--.1-e set (<DV>) representing survivor paths detected therein to the timing recovery circuit 800 via a line L15.

The timing recovery circuit 800 carries out a timing recovery process to obtain a phase error signal (PE) based on the <DV> and E in accordance with the CLK by using a predetermined PE generation techniaue to thereby supply the PE to the interpolation circuit 300 through the line L20.

The output control circuit 700 executes an output control 14 on the BD by using the H, CLK and CLK1 to thereby provide final output data (FD) to the codec system.

In detail, referring to Fig. 3, there is depicted a detailed block diagram of the output control circuit 700 within the data detection apparatus 100 illustrated in Fig. 2. And Figs. 4A to 4K exhibit diagrams representing wave forms of clock signals and output data sequences for use in describing the operation of the output control circuit 700 depicted in Fig. 3.

From now on, referring to Fig. 3 and Figs. 4A to 4K, the structure and operation of the output control circuit 700 will be described in detail. It should be noted that in Figs. 4A, 4H and 4K, the numbers appeared therein represent the data processing order, e.g., detecting, writing or retrieving order, wherein a greater number represents a later processing time than that of a smaller number. And each of vertical dot lines in Figs. 4A to 4H represents an identical timing. in Figs. 4A, 4H and 4K, hatched rortions represent asyricb-rc--.us C-, data positions processed in the asynchronous mode, respectively.

The output control circuit 700 includes a data delay circuit 710, a clock signal modification channel 720, an output control signal generation channel 730 and a firstin/first-cut (FIFO) data output control circuit 740. The output control signal generation channel 730 has a delay clock signal (DCS) generator 731 and an AND gate 732.

is - is The data delay circuit 710, e.g., as a shift register, delays the BD by one data-detection time interval (DDTI) to thereby provide a delayed BD to a data input terminal of the FIFO data output control circuit 740 via a line L71. Fig. 4A shows an output data sequence of the delayed BD at the position A indicated by an arrow in Fig. 3.

The clock signal modification channel 720 modifies the CLK by using the H to thereby supply a modified clock signal (MCLK) to a write input terminal (W) of the FIFO data output control circuit 740 via a line L72, wherein the frequency of the MCLK is equal to that of the CLK1. Fig. 4B reveals a diagram representing a wave form of the CLK at the position B indicated by an arrow in Fig. 3. Referring to Fig. 4B, there are 13 clock units of the CLK in a time interval T as shown therein.

And the output control signal generation channel 730 generates an output control signall (OCS) by using the CLK1 and then provides the OCS to a. read ccintrQl terminal (,R) p-' the FIFO data output control circuit 740 via a line L73.

The clock signal modification channel 720 has a first delay circuit 721, a second delay circuit 722, an inverter 723, a third delay circuit 724, a first AND gate 725, a fourth delay circuit 726 and a second AND gate 727. In -.he clock signal modification channel 720, the H is fed to the first delay circuit 721.

The first delay circuit 721, e.g., as a shift register, 16 is delays the H by the one DDTI to thereby provide a f irst delayed H to the second delay circuit 722 and a first input of the first AND gate 725.

terminal Fig. 4C presents a diagram representing the wave form of the first delayed H at the position C as indicated by an arrow in Fig. 3. Referring to Figs. 4A and 4C, it could be understood that the generation timing of the H coincides with that of asynchronous data indicated by 0 or 10 in Fig. 4A.

Meanwhile, the CLK is inputted to the inverter 723 and a second input terminal of the second AND gate 727. The inverter 723 inverts the CLK to thereby provide an inverted CLK to the second delay circuit 722. The second delay circuit 722, e.g., as a shift register, delays the first delayed H in response to the inverted CLK to thereby provide a second delayed H to the third delay circuit 724.

The third delay circuit 724 delays the second delayed H by a predetermined time interval, e.g., 4 nano-seconds, which is aboiiz 1/6 0. 2)-.e clock time-ini-erval of the CLK, thereby providing a third delayed H to a second input terminal of the first AND gate 725, wherein the predetermined time interval shorter than a half of one clock time interval of the CLK. Fig. 4D sets forth a diagram representing the wave form of the third delayed H at the position D indicated by an arrow in Fig. 3.

The 'first AND gate 725 performs a logic AND operation on the first delayed H and the third delayed H to thereby provide a modified H to the fourth delay circuit 726. Fig. 4E represents a wave form diagram of the modified H at the position E indicated by an arrow in Fig. 3.

The fourth delay circuit 726 delays the modified H by the predetermined time interval to thereby provide a fourth delayed H to a f irst input terminal of the second AND gate 727. Fig. 4F depicts a wave form diagram of the fourth delayed H at the position F indicated by an arrow in Fig. 3.

The second AND gate 727 executes a logic AND operation on the fourth delayed H and the CLK to thereby generate the MCLK to be supplied to the write input terminal of the FIFO data output control circuit 740 via the line L72. Fig. 4G shows a wave form diagram of the MCLK at the position G indicated by an arrow in Fig. 3.

In the output control signal generation channel 730, the CLK1 is inputted to a first input terminal of the AND gate 732. Fig. 41 reveals a diagram representing a wave form of T t'-,e CLKI at Che position. indicated by an arrow in Fig. 3.

Referring to Fig. 41, there are 11 clock units of the CLK1 in the time interval T as shown therein. Hence, referring to Figs. 413 and 41, it could be understood that the fre(Tuency of the CLK is greater than that of the CLK1.

T he DCS generator 731 generates and then provides a DCS to a second input terminal of the AND gate 732, wherein the DCS directs to delay the start. time of the CLK1 by a predetermined delay time interval. Fig. 4J represents a wave 18 is form diagram of the DCS at the position J indicated by an arrow in Fig. 3.

The AND gate 732 performs a logic AND operation on the CLKi and the DCS to thereby generate and then provide the OCS to the read control terminal of the FIFO data output control circuit 740 via the line L73.

The FIFO data output control circuit 740 performs a FIFO data output control on the delayed BD based on the MCLK in accordance with the OCS to thereby provide the FD to the codec system.

In detail, in the FIFO data output control circuit 740, the delayed 2D is written therein in accordance with the MCLK and then retrieved therefrom as the FD in accordance with the OCS. Fig. 4H shows a written data sequence of the delayed BD at the position indicated in Fig. 3 by DATA. And Fig. 4K depicts a retrieved data sequence of the FD at the position indicated in Fig. 3 by R.

it sliould be noted that the operation of the equal -za7:.o--,-l circuit 400, the data detection circuit 600, the outputcontrol circuit 700 and a timing recovery circuit 800 is held for the DDTI if the H is fed thereto.

The weight control circuit 500 performs a weight control in response to the H to thereby generate a system reset signal (SRS) and initial filter coefficients set (<'IFCS>) if more than a predetermined number of H' s are inputted thereto within a first preset time interval under the condition that the H 19 - generated by the interpolation circuit 300 Referring to Fig. 5, there is shown diagram of the weight control circuit 500 detection apparatus 100 illustrated in Fig.

is fed thereto. a detailed block within the data 2.

The weight control circuit 500 includes an inverter 510, a delay reset signal (DRS) generator 540, an accumulation module S30, a comparator 550 and a <IFCS> generator 560. The accumulation module 530 has an adder 531 and a delay circuit 532. The <IFCS> generator 560 has an address generator 561 and a read only memory (ROM) 562.

The inverter 510 inverts the H to thereby provide an inverted H to the adder 531. The DRS generator 540 produces a DRS periodically with a second preset time interval to thereby provide the DRS to the delay circuit 532 via a line L51. And the DRS generator 540 also produces a DRS if a system reset signal (SRS) is fed thereto from the comparator 550, thereby providing the DRS to the delay 532 via the line TSl.

The accumulation module 530 performs an accumulation process by using the inverted H, thereby supplying an accumulated value (ACV) to the comparator 550 via a line L52. it should be noted that if the DRS is inputted to the delay circuit 532, the delay circuit 532 is initialized so that a previously obtained delayed ACV stored therein is set to be a zero and hence the zero value is fed to the adder 531.

In detail, the adder 531 adds the inverted H to a - 20 is previously obtained delayed ACV (DACV) inputted thereto f rom the delay circuit 532, thereby providing the added value as the ACV to the comparator 550 and thedelay circuit 532 via the line 52. And the delay circuit 532, e.g., as a shift register, delays the ACV inputted thereto by the one DDTI, thereby feeding a DACV to the adder 531.

The comparator 550 compares the ACV inputted thereto within the f irst preset time interval with a predetermined threshold value (THV) to thereby generate the SRS on a line L53 if the ACV is greater than the THV. The SRS is inputted to the DRS generator 540, interpolation circuit 300, the equalization circuit 400 via a line L14, the data detection circuit 600, the output control circuit 700 and the timing recovery circuit 800. It should be noted that in accordance with a preferred embodiment of the present invention, the second preset time interval is longer than the first preset time interval.

The <IFCS> generation circuit 56C, in response to the SRS inputted thereto via the line LS3, generates the <IFCS> on the line L14. In detail, the address generator 561 generates and then su-onlies an address signal indicating an address to be used in accessing the <IFCS> within the ROM 562 in response to the SRS. The ROM S62 reads out the <IFCS> by using the address signal to thereby produce the <IFCS> on the line L14.

It should be noted that in case that the <IFCS> is generated by the weight control circuit SOO, the <IFCS> is - 21 inputted to the equalization circuit 400 and then the <IFCS> is utilized to update the filter coefficients employed therein.

And it should be also noted that the operation in each of the interpolation circuit 300, the equalization circuit 400, the data detection circuit 600, the output control circuit 700 and the timing recovery circuit 800 is reset in response to the SRS under the condition that the SRS is generated by the weight control circuit 500 and then fed thereto.

For example, in case that the SRS is inputted to the DCS generator 731 and the FIFO data output control circuit 740 in the output control circuit 700 via a line L75, the DCS generator 731 and the FIFO data output control circuit 740 are reset.

While the present invention has been described with respect to certain preferred embodiments only, other modif ications and variations. mav be made wit -out de:)artincr from the scope of the present invention as set forth in the following claims.

is - 22

Claims (14)

Claims

1. An asynchronous data detection apparatus for use in a magnetic recording/playback system provided with a magnetic head having a read element to detect binary data values from analog playback signals being obtained through preamplifying magnetic flux transitions induced by the read element of the magnetic head from a magnetic recording medium to a predetermined level, wherein digital data have been pre- recorded on the magnetic recording medium to a predetermined level at a predetermined recording frequency, the apparatus comprising:

means for generating a system clock signal (CLK), wherein the frequency of the CLK is greater than the predetermined recording frequency (PRF); means for generating a data output clock signal (CLK1), wherein the frequency of the CLK1 is equal to the PRF; means for analog-te digi,--.-IL (A/D) converting an analog playback signal into digital playback data in accordance with the CLK to thereby provide a sample value (S); means, based on a previously obtained phase error signal, for performing interpolation filtering on the S in accordance with the CLK to thereby provide an interpolated sample value (IS) and at the same time, if a predetermined hold condition is satisfied, generate a hold signal (H).

means for performing equalization on the IS in accordance - 23 is with the CLK to thereby supply an equalized sample value (ES) and at the same time provide an error signal (E), wherein the E re=esents an error between filtered data obtained by carrying out a finite response filtering on the IS therein and a level decision value obtained by performing a level determination on the filtered data therein; means for performing a data detection on the ES by using a maximum likelihood sequence detection (MLSD) technique to detect survivor paths in accordance with the CLK, thereby supplying a binary data value (BD) representing a f inal survivor path obtained therein and a predetermined number of decision values as a decision value set (<DV>) representing survivor paths detected therein; means for carrying out a timing recovery process to obtain a phase error signal (PE) based on the <DV> and E in accordance with the CLK to thereby supply the PE to said interpolation filtering means; and mcan., fnr executing ar output control on the BD by using the H, CLK and CLK1 to thereby provide final output data (FD) L

2. The apparatus according to claim 1, wherein said output control executing means includes: means for delaying the BD by one data-detection delay time interval (DDTI) to thereby provide a delayed BD; means for modifying the CLK by using the H to thereby supply a modi. f ied clock signal (MCLK), wherein the frequency - 24 of the MCLK is equal to that of the CLK1; means for generating an output control signal (OCS) by using the CLK1; and means for performing a f irst-in/f irst -out (FIFO) data output control on the delayed BD based on the MCLK in accordance with the OCS to thereby provide the FD.

3. The apparatus according to claim 2, wherein in said FIFO data output control means, the delayed BD is written therein in accordance with the MCLK and then retrieved therefrom as the FD in accordance with the OCS.

4. The apparatus according to claim 3, wherein said CLK modifying means has: means for delaying the H by the one DDTI to thereby provide a first delayed H; means for inverting the CLK to thereby provide an 7 iriver-LerCiLiK; means for delaying the first delayed H in response to the inverted CLK to thereby provide a second delayed H; means for delaying the second delayed H by a predetermined time interval shorter than a half of one clock time interval of the CLK to thereby provide a third delayed H; means for performing a logic AND operation on the first delayed H and the third delayed H to thereby provide a modif ied H; means for delaying the modified H by the predetermined time interval to thereby provide a fourth delayed H; and means for executing a logic AND operation on the fourth delayed H and the CLK to thereby generate the MCLK.

5. The apparatus according to claim 4, wherein said OCS generating means has: means for generating a delay clock signal (DCS) directing to delay a start time of the CLK1 by a predetermined delay time interval; and means for performing a logic AND operation on the CLK1 and the DCS to thereby generate the OCS.

6. The apparatus according to claim 5, wherein if the H is generated by the interpolation filtering means, the H is fed to said equalization means, said data detection means, said ti:m:'Lng recovery means and said output control and then each of the operation of said equalization means, said data detection means, said timing recovery means and said output control means is held for the one DDTI.

7. The apparatus according to claim 6, further comprising:

means for performing a weight cc-ntrol by using the H to thereby generate a system reset signal (SRS) and initial filter coefficients set (<IFCS>) if more than a predetermined 26 number of H's are inputted thereto within a first preset time interval under the condition that the H generated by the interpolation means is fed thereto.

8. The apparatus according to claim 7, wherein said weight control means includes:

an inverter for inverting the H to thereby provide an inverted H; a delay reset signal (DRS) generator for producing a DRS periodically with a second preset time interval which is longer than the first preset time interval; an accumulation module for performing accumulation by using the inverted H to thereby supply an accumulated value (ACV); a comparator for comparing the ACV with a predetermined threshold value (THV) within the first preset time interval to thereby generate the SRS if the ACV is greater than the THV; and a <IFCS> generator for generating the <I-7CS> in response to the SRS.

9. The apparatus according to claim 8, wherein if the SRS is generated by the weight control means, the SRS is fed to said interpolation filtering means, said equalization means said data detection means, said timing recovery means and said outDut control means and then the operation in each of said - 27 interpolation filtering means, equalization means, said data detection means, said timing recovery means and said output control means is reset.

10. The apparatus according to claim 9, wherein said accumulation module has: an adder for adding the inverted H to a previously obtained delayed ACV (DACV) to thereby provide the added value as the ACV; and a delay circuit for delaying the ACV by the one DDTI to thereby provide the DACV to the adder, wherein said delay circuit for delaying the ACV is initialized in response to the DRS if the DRS is inputted thereto from the DRS generator.

11. The apparatus according to claim 10, wherein said <IFCS> generator has: an address generator for generating an address signal indicating an address tc, be used -L.. accessing the <IFCS> in resmonse to the SRS; and a read only memory to read out the <IFCS> by using the address signal to thereby produce the <IFCS>.

12. The apparatus according to claim 11, wherein in case that said <IFC-S> is generated by the weight control means, the <IFCS> is inputted to said equalization means and then utilized to update the filter coefficients employed therein.

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13. The apparatus according to claim 12, wherein if the SRS is fed to the DRS generator, the DRS generator produces and then provides the DRS to the delay circuit.

14. An asynchronous data detection apparatus for use in a magnetic recording/playback system constructed and arranged substantially as herein described with reference to or as shown in Figures. 2, 3 and 5 of the accompanying drawings.

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