GB2314489A - Phase detecting method of a digital vestigial sideband modulation communication device - Google Patents

Abstract

A phase detecting method of a digital vestigial sideband modulation communication device has the steps of: digital-filtering I channel data applied from the exterior to restore Q channel data; compensating for a phase of the I and Q channel data by a prescribed phase error value; estimating an I channel level value which approximates to the I channel data from the phase-compensated I channel data; and obtaining a difference between the phase-compensated I channel data and the estimated I channel level value, and generating as the phase error value an operation value obtained by multiplying the difference by a sign of the Q channel data. The phase error is optimised by non-linear processing involving elimination of an isolated point.

Description

PHASE DETECTING METROD AND PHASE TRACKING LOOP CIRCUIT OF A DIGITAL VESTIGIAL SIDEBAND MODULATION COMMUNICATION DEVICE The present invention relates to a demodulator of a digital modulation communication system, and more particularly to a phase tracking loop (PTL) circuit and a phase detecting method for detecting a phase of a signal received from the demodulator to perform a data communication under use of a digital vestigial sideband (VSB) modulation.

The present application for a demodulator of a digital modulation system, is based on Korean Application No. 9250/1995 which is incorporated herein by reference for all purposes.

Since developing black and white television and color television, recent television developments have sought to give a realistic ambience, to have a large-sized screen and to increase resolution. With active research and development of such trends, Japan is sending the first high definition television (HDTV) broadcasting based on an analog transmission system. Such a system is called "Multiple Sub-Nyquist Sampling Encoding (MUSE)" transmission system. In U.S., a VSB modulation system has been proposed and adopted as a modulating method of a HDTV system by a GA (Grand Alliance) committee. The VSB modulation system is used as a modulating technique of an analog video signal in conventional TV broadcasting, and utilized to transmit a digital modulation signal in GA HDTV. In initial digital spectrum compatible (DSC) HDTV, 2-VSB and 4-VSB respectively using 2 and 4 levels are selected as the modulating method. In the GA HDTV, however, 8-VSB using 8 levels and 16-VSB using 16 levels applied to a high speed cable mode are selected as the modulating method. In order to demodulate VSB signals, the GA committee has proposed a schematic structure of a VSB receiver. The proposed VSB receiver of the HDTV has the following features. First, the proposed VSB receiver performs sampling by the unit of a symbol rate, unlike other demodulators of a digital modulating signal, by detecting data using only a signal of an I (in-phase) channel. Hence the VSB receiver has a simple structure in comparison with a quadrature amplitude modulation (QAM) receiver etc. simultaneously using a Q (quadrature) channel. Furthermore, even though a processing speed is relatively lower than a fractional rate receiver, data detection is possible because the data is processed by the symbol rate.

The proposed VSB receiver uses synchronous coherent detection for demodulating a carrier wave from the receiver to detect digital data from a modulating signal.

Although the synchronous coherent detection has an advantage in that it is possible to detect the data by a lower error rate than asynchronous coherent detection at the same signal-to-noise ratio, the structure of the receiver is more complicated due to a carrier wave restoring circuit. Therefore, in order to detect a phase of a transmitting signal for the synchronous coherent detection, the proposed VSB receiver is constructed with 2 stages using a frequency and phase locked loop (FPLL) and a phase tracker.

The FPLL estimates the phase of the transmitting signal using a pilot signal contained in the VSB signal.

The FPLL can be easily constructed by a frequency error detecting circuit of a conventional phase locked loop (PLL) and is disclosed in GA HDTV system specifications.

An output of the FPLL is supplied to an input of a PTL circuit after passing through a channel equalizer. The PTL circuit eliminates the noise of a phase which is not eliminated in the FPLL, that is, a phase error. The PTL circuit of the GA HDTV receiver is not quite different in structure from a decision directed carrier recovery (DDCR) circuit. However, the PTL circuit compensates for an error value of the phase after estimating a rotary component of signal points using sampled data of an input I channel. In data of the I channel, information to be actually transmitted is contained. Although the Q channel does not have an actual information transmitting function, it reduces a spectrum of a modulating signal. If there is a phase error during demodulation, a signal of the Q channel as well as data of the I channel is contained in the sampling data of the I channel. Accordingly, information of the Q channel is also needed to correct the phase error of the PTL circuit. The information of the Q channel can easily be obtained by filtering the data of the I channel by a Hilbert transform filter.

Figure 1 shows a GA HDTV receiver proposed as a standard system by the GA committee. A schematic operation of a VSB receiver shown in Figure 1 is disclosed in a collection of papers of 1994 autumn synthetic science meeting of Korea Telecommunications Society, entitled "DESIGN AND PERFORMANCE ANALYSIS OF A PHASE TRACKER FOR A SYNCHRONOUS VSB RECEIVER".

Referring to Figure 1, the operation of the VSB receiver proposed by the GA committee will be explained hereinafter. First, a signal received from an antenna is supplied to a tuner 10. An equivalent band-pass VSB signal y(t) of an output signal generated from the tuner 10 can be represented by the following equation (1): y(t) = x(t)j#ct+#(t) .....................................(1) where #c is a frequency of a carrier wave, 6(t) is a phase of the carrier wave, and x(t) is a complex lowpass filtering signal. z(t) consists of a real number component and an imaginary number component, and can be represented by the following equation (2): x(t) = xγ (t) + jxi(t) ...................................(2) A FPLL 20 restores a carrier wave eiet using a pilot signal contained in the equivalent band-pass VSB signal outputted from the tuner 10. The FPLL 20 multiplies the carrier wave effect by the equivalent band-pass VSB signal and converts the multiplied signal to a baseband signal.

The converted signal is expressed as the following equation (3): i(t) = xγ (t) cos (#[n]) - xi (t) sin (#[n]) ..............(3) A Q channel component is given by: q(t) = xγ (t) sin (#[n]) + xicos(#[n])....................(4) In the above equations (3) and (4), 0[n] is a phase error value estimated by the FPLL 20. There is a vestigial phase component caused by a phase error between the carrier wave of a received signal and the restored carrier wave. The vestigial phase component distorts a demodulating signal. In the VSB receiver proposed by the GA committee, only a signal of the I channel is used. A symbol timing recovery circuit (STR) 40 receives the output signal i(t) of the FPLL 20 and restores symbol timing to control the operation timing of an analog-todigital (A/D) converter 30. The A/D converter 30 converts the output signal i(t) of the FPLL 20 to a digital signal f[nt] according to a symbol interval rate under the control of the STR 40. The digital signal f[nT] is supplied through an equalizer 50 to a PTL 60. An output of the equalizer 50 is can be given by the following equation (5) tin the above equations N indicates a fixed number]: I[nT] ejwc[nT] = I[n] ejwc[n] =xγ [n] cos (#[n]) - xi[n] sin(#[n]) ..........(5) where it can be assumed that a variation in o (hereinafter [n] is omitted to simplify the description) is sufficiently slow. Therefore, 0[n] has a constant value during a few symbol time. The equation (5) shows an I phase component of a signal demodulated to the carrier wave in which the phase error is 8 . This signal is supplied to the PTL 60 through the equalizer 50. The PTL 60 estimates the phase error e to compensate for this value.

In the VSB modulation system, since Xr and Xi have values except 0, the phase error o can not be estimated only by the I channel signal expressed by the equation (5). Hence, a Q channel signal is needed to estimate the phase error 9 . However, since the I channel signal is used as an input of the PTL 60, the PTL 60 estimates the Q channel component of the equation (4) from the I channel component signal through a digital filter.

Figure 2 shows a block diagram of the PTL 60 according to the prior art. A digital filter 63, a Hilbert transform filter, digital-filters I data generated from a multiplier 61 to generate a restored signal Q' of the Q signal. The relationship between the I channel component and the Q channel component of an actual low-pass VSB signal is as follows: xγ * hvsb = xi ...........................................(6) where hvsb is equal to a response to a Hilbert transformer and a high-pass filter which are serially connected. The high-pass filter causes a vestigial sideband to exist in the spectrum of the VSB modulating signal. In the spectrum of the VSB signal adopted in the GA HDTV, the vestigial sideband is 0.31 MHz, and a band at a baseband of the VSB signal is 5.59 MHz. It is therefore apparent that the vestigial sideband occupies a very minute region. It is judged that there is no great error even though the spectrum of the VSB signal approximates to the spectrum of a single sideband (SSB) signal. In such a case, hvsb approximates to Hilbert transform hH . Since the Hilbert transform phase-shifts a signal by 90', the relationship between Xy and Xi is as follows: xγ * hH = xi ..............................................(7) xi * hH = -xγ .............................................(8) If a variation in the I signal of the equation (5) is very slow relative to a variation in o , the following equations are satisfied: xγcos# * hH = xicos# ....................................(9) xisin# * hH = -xγsin# ..................................(10) Consequently, the following result is obtained: I * hH = xicos# + xγsin# = Q ...........................(11) In the phase detecting structure of the PTL 60, the relationship between an actually transmitted signal xγ + + jxi and a signal I + jQ containing the phase error is as follows: (xγ + jxi) e#c = I + jQ ...............................(12) When expanding the above equation (12) for #[n] , then (I + jQ) (xγ - jxi) cos# + jsin# = ......................(13) xγ2 + xi2 In the above equation (13), when expanding only an imaginary part, then xγQ - xiI sin# = .....................................(14) xγ2 + xi2 If # is small, the phase error is given by: o = sinO = XYQ - X11 (15) xγ- + xi However, since a receiving side does not know real values of xγ and xi , an estimated value is used. That is, in the equation (15), if o is small, the I channel signal approximates to a value of xγ . Hence, the I channel signal is used as the estimated value of xγ . When squaring and adding the equations (5) and (11), then I2 + Q2 = xγ2 + xi2 ......................................(16) The estimated value a i of Xi is obtained by the following equation (17):

From the equation (17), if 6 is small, since Q approximates to Xi , #i is selected so as to have the same sign as the Q. That is, #γ = f ...................................................(18)

The expression of the phase error becomes the equation (15). A phase error signal is obtained using the equation (15) and accumulated in an accumulator 67. A sine and cosine table ROM (read-only memory) 68 supplies sine and cosine values corresponding to an average value of the accumulated phase error signal to a complex multiplier 65 and eliminates a vestigial phase component by repeating the above process. The most important factor determining the performance of the PTL 60 is a method for detecting a phase difference between the input signal and the output signal of the PTL 60.

The above-described phase tracking loop circuit has a shortcoming in that unreal assumption in the phase detecting algorithm is made. Moreover, since only the I value is used to determine X, , a linear operating range of phase detection is limited according to a determined error, resulting in performance deterioration. Further, although an accumulation limited value is multiplied by the input signal (i.e. the I data) to compensate for amplitude distortion caused by the vestigial phase, the amplitude compensation has delay for an actual error due to delay of the digital filter 63.

An example of another phase tracking loop circuit for overcoming these problems is disclosed in Korea Patent Application No. 95-5265, assigned to the same assignee as the present invention. In the above Patent Application No.

95-5265, the phase error is detected by the following equations (20) and (21). Figure 3 is a scattering line diagram for an input signal of the phase tracking loop circuit disclosed in the above Patent Application No. 955265. o = ATAN(Ie/O//) (20) Ie = I// - f ....................................................(21) Whereas only 1" is used to obtain 1e in Figure 2, the above Patent Application No. 95-5265 uses I and Q" as shown in Figure 3. That is, Is is determined by calculating a slope indicated by an oblique line. While a fixed determining region is apt to make a wrong decision at a small vestigial phase error, a determining error can be reduced with an adaptive determining region by obtaining the slope at a given number of data.

However, the above-described phase detecting method and phase tracking loop circuit still have a disadvantage in that the digital filter for estimating the Q value should be accurate since the Q value has an important role in detecting the phase error as expressed by the equations (19) and (20). Further, since a construction or algorithm for processing ATAN etc. should be added, the system is complicated.

It is therefore an aim of embodiments of the present invention to provide a phase detecting method of a digital vestigial sideband modulation communication device which is not sensitive to a Q channel value.

It is another aim to provide a phase tracking loop circuit which simplifies a hardware construction and is not sensitive to a Q channel value.

It is still another aim to provide a phase tracking loop circuit to operate by the symbol of an input data channel in a phase detecting method of a digital vestigial sideband modulation communication device.

It is still yet another aim to provide a phase tracking loop circuit for tracking a phase by the block of an input data channel in a phase detecting method of a digital vestigial sideband modulation communication device.

In accordance with one aspect of the present invention, a phase detecting method of a digital vestigial sideband modulation communication device includes the steps of: digital-filtering I channel data applied from the exterior to restore Q channel data; compensating for a phase of the I and Q channel data by a prescribed phase error value; estimating an I channel level value which approximates to the I channel data from the phasecompensated I channel data; and obtaining a difference between the phase-compensated I channel data and the I channel level value, and generating as the phase error value an operation value obtained by multiplying the difference by a sign of the Q channel data.

Preferably, the method further comprises the step of: receiving said phase error value to generate a phase error value eliminating an isolated point by nonlinear processing according to the following equation: #n,med/ =#n-1,med/ + med(#n-k/, #n-k-1,....,#n-1, #n) where #n,med/ is a phase error value eliminating an isolated point, an is a phase error value detected at a current symbol rate, and k is an arbitrary constant.

According to a second aspect, there is provided a phase tracking loop circuit of a digital vestigial sideband modulation communication device comprising: filtering and delaying units for filtering input I channel data, restoring a first Q channel data, delaying said input I channel, and outputting said delayed I channel data; a first multiplying unit for complex-multiplying said delayed I channel data and said first Q channel data by sine and cosine values to generate first I channel data and second Q channel data, respectively; a second multiplying unit for multiplying said first I channel data by an accumulation limited value, and outputting second I channel data whose gain is adjusted; an estimating unit for receiving said second Q channel data and said second I channel data outputted from said second multiplying unit, respectively, and generating an I level estimated value which approximates to said second I channel data in response to a vestigial phase error; a phase error determining unit for receiving said I level estimated value, said second I channel data and said second Q channel data, and determining a phase error value corresponding to a difference between said second I channel data and said I level estimated value according to the direction of said second Q channel data; a first dividing unit for dividing said phase error value by a first divisor to generate the divided value as a phase error value; a sine and cosine table storing unit for supplying sine and cosine values corresponding to said phase error value to said first multiplying unit; a second dividing unit for dividing said phase error value by a predetermined second divisor to supply the divided value as a vestigial phase error to said estimating unit; and an accumulation limiting unit for receiving said I level estimated value and said second I channel data, and supplying as a preset limited value a value obtained by subtracting said I level estimated value from said second I channel data to said second multiplying unit.

Preferably, said phase error determining unit determines a phase error value according to the following equation: o = SGN(Q") (I" - f) where Q/l is second Q channel data, IN is second I channel data, and f is an I level estimated value.

Preferably, the circuit further comprises: an accumulating unit for accumulating said phase error value of a prescribed number received from said first dividing unit to supply the accumulated value as a phase error value to said sine and cosine table storing unit.

Preferably, said second dividing unit has a second accumulating unit for accumulating a phase error o of N symbols outputted from said phase error determining unit, as expressed in the following equation and outputting a phase error value corresponding to said received data block, and a dividing unit for dividing said phase error value of said accumulated block by a second divisor and outputting a vestigial phase error value: Output of said second accumulating unit = (I//- .

Preferably, said estimating unit operates said vestigial phase error value of the block outputted from said dividing unit, as expressed in the following equation, and then provides said vestigial phase error of said estimated block to said accumulation limiting unit: -SGN(I//)α(I//-f) where is a constant related to a band width for phase compensation.

Preferably, said accumulation limiting unit has an accumulating unit for accumulating and symbol-delaying said phase error value of a prescribed number received from said estimating unit, and limiting unit for limiting said symbol-delayed accumulation value to the range of preset downward and upward threshold to supply the limited value to said second multiplying unit.

Preferably, said digital filtering unit is Hilbert transform digital filtering unit.

Said accumulation limiting unit may have an accumulation range and a reference value, receives said I level estimated value and said second I channel data, calculates a subtraction value obtained by subtracting said I level estimated value from said second I channel data, generates as said accumulation limited value a value within said accumulation range which is the most approximate value to said subtraction value when an absolute value of said I level estimated value is above said reference value, and generates said subtraction value as said accumulation limited value when said absolute value of said I level estimated value is under said reference value.

According to a third aspect, there is provided a phase tracking loop circuit of a digital vestigial sideband modulation communication device comprising: a digital filtering unit for Hilbert transform filtering input I channel data to restore first Q channel data; a delaying unit for delaying said input I channel data during a filtering time of said digital filtering unit to generate first I channel data; a first multiplying unit for complex-multiplying said first I channel data and said first Q channel data by sine and cosine values to generate a second I channel data and second Q channel data, respectively; a second multiplying unit for multiplying said second I channel data by an accumulation limited value; an estimating unit for receiving said second Q channel data and said second I channel data from said first and second multiplying unit, respectively, and generating an I level estimated value which approximates to said second I channel data in response to a vestigial phase error; a phase error determining unit for receiving said I level estimated value, said second I channel data and said second Q channel data, and determining a vestigial phase value corresponding to a difference between said second I channel data and said I level estimated value according to the direction of said second Q channel data; a first dividing unit for dividing said vestigial phase value by a first divisor to generate the divided value as a phase error value; an accumulating unit for accumulating said phase error value of a prescribed number from said first dividing unit to supply the accumulated value as a phase error value to said sine and cosine table storing unit; a sine and cosine table storing unit for supplying sine and cosine values corresponding to said phase error value to said first multiplying unit; a second dividing unit for accumulating said vestigial phase value of a prescribed number and dividing the accumulated value by a second divisor to supply the divided value as a vestigial phase error to said estimating unit; and an accumulation limiting unit having an accumulation range and a reference value, for receiving said I level estimated value and said second I channel data, calculating a subtraction value obtained by subtracting said I level estimated value from said second I channel data, generating as said accumulation limited value a value within said accumulation range which is the most approximate value to said subtraction value when an absolute value of said I level estimated value is above said reference value, and generating said subtraction value as said accumulation limited value when said absolute value of said I level estimated value is under said reference value.

In accordance with another aspect of the present invention a phase tracking loop circuit of a digital vestigial sideband modulation communication device includes: a digital filter for digital-filtering input I channel data to restore first Q channel data; a delayer for delaying the input I channel data during a filtering time of the digital filter to generate I channel data; a first multiplier for complex-multiplying the I channel data and the first Q channel data by sine and cosine values to generate first I channel data and second Q channel data, respectively; a second multiplier for multiplying the first I channel data by an accumulation limited value and for outputting the second I channel data in which the Q channel filtering imperfectness and amplitude distortion are compensated; an estimator for receiving the second Q channel data and the second I channel data from the first and second multipliers, respectively, and generating an I level estimated value which approximates to the second I channel data in response to a vestigial phase error; a phase error determiner for receiving the I level estimated value, the second I channel data and the second Q channel data, and determining a phase error value corresponding to a difference between the second I channel data and the I level estimated value according to the direction of the second Q channel data; a first divider for dividing the phase error value by a first divisor to generate the divided value as a phase error value; a sine and cosine table ROM for supplying sine and cosine values corresponding to the phase error value to the first multiplier; a second divider for accumulating the phase error value of a prescribed number and dividing the accumulated value by a second divisor to supply the divided value as a vestigial phase error to the estimator; and an accumulation limiter for receiving the I level estimated value and the second I channel data and supplying as the accumulation limited value a value obtained by subtracting the I level estimated value from the second I channel data to the second multiplier.

The invention includes an HDTV signal receiver comprising a phase tracking loop circuit in accordance with any of the aspects of the invention herein described as well as television or VTR apparatus including such an HDTV signal receiver.

For a better understanding of the invention, and to show how embodiments of the same may be carried into effect, reference will now be made, by way of example, to the accompanying diagrammatic drawings, in which: Figure 1 is a block diagram illustrating a GA-HDTV receiver proposed by GA-HDTV group of U.S.A.; Figure 2 is a block diagram illustrating a conventional phase tracking loop circuit proposed by the GA-HDTV group; Figure 3 is a diagram illustrating a scattering line for an input signal of another conventional phase tracking loop circuit of Figure 2; Figure 4 is a block diagram illustrating a phase tracking loop circuit according to one embodiment of the present invention; Figure 5 is a detailed block view according to one embodiment of an accumulation limiter shown in Figure 4; and Figure 6 is a block view of a phase tracking loop circuit according to a further embodiment of the present invention.

In the following description, the specific details are set forth to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without these specific details. In other instances, well known features have not been described in detail so as not to obscure the present invention.

Referring to Figure 4, a digital filter 310 Hilbert transform filters an input I channel data to generate first Q channel data, for example, Q channel data, which is different from the I channel data in its phase. A delayer 320 delays the input I channel data during a filtering time of the digital filter 310 to generate I channel data. A complex multiplier 330 complex-multiplies the I and Q channel data generated from the delayer 320 and the digital filter 310 by sine and cosine values corresponding to a phase error detected by a phase tracking loop to respectively generate phase-compensated first I channel data and second Q channel data, for example, Z channel Uata and Q" channel data. A multiplier 340 multiplies the I" channel data by an accumulation limited value and compensates for Q channel filtering imperfections and amplitude distortion to generate the second I channel data, for example, the I" channel data.

An estimator 350 receives the Q" channel data from the complex multiplier 330 and the I" channel data from the multiplier 340, and estimates an approximate I level value I of the I" channel data from a proportional value of a vestigial phase error to generate the f , the I" channel data and the Q" channel data. A vestigial phase detector 360 detects a vestigial phase value approximate I level value f and the I" channel data from the estimator 350 to generate an operation value of (I" - f) as an accumulation limited value, and limits the accumulation limited value to an approximate value within a preset limited range (for example, 0.8-1.2) when an absolute value of the I" channel data is over a preset level (for example, over 6).

In the above description, the second divisor "R' is an adjusted value for adjusting sensitivity of the vestigial phase value 8 .

The operation of the illustrated embodiment of the present invention will be explained hereinafter with reference to Figure 4.

Generally, in the GA HDTV, a received signal is demodulated by using the FPLL 20 shown in Figure 1. In the demodulation step, a vestigial phase component is generated according to a phase error between a received carrier wave and a carrier wave generated from the FPLL 20. The vestigial phase component distorts a demodulating signal generated in the demodulation step. A signal demodulated by the FPLL 20 is converted to a digital signal by a data symbol rate through the A/D converter 30 driven by the STR 40. The converted digital signal is supplied to the phase tracking loop circuit through the equalizer 50.

Since an input signal supplied to the phase tracking loop circuit is only an I channel signal, Q channel information is needed to extract phase information and compensate for a phase error. In order to restore the Q channel signal from the I channel signal, the I channel signal and the digital filter 320 which is a Hilbert transform filter are used. The digital filter 310 Hilbert transform filters the I channel data received from the equalizer 50 to restore the Q' channel data. The delayer 320 delays the I channel data received from the equalizer 50 during the filtering time of the digital filter 310 to generate the I channel data. The complex multiplier 330 of Figure 4 complex-multiplies the I" channel data and the Q' channel data respectively generated from the delayer 320 and the digital filter 310 by the sine and cosine values corresponding to the phase error detected by the phase tracking loop, to generate the phase-compensated channel data and Q" channel data, respectively. That is, the complex multiplier 330 compensates a phase through subtraction of the I channel input signal passing through the delayer 320 and the sine and cosine values generated from the phase tracking loop circuit by use of the Q' channel data. The multiplier 340 connected to one output node of the complex multiplier 330 multiplies the Ij channel data by the accumulation limited value received from the accumulation limiter 420 to compensate for the Q channel filtering imperfectness and amplitude distortion.

The compensated I" channel data column is supplied to a decoder and deinterleaver 70 shown in Figure 1. The estimator 350 receives the Q" channel data from the complex multiplier 330 and the I" channel data from the multiplier 340, and estimates the approximate I level value f of the I" channel data from the proportional value of the vestigial phase error to generate the approximate I level value f , the I" channel data and the Q" channel data. Accordingly, there are outputted the I channel estimation level value, the III channel data, and the Q" channel data from the estimator 350. The vestigial phase detector 360 detects the vestigial phase value o from the approximate I level value f outputted from the estimator 350, the I" channel data and the Q" channel data.

In the preferred embodiment, snce the phase detecting method uses only the direction of the Q channel value generated by the hilbert transform filtering, even if the digital filter is not accurate, there is no effect on the performance. The phase error is obtained by the following equation (22): # = SGN(Q//) (I// - f) ..................................(22) In the equation (22), the phase error is obtained only by an error for a decision value of the I channel signal and the direction of the Q" channel data filtered through the digital filter 310. The equation (22) can be simplified by the following equation (23) according to another embodiment of the present invention: # = SGN(Q//) SGN(I// - f) ...............................(23) Thus, since only the direction of the I" and Q" channel data is used, the hardware construction can be more simplified.

The first divider 370 divides the vestigial phase value obtained by the equation (22) or (23) by a divisor M, 30 for example, so as that the phase tracking loop does not diverge, to generate the phase error value. The first accumulator 380 accumulates the phase error value generated from the first divider 370 to supply the accumulated value to the sine and cosine table ROM 390.

The sine and cosine table ROM 390 has the sine and cosine values corresponding to each phase and supplies the sine and cosine values corresponding to the accumulated value generated from the first accumulator 380 to the complex multiplier 330. Meanwhile, the first accumulator ta: receives the phase error o from the vestigial phase detector 360. The phase error o is multiplied by a gain a (a < 1) and then added to a previous output value e = #n-1/ + 8n (24) &alpha;=1/M In the equation (24), a is a value related to a bandwidth for phase compensation and is also used for adjusting gain. The second accumulator 400 accumulates the vestigial phase value 8 of N symbols from the vestigial phase detector 360 and provides the input value to the second divider 410, as shown in the following equation (25).

Output of the second accumulator = # ....(25) The second divider 410 divides the accumulated value generated from the second accumulator 400 by the second divisor (N-R) and supplies the divided value as the vestigial phase error to the estimator 350. As accumulated in the above equation (25), the estimator 350 multiplies the vestigial phase error value divided as the second divisor by a value "-SGN(I")" to provide the vestigial phase error value estimated like the following equation (26) to the accumulation limiter 420: -SGN(I//)ss#(I//-f) ........ (26) where ss is no 1 NR The accumulation limiter 420 receives the vestigial phase error value of the I level value f and the I" channel data from the estimator 350 to generate an operation value of (Ill - f) as the accumulation limited value, and limits the accumulation limited value to an approximate value within a limited range (for example, 0.8-1.2) when an absolute value of the I" channel data is over a preset level (for example, over 6). The construction of such a second accumulation limiter 420 will be definitely understood by Figure 5.

Figure 5 is a detailed block view of the accumulation limiter shown in Figure 4. Referring to Figure 5, the estimated vestigial phase value outputted from the estimator 350, as shown in the equation (26), is inputted to one terminal of a third accumulator 422 of Figure 5.

The I channel data whose output level is limited by a limiter 426 is inputted to the other input terminal of the third accumulator 422. The third accumulator 422 accumulates the two input signals and outputs the signals to the symbol delayer 424. The symbol delayer 424 delays the input signal by the unit of symbol to output the signal to the limiter 426. The limiter 426 limits an absolute value of an output I channel data from the symbol delayer 424, i.e., a preset downward threshold value THL and a upward threshold value THH (for example, the values THL and THH are established as 0.8 and 1.2, respectively, when the absolute value of the I" channel data is over 6).

Then, the limiter 426 provides the value to the multiplier 340. That is, the accumulation limiter 420 limits an accumulation value to an approximate value of the preset value when the absolute value of the I" channel data is at a level of a maximum value, and then outputs the value to the multiplier 340.

In the above description, the direction of the input signal has been mainly used to simplify the hardware construction. However, the phase error o can be optimized to the following equation (27) to raise the reliability of the construction under an inferior channel circumstance with impulse noise.

#n,med/ = #n-1,med/ + med(#n-k/, #n-k-1,....,#n-1, #n) ............(27) where "med" is an intermediate value select function, and 6n,n?ed is a phase error eliminating an isolated point. That is, the phase error values en-* - #n of k symbols are obtained by the equation (22) or (23), and the isolated point is eliminated by nonlinear processing as expressed by the equation (27), thereby preventing an abnormal operation of the PTL 60. In the above equation (27), k is an even number. When k is 0, the equation (22) or (23) is satisfied. In the equation (27), on is the phase error value detected at a current symbol rate.

In the description of one embodiment of the present invention, the second accumulator 400 accumulates the vestigial phase values o of N symbols outputted from the vestigial phase detector 360, and then processes it by the unit of the block. However, the vestigial phase values can be processed by the unit of the symbol and its processing step is as follows.

If the second accumulator 400 shown in Figure 4 is deleted and the vestigial phase detector 360 is directly connected to the second divider 410 to thereby make a path 402, the data value inputted to the second divider 410 from the vestigial phase detector 360 becomes # (I//-f) At the moment, the second divider 410 divides the data E (I//-In by the second divisor N#R and outputs the divided value to the estimator 350 as the vestigial phase error. As mentioned above, if the vestigial phase value is processed by the unit of the symbol, an alphabet "N" in the divisor " N'R " must have a value of 1. The estimator 350 multiplies the vestigial phase error divided in the second divider 410 by the value of -SGN(I") to provide the estimated vestigial phase value to the accumulation limiter 420.

-SGN(I11)y(I11-1) (28) The accumulation limiter 420 accumulate-limits the level of the vestigial phase error value like the equation (28) and provides the value to the multiplier 340, so that it can be known that the phase tracking is executed by the unit of the symbol.

Figure 6 is a block view of a phase tracking loop circuit according to the other embodiment of the present invention. Constructions of Figure 6 are the same as those of Figure 4, except a fact that the input/output terminal of the multiplier 340 is disposed between the input line of the I channel data and the input terminals of the digital filter 310 and the delayer 320. Figure 6 is constructed to perform an operation of the phase tracking after gain of the I channel data is adjusted by the output of the accumulation limiter 420. Further, according to the construction of Figure 6, other values except the sine value are used as gain of the Q channel data.

It should be noted that the vestigial phase value o which is outputted from the vestigial phase detector 360 according to a selective connection of the second accumulator 400 and the path 402, is processed by the unit of the block or the unit of the symbol, to thereby perform the operation of the phase tracking.

As described above, since the phase error is obtained only by the direction without estimating the accurate Q value, the accurate digital filter is not needed. The hardware construction can be simplified by using only the direction of the I and Q values. There is no need to have an ATAN operating circuit or algorithm.

The reader's attention is directed to all papers and documents which are filed concurrently with or previous to this specification in connection with this application and which are open to public inspection with this specification, and the contents of all such papers and documents are incorporated herein by reference.

All of the features disclosed in this specification (including any accompanying claims, abstract and drawings), and/or all of the steps of any method or process so disclosed, may be combined in any combination, except combinations where at least some of such features and/or steps are mutually exclusive.

Each feature disclosed in this specification (including any accompanying claims, abstract and drawings), may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise. Thus, unless expressly stated otherwise, each feature disclosed is one example only of a generic series of equivalent or similar features.

The invention is not restricted to the details of the foregoing embodiment(s). The invention extends to any novel one, or any novel combination, of the features disclosed in this specification (including any accompanying claims, abstract and drawings), or to any novel one, or any novel combination, of the steps of any method or process so disclosed.

Claims (4)

1. CLAIMS 1. A phase detecting method of a digital vestigial sideband modulation communication device comprising the steps of: digital-filtering I channel data applied from the exterior to restore Q channel data; compensating for a phase of said I and Q channel data by a prescribed phase error value; estimating an I channel level value which approximates to said I channel data from the phasecompensated I channel data; obtaining a difference between said phase-compensated I channel data and said estimated I channel level value, and generating as the phase error value an operation value obtained by multiplying said difference by a sign of said Q channel data; and receiving said phase error value to generate a phase error value eliminating an isolated point by nonlinear processing according to the following equation: #n,med/ = #n-1,med/ + med(#n-k, #n-k-1,...., #n-1, #n) where enmed is a phase error value eliminating an isolated point, on is a phase error value detected at a current symbol rate, and k is an arbitrary constant.
2. 2. A phase detecting method substantially as herein described with reference to Figure 4, 5 and 6.
3. 3. An HDTV signal receiver utilising a phase detecting method according to any of the preceding claims.
4. 4. Television or VTR apparatus including an HDTV signal receiver in accordance with claim 3.