GB2292501A - Frequency hopping - Google Patents

Abstract

A frequency hopping digital communications transceiver operates at a 50% duty cycle with data and synchronising information transmitted during one half cycle and carrier frequency changing during the other. The transceiver generates a stream of correlation words related to the time-of-day, the correlation words being used for synchronisation and for determining the selection of frequencies during data transmission. Input data is connected via a buffer 11 to a data formatter 15 where it is interleaved on being read out in data frames via a switch 29 to the radio transmitter 35. Time-of-day code-words from a generator 20 are connected via a controller 12 to a frequency hop controller 30 and a time-of-day request and reply generator 28. A digital phase locked loop is provided in a bit synchroniser (44) in the receiver. The data frames may be time-shared between several users allowing common use of the transceiver aerial and associated circuitry. <IMAGE>

Description

TITLE: Improvements in or relating to Radio Communications This invention relates to radio communications, and in particular to digital radio transceivers adapted for use in a noisy environment and/or an environment subject to third part frequency jamming.

Frequency hopping is a well known technique for reducing the effects of jamming on radio communications, ar.d a number of communications systems have been developed exploiting this technique One known system in the UHF band employs Slow Frequency Hopping with relatively long dwell times on a given frequency.

With today's technology a follower jammer, (ie a frequency agile jammer which transmits in a instaneous narrow band and follows the frequency hopping pattern of the radio) can set on and jam for a sufficiently high fraction of the dwell time to negate the effectiveness of the frequency hopping.

In this system synchronisation, (ie tuning radio transmitters and receivers to the correct frequency at the appropriate times) is achieved by using only real-time clocks. Hence alien a radio tunes from one frequency to the next a short interruption occurs in the communication due to radio retune times, relative clock errors and propagation delays. The system has no provision to retrieve the information lost during these inter ructions since the system was designed for unencrypted analogue voice and is not really suitable for encrypted voIce. This is a grave disadvantage for military communication where message security is of prince importance.

The not system provides only a single voice channel per radio. In many locations several concurrent voice circuits are required, and i.t will be necessary to use one radio for each circuit vith each radio using its own dedicated aerial. It is not possible to meet this requirement in many situations (on ships, for example). .

Further, the system has inbuilt only one set of frequencies and some form of integrated random process for selection of frequency to be used from this set. There is no facility for changing the set of frequencies to be used or the method of selection. This raises problems for frequency planning, when interferance with other uscrs in the UNF band is to be avoided.

The object of the present invention is to provide a communications system with improved immunity from jamming.

The invention comprises a digital radio transceiver to form part of a frequency hopping communications system wherein there are pseudo-random changes of transmission frequency, the transceiver comprising:- a) a radio transmitter; a means for buffering message data for transmission; a means for selecting an output frequency hopping sequence common to the communications system; a means for controlling the transmitter such that the buffered data are transmitted in frames with the frames separated by quiescent periods during which the transmission frequency changes occur; a master clock adjustable to adequate synchronisation with a given datum; and a means for synchronising transmissions with the master clock; and b) a radio receiver; means for operating the transceiver in a frequency hopping sequence common to the communications system when used in the receiver mode; synchronising means for synchronising reception with a remote transmitter's master clock; and a message output means to reconstitute the transmitted message from the received signal.

Preferably the system uses fart frequency hopping with a 50% duty cycle. Because of the data buffering, communications inforration is then transmitted at a high data rate in single frequency frames with frequency changes occurring when the cata iE rot being transmitted. thus a receiver cal!, ir principle, completely reconstitute the original communication information.

In practice this makes the system suitable not only for data but also for digitised encrypted voice using Vinson - Lamberton coding.

In addition, by adopting short dwell times on each frequency, jamming of the system is made difficult since a jammer would need to have a very fast response time and also be close to the communications circuits otherwise radio propagation delays would make jamming impossible.

The buffering means may be arranged for single channel operation or for multichannel operation. Conveniently four channels are used with each transmission data frame being divided for sequential channel transmission. By this means four completely independent and non-interfering voice (or data) circuits can be supported using a common aerial.

In an advan+,ageous arrangement the buffering means receives a continuous digital data stream and includes means for formatting this data in an interleaving array and provides at an output thereof bursts of interleaved data coinciding with the transmission data frame times. This interleaving of the transmitted data ensures that a temporal block in transmission does not correspond to the loss of a block of data: the lost data will be distributed in time when the received transmission is deformatted. This further reduces the vulnerability of Vinson-Lamberton coded voice transmission to certain types of jamming.

The transmission synchronising means preferably includes a means for selecting correlation words using a pseudo-random process related to the time of day given by the master clock and a means for formatting the correlation words such that one complete word is transmitted during each data frame. Advantageously there is included a means to select when synchronisation transmissions are to be made to provide re-able, message continuing indications and post-amble transmissions.

The receiver synchronising means preferably includes a means for locking the phase of a locally-provided clock with the phase of the received data stream. There is also included in the preferred arrangement a means for continually monitoring the received data stream to detect valid correlation words and to determine from the instances of valid correlation word reception whether a valid synchronisation transmission is being received.

The transceiver master clock giving the time of day is normally coarsely synchronised to a reference time datum, normally GMT.

Preferably there is included a means whereby a master clock can be accurately aligned with the master clock in a remote transceiver.

The transceiver advantageously includes means to transmit a coded signal requesting timing refinement and including the transmitter time-of-day and means to adjust the master clock on receiving a response. The receiver of the transceiver advantageously includes a means for detecting a coded signal requesting timing refinement and means to actuate transmission of a signal indicating the time difference between the master clock and the master clock of a remote requesting transceiver. Advantageously there may be provided two modes for refinement of master clock timing, one for relatively fine adjustments up to + 0.2 msec and one for relatively coarse adjustments up to # 1 sec.If a transceiver fails to achieve synchronisation following a timing refinement request it can change to the second mode by transmitting a request for synchronisation using a second code.

The transceiver advantageously includes a clock which incrementally adjusts the timing of successive synchronisation request signals in steps of 0.2 msec throughout the 1 sec period of uncertainty until a synchronised response is received from a remote transceiver indicating the time difference (to within - 0.2 msec) between the clocks of the to transceivers.

preferably the stream of time-of-day code words produced by the pseudo random generator for synchronisation purposes is also connected to a frequency synthes5ser so as to select from the range of frenuercies available a different output transmission frequency corresponding to each code word. The set o,f output codewords pnd hrrce the set of frequenc'c.s used for the frequency hopping communication can be programmed so as to be able to define separate communication networks within the system.The system security is enhanced since all synchronisation transmissions: pre-ambles, postambles, time-of-day refinement requests etc are carried out in a frequency hopping mode. A separate network, ie pattern of frequency hopping, may be assigned to request and to look for transceivers requesting synchronisation when the time-of-day of the requester is only accurate to + 1 sec.

In order that the invention might, be more fully understood, one embodiment thereof will no be described, by way of example only, with reference to the accompanying drawings, in which: Figure 1 is a functional block diagram of equipment for controlling communication transmissions in accordance with the invention; Figure 2 is a functional block diagram of equipment for controlling communication reception in accordance with the invention; Figure 3 is a functional block diagram of a user data buffer circuit used in the arrangement of Figure 1; Figure4 is a functional block diagram of a unit for formatting data for transmission and deformating received data;; Figure 5 is a functional block diagram of a synchronisation generator used in the arrangenient of Figure 1; Figure 6 is a functional block diagram of a unit for generating. replies to tine of day (TOD) refinement and late entry requests, Figure 7 is a functional block dierari of a transceiver frequency hdn controller; Figure 8 is a functional block diagram of a codeword generator and store; Figure 9 is a functional block diagram of a controller for the equipment of Figures 7 and 2; Figure 10 is a functional block diagram of a bit synchronisation unit incorporated in the equipment of Figure 2; Figure 11 illustrates waveform synchronisation by the bit synchronisation unit of Figure 10;; Figure 12 is a functional block diagram of a receiver synchronisation detector; Figures 13 and 14 arc circuit diagrams of the units shown in figure 12; and Figure 15 shows circuitry and waveforms for a four-channel transceiver unit.

Referring to Figures 1 and 2, there is schematically shown the transmitter (Tx) and receiver (R ) control sections of a x transceiver unit. Although several units are common to both T and R where appropriate they are illustrated on both x Figures 1 and 2 and in later drawings for ease of description.

In Figure 1, a user unit 10 comprising a 16 Kbps data generator (not shown) is connected to a user data buffer 11 b a data line and a clock line which supplies a 16 KH clock in phase with the dicta. the unit 10 is also connected to a controller 12 by a line 13 iccatin whether or not the unit 10 requires to transmit (press-to-talk (PTT) operation). If the user unit 10 supplies analogue speech then the user data buffer 11 includes a " Continuouslg Variable Slope D@lta" (CVSD) modulator (not shown) to convert the analogue leech input into a 16 Kbps (kilobits per second) data stream. The user data buffer 11 is connected via a data transmission line 14 to a data formatter unit 15.

The controller 12 supplies the user data buffer store 11 with a 16 KH clock in phase with a Master Clock 18 via a line 16.

The controller 12 receives a 7 bit binary net number allocated to the communications network of interest from a net unit 17. The Master clock 18, accurate to within 0.2 msec of Greenwich Mean Time (GMT) and synchronised to a 1OMHz standard clock 19, supplies one pulse per second to the controller 12.

The controller 12 also receives a 10MHz signal from the standard clock 19. The controller 12 supplies TOD (Time of Day) information to a TOD codeword generator 20, which supplies a 15 bit binary codeword to a codeword store 21 and thence to the controller 12 via a call forward clock line 22 and a codeword supply line 23.

The controller also supplies a 500 Fz signal to the codeword generator 20 via line 24.

The controller 12 has an output bun 25 for supplying codewords and timing and control signals described later to the data formatter unit 15, a synchronisation generator 26 with associated sixteen-word RUl store 27, TOD refinement and late entry reply generator 2 , a transmission output select switch 29 and a frequency hop controller 30.The date formatter unit 15, synchronisation generator 26, TOD refinement and late entry reply generator 28 are connected to respective input terminals 31, 32 and 33 of the output select switch 29, which has an output terminal 34 connected via a modulator 35 to a radio transmitter 36 and aerial 37. The transmitter 36 is also connected to the frequency hop controller 30 for output frequency control and to the controller 12 for frequency change timing(39) and an indication (PTT) of whether or not the user unit 10 requires to transmit.

Referring now to Figure 2, a radio receiver 40 Is connected to an aerial 41 and its output is connected to the demodulator 35(as in Tx).

Thr frequency for reception b the receiver 4o iU controller by the frequency hop controller 30 and timing is supplied by the controller 12 via the frequency change timing line. The demodulator 35'is connected to a synchronisation detector 43, a data deformatter 46, and a bit synchronisation unit 44.The bit synchronisation unit 44 derives a 35 KHz clock in phase with the received 35 Kbps data, and this clock is supplied to the synchronisation detector 43 and the controller 12.TheSynchronisation detector 43 has an associated sixteen-word store 47 ( 27 in Figure 1). Operation of the frequency hop controller 30, synchronisation detector 43 and data deformatter unit 46 is controlled by the controller 12 connected thereto by a bus 49, the signals on this bus being described later. The operation of the TOD codeword generator 20, codeword store 21, the clocks 18 and 19 and the net unit 17 are the same as described for Figure 1 above.

The user unit 10 receives data from the data deformatterunit 46, either directly or via a lot-pass filter (not shown) if analogue speech is being used.

Figures 3 to 15 show in greater detail individual elements of the functional block diagrams of Figures 1 and 2. The user data buffer circuit 11 of Figure 1, is shown in Figure 3. The 1G :bps data stream from a user unit 10 is fed to an input switch pointer 60 contacting each of 32 contacts 61 in turn. The pointer 60 is clocked cyclically through the contacts 61 by the 76 KHz clock signal from the user unit 10, so that respective bits of the data stream overwrite the data held in respective locations of a 32 bit store 62.

From the store 62 the data bits pass to 32 contacts 63 arranged around an output switch pointer 64. The controller 12 of Figure 1 provides a 16KHz clock for clocking the output pointer 64 through the contacts 61 to read data from the store 62. The nput pointer 60 and output pointer 64 have reset arrangements (not shown) which eifect an initial 16 location offset between the two pointers.

Thus the input 16 Kbps data stream and the 16 KH clock used for output pointer control derived from the equipment clocks IS and 19 in Figure 1 man drift up to 16 clock c;lcles (of 16 Kops) with respect to each. other before conflict occurs.

The reset arrangements operate whenever the user unit 10 activates the press-to-talk (PTT) line.

Referring now to Figure4 , this shows the functional block diagram of the data formatter unit 15 (Figure 1). Data at 16 Kbps is fed along a line 70 alternatively to one of two random access memories (RAMs) 71 and 72. The RAMs 71 and 72 have respective row address units 73 and 74 and respective column address units 75 and 76. The address units 73 to 76 are controlled via buses 77 and 78 by a memory logic controller 79. The controller 12 of Figure 1 supplies via lines 80 a range of timing signals to the memory logic controller 79, as listed in Figure 4. The RAM outputs 82 and 83 are connected in turn via an OR-gate 84 to a single output 85 leading to the switch 29.In operation data is first clocked into RAM 71 row by row at 16KHz via line 70 from the user data buffer 11; the first twenty-three data bits are written into row 1, the second twenty-three into row 2 and so on until 800 bits have been read into the RAII forming a 23 x 35 bit array (except for the last 5 bits of row 35).

Once this array is full, the data is clocked out at 35 Kbps column by column, thus interleaving the data for security and effecting readout of each column in lmsec. After each column is read out, the 35 Kbps is low or quiescent for a further Ims, so that each Ims burst or column of data is separated by Ims from that preceding. After the 23 x 35 data bit array has been read out in full from RAM 71, further data is then read into The 71. Simultaneously with reading out the data from RXi 71 data is fed into I?A! 72 and subsequently the procedures are reversed.The time taken to readout completely is 46 msec (23 columns x 2 msec) and tis together with transmission of to "message continuing" hops, as described later, gives a 50 msec data frame.

The received data deformatter operates in a complementary fashion to able data formatter described above. Data is f(d from the demodulator 35 alternatively into the RAs 71 and 72 in bursts of 1 msec and colunn by column, and read out at 16 Kbps row by row. whilst one RS; is being read the other is being filled and thus a continuous 16 Kbps data stream is connected to the user unit 10. Detailed circuit diagrams of the individual circuits incorporated in the formatter and deformatter are not given since these should be apparent to skilled electronic engineers from the foregoing description.

Referring now to Figure 5, the synchronisation generator 26 includes a clock generator 90 having input lines 91 carrying timing signals from the controller 12 as listed on the Figure.

The clock generator 90 is connected to a column select address unit 92 of a 16 x 35 bit RAI! store 27 (see Figure 1) having a row select address unit 94. For initiall,sation purposes only a microprocessor 95 is connected to the column and row address select units 92 and 94 and to the RAM store 27 by respective buses 96, 97 and 98. The micronrocessor 95 is used to store sixteen 24-bit preselected correlation words (prefixed by 11 reversals) entered b an operator via a keyboard and monitor (not shown). The microprocessor 95 then clocks each correlation word plus reversals into a respective row of the RMl store 27 by generating column and row select lines and memory chip enable pulses.The microprocessor contains software for these purposes. Once all sixteen correlation words have been stored, the operator inputs to the microprocessor 95 are disable and the microprocessor 95 ceases to control the RAM @ store 27, which then comes under the control of the clock generator 90 and TOD codeword formatting unit 100 for column and row select purposes respectively. A 4-bit TOD codeword is passed from the controller 12 via unit 101 to the formatting unit 100 here it is formatted into one of the following formats: (a) its original form; (b) its binary complement; or (c) the exclusive-OR product of itself with a fixed code maintained by the formatting unit 100.

The formatting implemented (i.e. (a),(b) or(c)) is selected by the control lines 102 from the controller 12. In this way each TOD codeword is used to provide a row address corresponding to a respective stored 35-bit word. When the TOD codeword changes (nominally at 2 msec intervals) the row address changes.

The sets of row addresses(a),(b) and(c) are employed to provide the preamble (and message continuing indication)1postamble and indicator portions of a message respectively. Thus the 4-bit TOD codeword used to select the correlation word is modified for the preamble, postamble and indicator sections and so aids recognition of these different sections.

The clock generator 90 combines the 35 KHz and 500 Hz signals via an AID gate (not shown) to provide Ims ON, Ims OFF bursts of a 35 K'{z clock to drive the column address select unit 92. This clock is thus used to clock out from the RAtI 27 all thirty-five bits of the correlation word stored in the row addressed by the modified OD 4-bit codeword in 1 msec. The output of the RUl 27 is fed to the switch 29 but is only fed to the modulator 35 when required for transmission preambles, postambles or indicator frames.

Referring now to Figure 6, the TOD refinement/late entry reply generator 28 comprises a central unit 120 identical to the synchronisation generator unit 26 described with reference to Figure 5 with the addition of a witch 195. The central unit 120 receives from the controller 12 timing clock signals via lines 121 as listed in Figure 6 with all clocks being offset in time (phase delay or advance) from the Master Clock by an amount equal to the offset between the clock derived during the fine synchronisation process with the received signal requesting TOD refinement or late entry and the Master Clock.. The central until 120 receives 4-bit TOD codewords corresponding to the offset time via a bus 119 and control signals via a line 122 from the controller 12.A time difference data formatter 123 is connected in line 124 between the controller 12 and the switch 195, which is controlled by the controller 12 via the line 122. The information on line 122 also controls the 4-bit formatter 100 which modifies the TOD codeword used for correlation word selection, as described above.The logic for this selection process and operation of switch 195 is as follows:

Status on Output of hessage type Input to lines 122 4-bit formatter 100 Switch 195 O O Unmodified Preamble 4-bit formatter TOD codeword 100 0 I binary Compliment Postanble 4-bit formatter TOD Codeword 100 1 0 Ex-OR product of Indicator 4-bit formatter TOD codeword with 100 fixed 4-bit Word 1 1 - Time difference Time difference data data formatter 123 The TOt) refinement/late entry reply generator 23 provides replies to requests from remote transceivers for TOD updates. The replies set contain sufficient information, as described later, to allow the requesting transceiver to align its Master Clock to within t 1@sec with the later Clock of the replying transceiver.

The requests for TOD refinement (for adjustments of up to-+ 0.2 msec) and late entry (for adjustments of up to 1 sec) are made un the synchronisation generator 2( described .above, in a format described later. The replies to both types of request are made using the TOD refinement late entry reply generator 29, with format deseribed later, and with all timing hased on clocks offset from the @aster Clock by an amount equal to the time difference between the pilaster Clock and the Clocks derived from the received request signal.These clock offsets are determined by the controller 12, described later, and are passed to the time difference data formatter 123 via lines 124 and thence to the switch 195. The time difference data formatter 123 formats the time offset in a 21-bit binary word (which is a binary representation of the number of 1 tE clock cycles between the waster Clock and the clock derived from the received signal).

Referring now to Figure 7, the frequency hop controller 30 includes an input line 130 initially connected to an external user controlled microprocessor 95 (in Figure 5) for frequency data in the form of 15-bit words which are stored in the 4096 x 15-bit RAM word store 131. A 12-bit address bus 132 is also connected to the microprocessor 95 and word store 131 when a user is initially storing. frequency data. During radio frequency hopping, the address bus 132 is instead fed by 12-bit TOD codewords from the controller 12. The external microprocessor is initially operated to fill the word store 131 with 15-bit words each indicating a respective radio output frequency.

Each frequency word is allocated to a respective 15-bit row of the word store 131 addressed by the external microprocessor.

After this initial setting-up procedure, the microprocessor outputs to the word-store 131 are disabled. 15-bit words from the word store 131 are clocked into the parallel in/serial out shift register 133 via lines 134 using the clocks on lines 135A and 1353 from the controller 12. The 12-bit TOD codeword present on the address bus 132 from the controller 12 is used as the row address for the word store 131 and thus selects the word to be connected to the shift-register 133. The clocks lines 135A and 1353 also control the serial output of the word from the shift register 133 within 2 msec to a radio frequency synthcsiser (not shown) in unit 36 via the line 136.The radio synthesiser responds to each freo.ency word when instructed by the controller 12 via the frequency change timing line, by generating a respective radio transmission frequency in the band 225 to 399.9?5 MHz accurate to -+ 1 KHz of that requested. Each transmission frequency is spaced by 25 KHz in this band, ie each frequency is 225 MHz + 25 MKHz, where i3 = 0. 1. 2 .......... 6999, giving a maximum 7 x 103 possible transmission frequencies. The maximum bandwidth for frequency hopping in a given communications net mey be all or a fraction of the 1?4.975 MHz available, so that in the latter case many nets may be used simultaneously.

Referring now to Figure 8 , the TOD codeword generator 20 and the codeword store 21 are shown, these being common to Tx and Rx. The generator 20 receives TOD information (in terms of number of 500 Hz cycles since a given datum) and 500 Hz pulses (2msec spacing) from the controller 12. In response to these signals the generator 20 produces 500 codewords per second from a pseudo-random number generator (not shown).

All Tx and Rx systems have similar pseudo-random generators producing the same stream of codewords in response to the TOD information, the stream dictating the transmission frequency hopping pattern and correlation word selection as previously described with reference to Figures 5 and 6. Each TOD signal on line 140 to the generator 20 effects insertion of a TOD codeword via a pointer 141 into the 3 x 15 bit codeword store 21. The TCD codewords are fed into the codeword store 21 in parallel using e read in clock on line 142 from the controller 12. The T0D codewords are fed in cyclically, words inserted previously being overwritten, in the sequence 1, 2, , 1, 2, 3 1, 2, 3 .... The codeword store output is a pointer 143 whose etore row position is adjusted by the controller 12 via the call forward clock line 22 (see Figure 1).

The output pointer 143 supplies the output codewerd to the controller 12 via the codeword supply line 23 as shown in Figure 1, Te TOD codewords are read out of the store 21 by an 8 DIz clock on line 144 from the controller 12. The output pointer position relative to the input pointer position is dictated by current Tx or Rx mode of operation. During x transmission and in the search for synchronisation receive mode the codeword inserted into the store 21 et time To -5 is used to derive the transmission frequency for time To, all clocking waveforms being based on coarse synchronisation from the Plaster Clock.When messages are being received or replies are being transmitted to TOD refinement or late entry requests, all clocking waveforms are based on fine synchronisation derived from the appropriate received signals.

Referring now to Figure 9, the controller 12 is shown as employed for control of both T and R of the transceiver.-The 7-bit x x communications net number from the net unit 17 is sent on a controller input line 150 and is used to multiply the 7 least significant bits of the current TOD codeword in a multiplier 151 before the codeword is passed to a 15-bit output bus 152.

The 10 IJiz system standard clock 19 is connected to an input 153B of the controller's system clock derivation section 154, which derives timing and control signals for message transmissions and search for synchronisation operation. These clock signals are necessarily phase-locked to the aster clock 18 accurate to within + 0.2 msec of GMT and are passed to output lines 155.

In the receive mode, received signals indicating preamble detection by the synchronisation detector 43 (Figure 2) and bit synchronisation by the unit 44 pass via respective inputs 156 and 157 to the controller's clock derivation unit 158.

The clock derivation unit 158 generates clock signals finely synchronised to received signals which are routed from the derivation unit 153 via the bus 49. These clock signals are used during reception of mesas and for transmission of TOD refinement and late entry replies.

The controler 12 has a time difference calculator 160 to which the TOD is fed via an input 153A from the Master Clock.

The calculator 160 calculates the degree of offset between the Vaster Clock derived from fine synchronisation with received signals and furnishes this offset information to the time difference formatter 123 of Figure 6. The controller 12 has a 2-bit switch control bus 162A connecting an output switch select control section 162 to the switch 29, the section 162 selecting the terminals 31, 32 or 33 of the switch 29 as appropriate to the current T system function. The codeword output bus 152, x T clock lines 155 and switch control bus 162A are combined x into the single bus 25 of Figure 1. The controller also passes on the PTT (press-to-talk) signal indication from the user unit 10 to the transmitter 36 (but this line is not shown).

Referring now to Figure 10 illllstrating in more detail the bit synchronisation unit 44 of Figure 2, input line 170 carries 35 Kbps data from the demodulator 35 to a phase difference monitor 171. The monitor 171 also receives on line 172 a 700 KNz reference signal derived locally (not shown) from the 10 MHz standard clock 19. The 700 KHz reference signal is also fed on line 173 to a divider 174. The divider 1?4 divides the reference signal by 19, 20 or 21 to provide an approximately 35 KXz signal for output to the synchronisation detector 43 and controller 12 on line 175 and for input at 176 to the monitor 171.

The monitor 171 measures the phase difference between the 35 EEz clock on line 176 and the 35 iAps Rx data signal by determining the number of 700 KHz cycles between edges of the two signals.

The number of 700 KRz cycles counted between edges controls the selection of division factor 19 20 or 21 at the divider 174 to provide the approximate 35 KHz signal from the 700 KHz reference.

With reference now also to Figure 11 if nine or fewer 700 KHz counts (177) are measured, in the time T1 between the edges 178 of the local 35 KHz signal on line 176 and the data signal edges on line 170, the 700 KHz signal is divided by 19. If ten counts are made \ division is by 20, and for greater than ten counts(T3)division is by 21. This process ensures that the derived 35 KHz clock has its positive rising edges near the centre of Rx data bit periods. Division by 19 or 21 results in the next 35 KHz derived clock pulse being one cycle of 700 KHz earlier or later respectively, whereas division by 20 maintains the pulse spacing.In this way the derived 35 }cHz clock is phase advanced, retarded or unchanged as required to maintain its positive risking edge at ten counts from the Rx data signal edge. The bit synchroniration unit 44 acts as a digital phase-locked loop, correcting for initial phase mismatch and any subsequent relative phase drift between the Rx data signal and the 35 KHz derived clock. The phase match or bit synchronisation accuracy is to + 1/20 of a 35 KHz cycle, or + 1.4 microseconds.

Referring now to Figure 12, the synchronisation detector 43 comprises a correlator 180 of known kind connected via a bus 181 to the 16 by 35-bit RAM word store 27 incorporated in the synchronisation generator 26 (Figures 1 and 5). The RAM store 27 operation has been previously described. The RAM store 27 receives a 4-bit TOD codeword on input 182 from the controller 12, which selects the correlation word from those stored in the RA!4 store for supply to the correlator 180.A second input 183 to the RAM store receives clocks derived from the Master Clock (during search for synchronisation) or from the X signal (when synchronisation is detected) as appropriate from the controller 12, these effecting output from the RAM store 27 of the correlation words addressed by the 4-bit TOD codeword on line 182 . The demodulator 35 (sec Figure 2) supplies a received data stream to the correlatorinput line 184, and a second correlator input receives the phase-adjusted 35 KHz clock from the bit synchronisation unit 44 on line 185.

This 35 KHz clock is used to clock the received data stream through the correlator, and on each clock pulse. tests for correlationwith the current correlation word sent on the bus 181.

The degree of correlation at each test initialised by a signal on line 191 is represented by a 6-bit binary number which is sent after each test via a correlation number line 193 to a threshold crowing detector loop 187. The threshold crossing detector loop 187 keeps a running total of the number of correlations detected, as described below, under control provided on line 190, and if the number of correlations exceeds the threshold set up on line 189, then a correlation peak detected pulse is sent out on line 186 to the controller 12.A pulse on this line 126 indicates that a preamble, postamble or indicator frame (as appropriate) has been detected, and in the case of preamble detection also gives the time datum for derivation of all clocks from the received signal (i.e. fine synchronisation) for subsequent reception of the message data.

Referring to figure 13 showing a functional block diagram of the threshold crossing detector loop, C-btt correlation numbers on line 206 are fed to an 8-bit parallel binary adder 197.

A second input 210 to this adder supplies an 0 bit binary word to the adder. An 8 bit bus connects the output of the adder 19? to the date inputs of a RAM 196 via eight AND gates 194 and eight tristate buffers 195,under control of line 205. The RAM parallel data output is fed to the latches 199 on bus 207 and is a]so clocked to the adder 197 by latch clock 201. An bit comparator 200 having a threchold number set up on lines 211 is fed from the adder 197 output.

The operation of the threhold crossing detector loop 1(57 is as follows. In the search for synchronisation mode, there is an uncertainty of - 0.4 msec to + 1.65 msec between the receive signal timing and the taster clock, (based onparameters given later) and the search for a particular correlation word has to extend over this uncertainty window. As described later, preamble transmission can start every 100 msec and at start of a 100 msec frame time given b the waster Clock and preceeding the first uncertainty window the RAM (Figure 13) is initialised by filling every location withzeroesunder control of lines 202, 203, 204 and 205 from the control logic 188 in Figure 12. Following the start of the first uncertainty window in the frame the number held in location 1 of the Rkl is fed out along bus 207 and clocked across latches 199 by clock 201 to the address 197. This number is added to the correlation number on bus 206 and the sum is fed back into location 1 of the RAI. This cycle is then repeated for location 2 in the RAM and all subsequent locations up to the 77th location in tbe RM;. Each cycle takes place within one cycle of the 35 EIz clock generated from the received data stream, as described above, and thus the 77 cycles take 2.2 msec which just exceeds the duration of the uncertainty window.The adder 197 output is continually monitored by a comparator 200 which contains a threshold number and if the adder output exceeds this number a pulse is sent to the controller 12 via line 212 to indicate that a correlation peak has been detected. If a preamble has not been detected in a 100 risec frame, then the Rh'l is initialised again and the procedure repeated. When carrying out this procedure the equipment is said to be n the bearch for synchronisation" mode..

Figure 14 shows a detailed circuit diagram of the control and timing signal generation which is part of the control logic 188(Figure 13) associated with the threshold crossing detector loop 187. Connected to four inputs to the circuit are a squared 35 KHz signal(214)derived from the bit synchronisation circuit output 175 (Figure 10),35 KHz pulses from the line 175, acorrelation window start pulse(215) and 10 Hz pulses(216). The outputs from the circuit carry a 7-bit address 212 for the RAM 209,RAll control signals 202-204 and the AND gate control signal 205.

The data deformatter unit 46 of the Rx of Figure 2 has been described with reference to Figure 4.. Similarly the frequency hop controller 30, the TOD codeword generator 20 and controller 12 of Figure 2 are common to T and R control equipment for the x x transceiver, and have been described with reference to Figures 10/11, 12 and 13 respectively.

The single channel communications control equipment described with reference to Figures 1 to 14 may be extended to operate in a multiplicity of channels as follows. For four channels, for example, the controller 12 requires a data clock of 140 KHz (4 x 35 KHz) to clock data to and from the modulator/demodulator 35. A channel gating signal is required for each channel (named A to D for convenient reference) from the controller 12 as illustrated at 220A to 2200 in Figure 15, the signal comprising a 50 msec 0ll - 150 msec OFF waveform for each channel such that each channel is ON for a respective quarter of the 200 msec interval.

The gating signal is provided by four AI4D gates 221 which AllD 10 Hz and its antiphase 10 Hz each with 5 Hz and 5 Hz to provide channels A to D in a respective quarter or 50 msec of the 200 msec interval.

The data formatter and deformatter units 15 and 46 of Figures 1 and 5 are expanded, the RAMS 71 and 72 are each required to be of 23 x 140 bits (so that each RAII contains sufficient data bits to provide 23x1 msec bursts at 140 Kbps with one burst every secondmillisecond in a given 50 msec period - the 24th 2 msec period being used for "message continuing" indicators as in the simple channel case and the 25th period left vacant for guard time between successive channel periods) and in quadruplicate, i.e. eight 23 X 140 bit RAMs to provide 2 dedicated RAJjs per channel. The DMi in use at any moment is selected b the gating signals described with reference to Figure 15. The synchronisation generator of Figures 1 and 8 is required to have the RAM 27 extended to 16 x 140 bits (instead of 16 x 7.5 bits) so that 64 bit correlation words embedded in a series of 56 reversals can be used for prearqble, postamble message continuation and indicator frames.The method of the operation. of the 4 channel system is hen identical to tha of the single channel with each of the four channels A to D operating completely independently of the other three .e. channel A can be transmitting, searching for synchronisation preamble (for channel A) or receiving data irrespective of what channels B, C and D are doing, and similarly for the other channels.

The transceiver control system described with reference to Figures 1 to 15 operates as follows. The user unit 10 provides either an analogue voice signal to be d'gitised at 16 Kbps b the CVSD unit (not shown) or any '16 Kbps data (eg secure speech having Vinson/Lamberton encryption) to the user data buffer 11. The controller 12 clocks 16 Kbps data out of the user data buffer 11 by means of the 16 EEz clock derived from the Master and Standard clocks 18 and 19 respectively. The input to the user data buffer 11 is approximately 16 store locations (in the buffer) in front of the output to allow for relative drift between the 16 Kbps data and the controller 16 KHz cloc.

The 16 Kbps data stream passes from the user data buffer 11 to the data formatter unit 15, which transforms the stream into a 35 Kbps interleaved data stream in 1 msec bursts for output in 50 msec data frames to the output select switch 29. This switch also receives preamble, postamble and indicator frames from the synchronisation generator 26 and TOD refinement/late entry reply generator unit 28. The transmitted output from the radio 36 consists of Isec ON, sec 0zi pulses, or 500 pulses/sec.

The lmsec OFF period is for frequency hop retuning by the frequency synthesiser, which takes a finite time to do so and the lmsec ON period coincides with the 1msec bursts of data output front the switch 29. The frequency hopping controller 30 provides a pseudo random frequency codeword to the frequency synthesincr every 500msec, so that the T transmits each 1msec ON pulse on a selected frequency; the Tx then hops to another frequency for the next 1msec transmission in response to the next frequency codeword from the frequency hopping controller ro. The number of frequencies available for selection can be any nurnber from 1 to 4O96, and is determined b, thc user initialisation of the frequency hop controller 30 using the microprocessor 95.

The data buffer and control equipment in Figure 1, in conjunc tion with the radio Tx36 delivers messages consisting of an initial 100msec (50 hop) preamble frame, as many 50msec (25 frequency hops) data frames as required by the user and a final 50msec (25 hop) postamble frame. The first 23 hops in a data frame contain data from the data formatter unit 15 and the last two hops are for message continuing indication. The 24th and 25th hops (the last two hops in each data frar'..e) contain correlation words wallowing remote receivers to verify transmission continuance, avoiding the receiver being locked into synchronisation due to a missed postamble.The central data frame space may alternatively be filled by a 50msec (25 hop) indicator frame containing correlation words followed by a 50msec data frame indicating GMT + 0.2 msec supplied by the TOD refinement/late entry reply generator unit 28. The indicator and data frames are only transmitted from the TOD refinement/late reply generator unit 28 in response to a request from a remote transceiver as described above. All timings for transmission are derived from the Vaster Clock except for replies to TOD refinement and late entry requests for which timing is derived in phase with the received request signal.

Each preamble frame is 100msec in length, containing fifty x 2msec hops (ie lmsec rcturn + Irsec transmit) each of 35-bit words, at 35 Khps. Each 35-bit word is supplied by the synchromisa- tion generator's RAM store 27, and consists of eleven reversals followed by a bit correlation word selected from the sixteen words available. Each indicator and postamble frame is 50msec in lenGth, containing 25 frequency hops each of a thirty-five bit word -- eleven reversals and a 24-bit correlation word.The indicator and postamble frames are accordingly similar to but half the length of the r.reamble frame. The method of selecting correlation words also differs between these thrce kinds of frame. The preamble frame in designed for synchronisation by a remote receiver, and it is arranged to begin at 100@ msec after 0000Z 912 midnight) where N is 0, 1, 2, ..... etc. All transceivers not currently receiving or tra@smitting a message search for such preambles at each 100 msec after 0000Z.The TOD codeword, having valu@s 0000 to 1111 inclusive and employed to address correlation words in the synchronisation generator RAM store 27 and the TOD refinement/late entry reply generator RAM (Figures 8 and 9), is unchanged for preamble correlation word and message continuing indication words selection, binary complemented for post amble word selection and exclusive-ORed with afixed code for indicator word selection.

The controller 12 selects via the switch controller 162 the correct terminal (31, 32 or 33) of the output switch 29 to be connected to the modulator 35., Thus a message signal involves connection of switch output 34 to input terminal 32 for 100msec to obtain the preamble frame from the sync generator 26, to input terminal 31 (formatter unit 15) for data frames and to input terminal 32 once more for the postamble frame. Also the switch is set to input terminal 32 for every 24th and 25th hop period in a data frame for message continuing indication words. To respond to a request for TOD refinement or late entry from a remote transceiver, the connection sequence for switch terminal 34 is terminal 33 throughout.

As has been noted in the description of Figure 12, the controller 12 furnishes clock signals for transmission either coarsely synchronised to Q 2, or finely synchronised to a received signal as appropriate, at 35 KHz, 15 NHz, 500 Hz, 20 Hz and 10 its. It will now be appreicated that:: (a) the 35 IC!z signal is provided to clock out each bit of a preamble, postamble, indicator or data frame; (b) the 16 I2Iz signal is provided to clock data from the user data buffer 11; (c) the 500 Hz signal (2msec period) defines the lmsec ON, lmsec OvF modulation of the output signal from the radio transmitter 36; (d) the 1C Hz signal defines the length of the preamble frame; and (e) te 20 Hz signal defines the length of the indicator, data and post amble frames.

The 23 ,5 3 bit array of the RA@s 71 and 72 of the data formatter unit 15 each provide 805 bit locations. In practice 800 consecutive data bits in the 16 Kbps data stream are fed into one RAM and the last 5 bits in the Rkt are left unfilled or spare.

The 801st data bit in the stream then becomes the first data bit loaded into the other RUji and whilst one RAM is being filled the other is being read out to the modulator 35. The use of data interleaving by means of the formatter unit 15 provides an extra degree of anti-jamming protection to the communications particularly when Vinson-Lamberton secure speech equipment is used. However, where such protection is unnecessary, interleaving and de-interleaving may be dispensed with and the data stream transmitted in unchanged order, 35 bits at a time in sequential hops.

Turning now to R operation, the radio receiver 40 listens for x any incominG 35 Kbps data stream, to be routed via the demodulator 35 to the unit 46 for data deformatting and to the synchronisation detector 43. If no correlation with a preamble is detected in the first 71msec (36 hops) after 0000Z + 100Nmsec (N = 0, 1, 2, ....), the receiver stitches to late entry mode. If correlation is obtained within 7lmsec, the remaining 29msec or 14 frequency hops within the synchronisation preamble are used for synchronisation verification.A 35 EEz clock signal is derived in the bit syn chronisation unit 44 to be accurately or finely synchronised (within 0.5microsec) to the receive signal from the remote T and x this together with the correlation peak detected output from the synchronisation detection unit 43 is sufficient for the controller 12 to derive all clocks necessary for subsequent reception of the message data. The frequency hop controller 30 arranges the frequency hopping scheme of the radio receiver 40 to conform to that of the remote Tx, since all transceivers in a common communications network generate the same frequency hop sequence.

After fine synchronisation is obtained data frames are receive, immediately following the preamble, and are routed to the user unit 10 after deformatting in unit 46.

The time of day refinement facility also allows a participating unit to have ts laster clock reset by a remote radio transceiver which has a more accurate @@aster clock It is included to allow units having clocks with stability less than that of atomic standards (eg quartz) to operate within the system.

Radio transceivers in the communications net may transmit a time of day refinement request signal on any common communications network as selected by the user, when that channel is inactive.

This signal consists of a normal preamble frame of 100msec followed immediately b a 50msec indicator frame, indicating that TOD refinement is requested. The indicator frame is followed immediately by a 5Omsec postamble frame. The radio them immediately switches to the search for synchronisation and awaits a reply. The reply, as described above, consists of a preamble, followed by an indicator frame followed by data which represents a value T1 (defined below) and terminated by a 50msec postamble frame.

Upon receiving a synchronisation preamble, the requesting radio switches to a 'check for indicaor' mode for the next 50msec to verify that the reply is a time correction and not a normal transmission. If the indicator is received the controller 12 measures T3, which is the time offset between the clock derived from the received reply and its master clock. The controller then adjusts the master clock by (T1-T3) which aligns the master clock with the remote master clock. Transmission of a tine of day refinement request is user initiated, and a visible or audible indicator is provided to alert the user to completion of the sequence.

The operation of the rado from which the TOD refinement is requested is as follows. In normal operation the radio always carries out a check for a time of day refinement indicator in the first 50msec period following receipt of a synchronisation preamble.

This is carried out in parallel with tile loading of the data deformatter unit and causes no dela, to the processing of normal received communication traffic. Upon receipt of such an indicator the controller 12 measures T1, which is the time offset between its maser clock and the clock derived from the received TOD request and digitises this difference. As soon as possible, ie Then the channel is inactive, the radio transmits a reply on the same channel on which the request was received. The reply consists of a 100msec normal synchronisation preamble, followed immediately by a 50msec reply indicator frame.The indicator frame is followed immediately by a 50msec period of data representing the value T1, and terminated by a normal postamble. Following this transmission the radio reverts to the normal search for synchronisation mode.

Turning now to the implementation of late entry, there is one late entry mode which has full anti-jamming protection. A radio having lost coarse synchronisation has its master clock set to correct time within + 1 second (by VEflv transmissions for example).

The radio, under user instruction then commences a cycle of trans mitten for 10 secs and receiving for 2 secs on a channel selected as the late entry channel, all timing being derived from the radio's master clock. This cycle is then repeated until a validated reply is received.

The 10 sec transmission periods start at 0000Z + 12 N secs where N = 0, 1, 2, 3 ..... etc, and consists of a continuous sequence of 100msec synchronisation preambles. These preambles are constructed in exactly the same way as the normal synchronisation preambles, except the late entry channel number from the net unit 17 is used in determining frequency and correlation word address for each hop.

The radio switches to the receive mode at OOOOZ + (12N+10) seconds and carries out the normal search for synchronisation routine on the late entry channel for a period of 2 seconds, seeking for a valid reply. A valid reply consists of a normal 100msec synchro- nisation preamble followed immediately by two 50msec data frames and terminated by a 50msec post amble.

When a reply iD received the radio measures T1, where T1 is the time offset between its Master clock and the clock derived fron the received reply. The data frames in the reply contain a value for T as defined later. The master clock is then retarded by an amount equal to (T1+T2), which brings it into synchronisation with tiie master clock of the remote eplsing radio. The radio then has coarse synchronisation, and can participate in any common communication :ietwork.

A coarsely synchronised radio receiver which ;s in the late entry mode (eg after reverting to it) searches for transmitted synchronisation preambles on the user designated late entry channel, over a time uncertainty of + 1 second. This search discovers signals from remote radios which have lost coarse synchronisation.

If the normal communications net to which the radio is tuned is inactive, then the search over the + 1 second takes a maximum of 3 minutes. The search is timed from a special late entry clock, this being progressively offset from the master clock in 2msec increments each time the radio enters the late entry mode to cover the + 1 sec uncertainty. The search is carried out from early to late to avoid spoofing. The search is carried out cyclically by searching for 10 secs and resting for 2 secs. The search commences at 0000Z + 12 N secs according to the late entry clock, where N = 0, 1, 2, 3 ..... etc and the rest periods during which searching does not take place commence at 0000Z + (12N+10) secs according to the late entry clock.

Upon receipt of a synchronised preamble (ie a request for late entry) on the late entry channel, the late entry clock is not adjusted further and the radio determines the time difference T2 between its late entry clock and its master clock. The time difference is doubled to give T2, which is digitised for a reply transmission to the remote radio requesting late entry. The reply transmission commences 1 sec after the start of the next available rest period (ie at a time 0000Z + (12B+11) sec, where N = 0, 1, 2 ..... etc). All timing for the reply is referred to the late entry clock.

The reply transmission consists of a normal 100msec synchronisation preamble, followed immediately by to 50msec data frames which contain the value T2, and terminated by a 50msec postamble frame. This tr nsmission thus occurs during the period 1000 to 1250msec after the start of the rest period.

At the end of the reply ran mission the late entry clock is advanced by 2msec and the value of T2 increased by 0.002 secs. A second reply transmission, with the same format as the first reply, is then sent commencing 1400msec after the start of the rest period according to the advanced late entry clock. For the second reply the advanced late entry clock is used for all timing including correlation word and frequency selection and the adjusted value of T2 is transmitted.

After sending the second reply the radio reverts to its normal search for synchronisation mode.

It is envisaged that the probability of a radio transceiver in accordance with the above example achieving reliable synchronisation would be greater than 99.9'/3' when one synchronisation preamble frame is received under the following conditions: (1) The bit error rate in the received preamble is < 12.5% plus up to 255: of the frequencies in use being clocked by third party jamming; (2) The time uncertainty in the time of arrival of the synchronisation preamble is within + 0.2 ms of the common time datum (GMT) plus any time uncertainty in the receiver master clock, plus a propagation delay of up to 1.25ms; (3) The mean time between false synchronisation due to random noise is greater than 500 hours; and (4) The mean time between false synchronisation due to a jammer radiating synchronisation correlation words on 25% of the frequencies in use is greater than 1 hour.

The conditions (1) and (2) above relating to synchronisation would also apply to the detection of a postamble.

In the late entry modes, the probability that a radio will detect a transmitted late entry request should be greater than 95% during one search over the + 1 second time uncertainty. The probability of success should be met under the signal conditions specified in (1) above.

"en receiving a transmission which terminates and the postamble frame is not detected, the probability of the radio recognising the absence of message continuing indication words in the 24th and 25th hop period in each data frame should be greater than 99, the end of a period of 2 seconds after the transmission has ceased, ind the radio would revert to the search for synchronisation mode. The probability of the radio indicating that the correlation words are absent, when in fact they are being transmitted, should be less than 0.00006%. In both cases it is assumed that the signal conditions are as specified under (1) above.

Claims (17)

Claims

1. A digital radio transceiver to form part of a frequency hopping communications system wherein there are pseudo-random changes of transmission frequency, the transceiver comprising: a) a radio transmitter; a means for buffering message data for transmission; a means for selecting an output frequency hopping sequence common to the communications system; a means for controlling the transmitter such that the buffered data are transmitted in frames with the frames separated by quiescent periods during which the transmission frequency changes occur; a master clock adjustable to adequate synchronisation with a given datum; and a means for synchronising transmissions with the master clock; and b) a radio receiver; means for operating the transceiver in a frequency hopping sequence common to the communications system when used in the receiver mode; synchronising means for synchronising reception with a remote transmitter's master clock; and a message output means to reconstitute the transmitted message from the received signal.

2. A digital radio transceiver according to claim 1 wherein a 50 duty cycle is used, data being transmitted at a single frequency during one half of the cycle and a frequency change occurring during the second half of the cycle.

3. A digital radio transceiver according to claim 1 or 2 wherein each data frame is arranged for separate sequential channel operation.

4. A digital radio transceiver according to any one preceding claim wherein the buffering means receives a continuous digital data stream and includes means for formatting this data in an interleaving array and provides at an output thereof bursts of interleaved data coinciding with the transmission data frame times.

5. A digital radio transceiver according to any one preceding claim wherein the transmission synchronising means includes a means for selecting correlation words using a p eudo- random process related to the time of day given by the master clock and a means for formatting the correlation words such that one complete word is transmitted during each data frame.

6. A digital radio transceiver according to claim 5 wherein there is included a means to select when synchronisation transmissions are to be made to provide pre-amble, message continuing indications and post-amble transmissions.

7. A digital radio transceiver according to claim 6 wherein there is a means for continually monitoring the received data stream to detect valid correlation words and to determine from the instances of valid correlation word reception whether a valid synchronisation transmission is being received.

8. A digital radio transceiver according to any one preceding claim wherein there is included a means for locking the phase of a locally-provided clock with the phase of the received data stream.

9. A digital radio transceiver according to clain 8 wherein the phase locking means comprises a bit synchronisation unit incorporating a digital phase locked loop.

10. A digital radio transceiver according to any one preceding claim including means to transmit a coded signal requesting timing refinement and including the transmitter time-of-day and means to adjust the master clock on receiving a response.

11. A digital radio transceiver according to claim 10 wherein the receiver of the transceiver includes a means for detecting a coded signal requesting timing refinement and means to actuate transmission of a signal indicating the time difference between the master clock and the master clock of a remote requesting transceiver.

12. A digital radio transceiver according to claim 11 wherein there are provided two modes for refinement of master clock timing, one for relatively fine adjustments up to t 0.2 msec and one for relatively coarse adjustments up to - 1 sec.

13. A digital radio transceiver according to claim 12 wherein there is included a clock which incre:nentally adjusts the tiring of successive synchronisation request signals in steps of 0.2 msec throughout the 7 sec period of uncertainty until a synchronised response is received from a remote transceiver indicating the time difference (to within - 0.2 msec) betwcen the clocks of the two transceivers.

14. A digital radio transceiver according to claim 5 wherein the stream of correlation words produced by the pseuso random generator for synchronisation purposes is also connected to a frequency synthesiser so as to select from the range of frequencies available a different output transmission frequency corresponding to each code word.

15. A digital radio transceiver according to claim 14 wherein the set of output correlation words and hence the set of frequencies used for the frequency hopping communication can be programmed so as to be able to define separate communication networks within the system.

16. A digital radio transceiver according to claim 15 wherein a separate network or pattern of frequency hops is assigned for requesting accurate time of day and for searching for requests for t;e of day refinement.

17. A digital radio transceiver substantially as described with reference to figures 1 to 15 of the attached Drawings.

17. A digital radio transceiver substantially as described with reference to figures 1 to 15 of the attached Drawings.

Amendments to the claims have been filed as follows 1. A digital radio transceiver to form part of a frequency hopping communications system wherein there are pseudo-random changes of transmission frequency, the transceiver comprising: a) a radio transmitter; a means for buffering message data for transmission; a code word generator for producing a stream of code words related to the time-of-day, the code words being used for selection of message synchronisation data and for selection of the frequencies for data transmission; a means for controlling the transmitter such that the buffered data and message synchronisation data are transmitted in frames with the frames separated by quiescent periods during which the transmission frequency changes occur; a master clock adjustable to adequate synchronisation with a given datum; a means for synchronising transmissions with the master clock; and b) a radio receiver; means for operating the transceiver in a frequency hopping sequence common to the communications system when used in the receiver mode; a means responsive to received message synchronisation data; synchronising means for synchronising reception with a remote transmitter's master clock; and a message output means to reconstitute the transmitted message from the received signal.

2. A digital radio transceiver according to claim 1 wherein a 50% duty cycle is used, data being transmitted at a single frequency during one half of the cycle and a frequency change occurring during the second half of the cycle.

3. A digital radio transceiver according to claim 1 or 2 wherein each data frame is arranged for separate sequential channel operation.

4. A digital radio transceiver according to any one preceding claim wherein the buffering means receives a continuous digital data stream and includes means for formatting this data in an interleaving array and provides at an output thereof bursts of interleaved data coinciding with the transmission data frame times.

5. A digital radio transceiver according to any one preceding claim wherein the transmission synchronising means includes a means for selecting correlation words using a pseudorandom process related to the time of day given by the master clock and a means for formatting the correlation words such that one complete word is transmitted during each data frame.

6. A digital radio transceiver according to claim 5 wherein there is included a means to select when synchronisation transmissions are to be made to provide pre-amble, message continuing indications and post-amble transmissions.

7. A digital radio transceiver according to claim 6 wherein there is a means for continually monitoring the received data stream to detect valid correlation words and to determine from the instances of valid correlation word reception whether a valid synchronisation transmission is being received.

8. A digital radio transceiver according to any one preceding claim wherein there i6 included a means for locking the phase of a locally-provided clock with the phase of the received data stream.

9. A digital radio transceiver according to claim 8 wherein the phase locking means comprises a bit synchronisation unit incorporating a digital phase locked loop.

10. A digital radio transceiver according to any one preceding claim including means to transmit a coded signal requesting timing refinement and including the transmitter time-of-day and means to adjust the master clock on receiving a response.

11. A digital radio transceiver according to claim 10 wherein the receiver of the transceiver includes a means for detecting a coded signal requesting timing refinement and means to actuate transmission of a signal indicating the time difference between the master clock and the master clock of a remote requesting transceiver.

12. A digital radio transceiver according to claim 11 wherein there are provided two modes for refinement of master clock timing, one for relatively fine adjustments up to i 0.2 msec and one for relatively coarse adjustments up to - 1 sec.

13. A digital radio transceiver according to claim 12 wherein there is included a clock which incrementally adjusts the timing of successive synchronisation request signals in steps of 0.2 msec throughout the 1 sec period of uncertainty until a synchronised response is received from a remote transceiver indicating the time difference (to within - 0.2 msec) between the clocks of the two transceivers.

14. A digital radio transceiver according to claim 5 wherein the stream of correlation words produced. by the pseud random generator for synchronisation purposes is also connected to a frequency synthesiser so as to select from the range of frequencies available a different output transmission frequency corresponding to each code word.

15. A digital radio transceiver according to claim 14 wherein the set of output correlation words and hence the set of frequencies used for the frequency hopping communication can be programmed so as to be able to define separate communication networks within the system.

16. A digital radio transceiver according to claim 15 i,herein a separate network or pattern of frequency hops is assigned for requesting accurate time of day and for searching for requests for time of day refinement.