GB2288521B - Reconfigurable process stage - Google Patents

Reconfigurable process stage

Info

Publication number
GB2288521B
GB2288521B GB9504047A GB9504047A GB2288521B GB 2288521 B GB2288521 B GB 2288521B GB 9504047 A GB9504047 A GB 9504047A GB 9504047 A GB9504047 A GB 9504047A GB 2288521 B GB2288521 B GB 2288521B
Authority
GB
United Kingdom
Prior art keywords
process stage
reconfigurable process
reconfigurable
stage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
GB9504047A
Other versions
GB2288521A (en
GB9504047D0 (en
GB2288521A8 (en
Inventor
Adrian Philip Wise
William Philip Robbins
Martin William Sotheran
Anthony Mark Jones
Anthony Peter John Claydon
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Discovision Associates
Original Assignee
Discovision Associates
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from GB9405914A external-priority patent/GB9405914D0/en
Priority to GB9504047A priority Critical patent/GB2288521B/en
Application filed by Discovision Associates filed Critical Discovision Associates
Priority to US08/399,898 priority patent/US5768561A/en
Priority to CA002145549A priority patent/CA2145549C/en
Priority to CA002145219A priority patent/CA2145219C/en
Priority to KR1019950006172A priority patent/KR100291532B1/en
Priority to CA002145426A priority patent/CA2145426A1/en
Priority to JP09001095A priority patent/JP3302527B2/en
Priority to CN95103246A priority patent/CN1137212A/en
Publication of GB9504047D0 publication Critical patent/GB9504047D0/en
Priority to JP7266747A priority patent/JPH0918871A/en
Priority to JP7266757A priority patent/JPH08116260A/en
Publication of GB2288521A publication Critical patent/GB2288521A/en
Publication of GB2288521A8 publication Critical patent/GB2288521A8/en
Priority to CN98103849A priority patent/CN1235483A/en
Priority to JP10318260A priority patent/JPH11266460A/en
Publication of GB2288521B publication Critical patent/GB2288521B/en
Application granted granted Critical
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/04—Addressing variable-length words or parts of words
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0607—Interleaved addressing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1673—Details of memory controller using buffers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3867—Concurrent instruction execution, e.g. pipeline, look ahead using instruction pipelines
    • G06F9/3871—Asynchronous instruction pipeline, e.g. using handshake signals between stages
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3867—Concurrent instruction execution, e.g. pipeline, look ahead using instruction pipelines
    • G06F9/3873—Variable length pipelines, e.g. elastic pipeline
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units
    • G06F9/3893—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator
    • G06F9/3895—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator for complex operations, e.g. multidimensional or interleaved address generators, macros
    • G06F9/3897—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator for complex operations, e.g. multidimensional or interleaved address generators, macros with adaptable data path
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
    • H04N19/423—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation characterised by memory arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/60—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding
    • H04N19/61—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding in combination with predictive coding
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
    • H04N19/102—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the element, parameter or selection affected or controlled by the adaptive coding
    • H04N19/13—Adaptive entropy coding, e.g. adaptive variable length coding [AVLC] or context adaptive binary arithmetic coding [CABAC]
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/90—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using coding techniques not provided for in groups H04N19/10-H04N19/85, e.g. fractals
    • H04N19/91—Entropy coding, e.g. variable length coding [VLC] or arithmetic coding
GB9504047A 1992-06-30 1995-02-28 Reconfigurable process stage Expired - Lifetime GB2288521B (en)

Priority Applications (12)

Application Number Priority Date Filing Date Title
GB9504047A GB2288521B (en) 1994-03-24 1995-02-28 Reconfigurable process stage
US08/399,898 US5768561A (en) 1992-06-30 1995-03-07 Tokens-based adaptive video processing arrangement
CA002145549A CA2145549C (en) 1994-03-24 1995-03-22 Multi-standard configuration
CA002145219A CA2145219C (en) 1994-03-24 1995-03-22 Pipeline system including inverse modeller stage, inverse cosine transform stage, and processing stage
KR1019950006172A KR100291532B1 (en) 1994-03-24 1995-03-23 An information processing system comprising a reconfigurable processing stage
CA002145426A CA2145426A1 (en) 1994-03-24 1995-03-23 Pipeline processing machine, related system and multi-standard decoder including reconfigurable processing stages and method relating thereto
JP09001095A JP3302527B2 (en) 1994-03-24 1995-03-24 Reconfigurable processing system
CN95103246A CN1137212A (en) 1994-03-24 1995-03-24 Treating stage capable of reconfigurating
JP7266747A JPH0918871A (en) 1994-03-24 1995-09-13 Reconfigurable processing system
JP7266757A JPH08116260A (en) 1994-03-24 1995-09-13 Re-configrable processing system
CN98103849A CN1235483A (en) 1994-03-24 1998-02-16 Prediction filter
JP10318260A JPH11266460A (en) 1994-03-24 1998-10-06 Video information processing circuit

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB9405914A GB9405914D0 (en) 1994-03-24 1994-03-24 Video decompression
GB9504047A GB2288521B (en) 1994-03-24 1995-02-28 Reconfigurable process stage

Publications (4)

Publication Number Publication Date
GB9504047D0 GB9504047D0 (en) 1995-04-19
GB2288521A GB2288521A (en) 1995-10-18
GB2288521A8 GB2288521A8 (en) 1996-04-15
GB2288521B true GB2288521B (en) 1998-10-14

Family

ID=26304581

Family Applications (1)

Application Number Title Priority Date Filing Date
GB9504047A Expired - Lifetime GB2288521B (en) 1992-06-30 1995-02-28 Reconfigurable process stage

Country Status (5)

Country Link
JP (4) JP3302527B2 (en)
KR (1) KR100291532B1 (en)
CN (2) CN1137212A (en)
CA (3) CA2145549C (en)
GB (1) GB2288521B (en)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2794601B1 (en) * 1999-06-02 2001-07-27 Dassault Automatismes COMMUNICATION DEVICE FOR COLLECTIVE INFORMATION RECEPTION, IN PARTICULAR OF DIGITAL TELEVISION IMAGES AND / OR MULTIMEDIA DATA
EP1148727A1 (en) * 2000-04-05 2001-10-24 THOMSON multimedia Method and device for decoding a digital video stream in a digital video system using dummy header insertion
KR100354768B1 (en) 2000-07-06 2002-10-05 삼성전자 주식회사 Video codec system, method for processing data between the system and host system and encoding/decoding control method in the system
US8284844B2 (en) 2002-04-01 2012-10-09 Broadcom Corporation Video decoding system supporting multiple standards
KR100722428B1 (en) * 2005-02-07 2007-05-29 재단법인서울대학교산학협력재단 Resource Sharing and Pipelining in Coarse-Grained Reconfigurable Architecture
US7873105B2 (en) 2005-04-01 2011-01-18 Broadcom Corporation Hardware implementation of optimized single inverse quantization engine for a plurality of standards
KR100711088B1 (en) * 2005-04-13 2007-04-24 광주과학기술원 Integer Transform Device for Moving Picture Encoder
KR100718135B1 (en) 2005-08-24 2007-05-14 삼성전자주식회사 apparatus and method for video prediction for multi-formet codec and the video encoding/decoding apparatus and method thereof.
JP5698428B2 (en) * 2006-11-08 2015-04-08 三星電子株式会社Ｓａｍｓｕｎｇ Ｅｌｅｃｔｒｏｎｉｃｓ Ｃｏ．，Ｌｔｄ． Motion compensation method, recording medium, and motion compensation device
KR101354659B1 (en) 2006-11-08 2014-01-28 삼성전자주식회사 Method and apparatus for motion compensation supporting multicodec
KR101553648B1 (en) 2009-02-13 2015-09-17 삼성전자 주식회사 A processor with reconfigurable architecture
CN102783065B (en) * 2010-04-02 2014-11-19 富士通株式会社 Apparatus and method for orthogonal cover code (OCC) generation, and apparatus and method for OCC mapping
US8413166B2 (en) * 2011-08-18 2013-04-02 International Business Machines Corporation Multithreaded physics engine with impulse propagation
US10219006B2 (en) * 2013-01-04 2019-02-26 Sony Corporation JCTVC-L0226: VPS and VPS_extension updates
US9395990B2 (en) * 2013-06-28 2016-07-19 Intel Corporation Mode dependent partial width load to wider register processors, methods, and systems
JP6223323B2 (en) * 2014-12-12 2017-11-01 Ｎｔｔエレクトロニクス株式会社 Decimal pixel generation method
KR102602476B1 (en) * 2015-07-03 2023-11-14 인텔 코포레이션 Apparatus and method for data compression in wearable devices
CN107844322B (en) * 2017-07-20 2020-08-04 上海寒武纪信息科技有限公司 Apparatus and method for performing artificial neural network forward operations
CN109901044B (en) * 2017-12-07 2021-11-12 英业达科技有限公司 Central processing unit differential test system of multiple circuit boards and method thereof
CN113591795B (en) * 2021-08-19 2023-08-08 西南石油大学 Lightweight face detection method and system based on mixed attention characteristic pyramid structure

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0196911A2 (en) * 1985-03-28 1986-10-08 Honeywell Inc. Local area networks
EP0576749A1 (en) * 1992-06-30 1994-01-05 Discovision Associates Data pipeline system and data encoding method
GB2269070A (en) * 1992-07-07 1994-01-26 Ricoh Kk Huffman decoder architecture for high speed operation and reduced memory.
US5298896A (en) * 1993-03-15 1994-03-29 Bell Communications Research, Inc. Method and system for high order conditional entropy coding
WO1994025935A1 (en) * 1993-04-27 1994-11-10 Array Microsystems, Inc. Image compression coprocessor with data flow control and multiple processing units

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0196911A2 (en) * 1985-03-28 1986-10-08 Honeywell Inc. Local area networks
EP0576749A1 (en) * 1992-06-30 1994-01-05 Discovision Associates Data pipeline system and data encoding method
GB2269070A (en) * 1992-07-07 1994-01-26 Ricoh Kk Huffman decoder architecture for high speed operation and reduced memory.
US5298896A (en) * 1993-03-15 1994-03-29 Bell Communications Research, Inc. Method and system for high order conditional entropy coding
WO1994025935A1 (en) * 1993-04-27 1994-11-10 Array Microsystems, Inc. Image compression coprocessor with data flow control and multiple processing units

Also Published As

Publication number Publication date
CA2145426A1 (en) 1995-09-25
JPH0870453A (en) 1996-03-12
JPH08116260A (en) 1996-05-07
KR100291532B1 (en) 2001-06-01
GB2288521A (en) 1995-10-18
GB9504047D0 (en) 1995-04-19
CA2145549C (en) 2001-02-20
JPH0918871A (en) 1997-01-17
CN1235483A (en) 1999-11-17
CA2145549A1 (en) 1995-09-25
JP3302527B2 (en) 2002-07-15
JPH11266460A (en) 1999-09-28
GB2288521A8 (en) 1996-04-15
CA2145219C (en) 2001-11-27
CN1137212A (en) 1996-12-04
KR950033896A (en) 1995-12-26
CA2145219A1 (en) 1995-09-25

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Legal Events

Date Code Title Description
732E Amendments to the register in respect of changes of name or changes affecting rights (sect. 32/1977)

Free format text: REGISTERED BETWEEN 20100408 AND 20100414

PE20 Patent expired after termination of 20 years

Expiry date: 20150227