CN1235483A - Prediction filter - Google Patents
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- CN1235483A CN1235483A CN98103849A CN98103849A CN1235483A CN 1235483 A CN1235483 A CN 1235483A CN 98103849 A CN98103849 A CN 98103849A CN 98103849 A CN98103849 A CN 98103849A CN 1235483 A CN1235483 A CN 1235483A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/04—Addressing variable-length words or parts of words
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
- G06F12/0607—Interleaved addressing
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
- G06F13/1673—Details of memory controller using buffers
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3867—Concurrent instruction execution, e.g. pipeline, look ahead using instruction pipelines
- G06F9/3871—Asynchronous instruction pipeline, e.g. using handshake signals between stages
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3867—Concurrent instruction execution, e.g. pipeline, look ahead using instruction pipelines
- G06F9/3873—Variable length pipelines, e.g. elastic pipeline
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3885—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units
- G06F9/3893—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator
- G06F9/3895—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator for complex operations, e.g. multidimensional or interleaved address generators, macros
- G06F9/3897—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator for complex operations, e.g. multidimensional or interleaved address generators, macros with adaptable data path
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
- H04N19/423—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation characterised by memory arrangements
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/60—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding
- H04N19/61—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding in combination with predictive coding
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
- H04N19/102—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the element, parameter or selection affected or controlled by the adaptive coding
- H04N19/13—Adaptive entropy coding, e.g. adaptive variable length coding [AVLC] or context adaptive binary arithmetic coding [CABAC]
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/90—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using coding techniques not provided for in groups H04N19/10-H04N19/85, e.g. fractals
- H04N19/91—Entropy coding, e.g. variable length coding [VLC] or arithmetic coding
Abstract
A video information processing device which uses a first and a second prediction filter circuits with the same essential and uses control signals to process video information coded with multi-standard. A filter circuit for video decompression used in the device includes a prediction filter format device, a first one dimension prediction filter, a dimension buffer and a second one dimension prediction filter. A prediction filter which can be used in this filter circuit includes six registers, two time multiplication devices and two sum circuits.
Description
The application is that name is called an application for a patent for invention (applying date: March 24 nineteen ninety-five, application number: dividing an application 95103246.1) of " treating stage capable of reconfigurating ".
The present invention relates to a kind of decompression circuit.The work of this decompression circuit is that the input signal to a plurality of different codings decompresses and/or decodes.Hereinafter select the decoding to multiple encoded image standard of description.Specifically, it relates to the decoding for any one standard in the well-known compression standard such as Joint Photographic Experts Group (JPEG), Motion Picture Experts Group (MPEG) and H.261.
The U.S. Patent No. 4,866,510 of authorizing people such as Goodfellow discloses a kind of differential pulse code device that reduces the composite colour video signal bit rate.The realization of this reduction is to predict present vision signal sample value and form the signal of representing predicated error from the past sample value of reconstruct.By signal and formation and this error signal that produces this error signal of prediction and the corresponding signal of difference of predicting the signal of this error signal, bit rate is further reduced.When output, sue for peace the reconstructed video signal sample value with the signal of predicting previous vision signal sample by error signal to reconstruct.The vision signal sample value generally includes the delegation or the multirow of composite signal.
The U.S. Patent No. 5,301,040 of authorizing people such as Hoshi discloses a kind ofly comes the data apparatus for encoding by view data being transformed to frequency domain.This device can comprise two kinds of code devices that can walk abreast and encode.
The U.S. Patent No. 5,301,242 of authorizing people such as Gonzales discloses a kind of apparatus and method to encoding video pictures.These apparatus and method only are transformed into the group of digital video signal piece according to mpeg standard the group of compressible digital video signal piece.
The U.S. Patent No. 4,142,205 of authorizing Iinuma discloses a kind of interframe encode device that is used for video burst and sync signal.This interframe encode device obtains the frame difference signal by a frame signal is deducted from the next frame signal.Corresponding interframe decoder then carries out inverse operation.
The U.S. Patent No. 4,924,298 of authorizing Kitamura discloses a kind of method and apparatus that the digital signal that obtains from shifted color burst signal into burst interval of analog color video signal is carried out predictive coding.In the process of predictive coding, usually predict pictorial element in first scan line according to the image primitive in second scan line adjacent with first scan line.
The U.S. Patent No. 4,924,308 of authorizing Feuchtwanger discloses a kind of bandwidth reducing system that is used for TV signal.This system uses three spatial filter circuit that can produce resolution characteristic separately to signal.According to the degree of the motion that occurs in the space segment separately at television image, different spatial filter circuit produces the resolution of different brackets.
The U.S. Patent No. 5,086,489 of authorizing Shimura discloses a kind of method that is used for compressing image signal.According to this patent, the original image signal component of representative image is taken a sample, make along the phase place of each sample value of delegation and between each sample value of adjacent lines, phase shifts is arranged.These representational picture signal components are divided into the principal component with the sampling of suitable sampling interval; With the interpolation component that stands the interpolation prediction encoding process according to described each principal component.The decompression circuit general introduction
Decompression circuit can comprise spatial decoder, temporal decoder and video formatter.A kind of circuit like this has more detailed description in U.S. Patent application No.9405914.4, list this patent application here for your guidance.The temporal decoder general introduction
The temporal decoder utilization one or more picture frames-or claim reference frame-in information predict information in another picture frame.Because different coding standard allows dissimilar predictions, dissimilar motion compensation and dissimilar frame rearrangements, so the operation of termporal filter is different because of the coding standard in the operation.Described each reference frame storing is in two external frame buffers.The Joint Photographic Experts Group general introduction
Joint Photographic Experts Group does not adopt inter prediction.Therefore, except being decoded by spatial decoder, temporal decoder will allow jpeg data pass through to video formatter and do not carry out the decoding of any essence under this mode.The mpeg standard general introduction
Mpeg standard utilizes three types frame: (I), prediction (P) and two-way interpolation (B) in the frame.Frame is made up of pixel.The I frame need not to use the time decoder decode, but the I frame is used for P and B frame decoding.Before needs I frame, it can be stored in the frame buffer.
The decoding request of P frame is formed prediction from the I or the P frame of previous decoding.In order in the decoding of P and B frame, to use later, can be stored in decoded P frame in one of frame buffer.
The B frame is taken from the future for one with according to being stored in two reference frames in the frame buffer, take from the past for one, and carry out be predicted as the basis.But the B frame is not stored in any one of frame buffer.
Mpeg standard also adopts motion compensation, and motion compensation is to use motion vector to improve efficient to pixel prediction.Motion vector is provided at over and/or the skew in the reference frame in the future.
Mpeg standard adopts the motion vector on x and the y bidimensional.This standard allows motion vector is stipulated that each dimension goes up the precision of half-pixel.
In a kind of configuration under mpeg standard, identical during with these frame decoders input time from the order of each frame of temporal decoder output.This configuration is called the MPEG operation of not resequencing.But, because mpeg standard allow according to future reference frame predict, so can rearrange the order of frame.In this configuration, each B frame decoded with the aforesaid order identical output with when input.Yet I and P frame are not exported after decoding.On the contrary, they write frame buffer after decoding.They are only just exported when being used to decode at next I or the arrival of P frame.
Obtaining can be with reference to the mpeg standard draft of being advised about the full details of prediction and related arithmetical operation.Temporal decoder satisfies every requirement of listing in this draft.H.261 standard general introduction
The H261 standard is only predicted according to the frame of decoding just.In operating aspect, behind every frame decoding, this frame is write one of two frame buffers for using in the next frame decoding.After the image of decoding write frame buffer, they were exported by temporal decoder; Therefore, H261 does not support the rearrangement of frame.
Under standard H.261, motion vector is only stipulated the precision of whole pixel.In addition, encoder can regulation be added to low pass filter on any gained prediction result.
Obtaining can be with reference to standard H.261 about the full details of prediction and related arithmetical operation.Temporal decoder satisfies every requirement of listing in this standard.
Temporal decoder comprises the predictive filter system.This predictive filter system receives the one or more block of pixels that will use and receives the additional information of representing with sign or signal form in prediction.According to this additional information, the predictive filter system determines the configuration of operational standard, this standard, accuracy class and other information of motion vector.The predictive filter system uses correct interpolation function according to this information then.
Because can predict to some piece in the frame, and can be to other piece direct coding, so the output of each predictive filter may need to be added on the remainder of a frame.The prediction adder is finished this function.
If described frame is the B frame, then temporal decoder outputs to video formatter with it.If described frame is I or P frame, then temporal decoder is write one of frame buffer with this frame, and exports this frame when invalid when frame reorders, perhaps when frame reorder output previous I or P frame when effective.
According to the present invention, a plurality of predictive filter circuit can be handled video information, and a control signal then makes the possibility that is treated as with the video information of multiple standards coding.Wherein disclose a filter circuit that can be used for handling video information, it comprises predictive filter formatter, dimension buffer and two one-dimensional prediction filters.Each such one-dimensional prediction filter can comprise six registers, two multipliers (multiplexer) and two summing circuits, and these parts link together and make and can handle video information with the multiple standards coding.
Adopt predictive filter of the present invention to make and can handle the video information of encoding expeditiously with multiple standards, thus just easy to the processing of a large amount of different image standards.
With reference now to description of drawings embodiment, with further specify the present invention.
Fig. 1 is the block diagram that contains the temporal decoder of predictive filter system.
Fig. 2 is the opposing party's block diagram that contains the temporal decoder of predictive filter system.
Fig. 3 is a block diagram that contains the temporal decoder of predictive filter system.
Fig. 4 is the block diagram according to the predictive filter system of one embodiment of the invention.
Fig. 5 is the block diagram according to the predictive filter of one embodiment of the invention.
Fig. 6 is the more detailed block diagram of predictive filter.
Fig. 7 is a pixel data blocks.
At temporal decoder 10 shown in Fig. 1,2 and 3.First output of DRAM (dynamic random access memory) interface 12 is sent to predictive filter system 400 by line 404,405.The output of predictive filter system 400 is arrived prediction adder 13 by line 410 as second input transfer.First output of prediction adder 13 is sent to outlet selector 15 by line 14.The second output warp 16 of prediction adder 13 transmits.
Each arrow among Fig. 1 is represented one two line interface.The token streams of input is by input interface, and this interface is internal clocking that obtains from phased lock loop (Ph0/Ph1) and the data sync of coming from external system clock.Token streams is divided into two-way by a top layer fork, and one the tunnel enters address generator, another road to one 256 word FIFO.From the data of the I or the P frame of front, when taking out from DRAM, FIFO plays cushioning effect to data.Meanwhile, the data of preceding several I or P frame are taken out from DRAM, they are added in prediction adder (Prediction Adder) before the input error number (incoming error data) that comes from spatial decoder (Spatial Decoder) goes up, and handle (P and B frame) earlier in calculating filter.During mpeg decode, the frame of I and P frame reorders, and data are also necessary takes out, so that the order of output frame is correct.The data that reorder are inserted in the stream in read pointer (Read Rudder) piece.
Address generator is forward direction and back forecast, reorder, read and write is returned etc. produces independently address.The data that write back are told from stream in write pointer piece (outlet selector).At last, data are synchronous again with external clock in the output interface piece.
All main pieces are connected to internal microprocessor interface (UPI) bus in the temporal decoder.This is to obtain from external microprocessor interface (MPI) bus the Microprocessor Interface parts.These parts have the address decoder of each parts in to the chip relevant with it.Affair logic is also relevant with Microprocessor Interface.
With reference now to Fig. 2,, the unit irrelevant with standard comprises DRAM interface 12, fork, fifo register, adder 13 and outlet selector 15.The unit relevant with standard is address generator, it H.261 be different among the MPEG, also have predictive filter 400, it is reconfigurable, has the ability H.261 all working with two kinds of standards of MPEG.Jpeg data can not flow through entire machine fully with changing.
In the temporal decoder of the present invention, the fork receives the input of the output of IDCT (reverse discrete cosine transform) (not shown) as it in Fig. 2.As the first control token of exporting at fork, for example mobile vector or the like is delivered to address generator.For the purpose of counting, data token is also delivered to address generator.As second output at fork, data are delivered to FIFO.The output of FIFO is delivered to the prediction adder as first input then.Deliver to DRAM interface 12 from the output of address generator as first input.DRAM with 12 pairs of outsides of DRAM interface sends signal or received signal.First output of DRAM interface 12 is delivered to by line 404,405 and is surveyed filter 400.The output of predictive filter 400 is delivered to adder by line 410 as second input.First output of adder is delivered to outlet selector 15 by line 14.Second output of adder is delivered to DRAM interface 12 by line 16 as second input.Second output of DRAM interface is delivered to outlet selector 15 as second input.Video formatter (not shown in Fig. 2) is delivered in the output of outlet selector 15.
Referring to Fig. 3, dispenser (split) receives input.Address generator is delivered in first output of dispenser.DRAM interface 12 is delivered in the address that address generator produces.12 couples of outside DRAM send signal or received signal with the DRAM interface.First output of DRAM interface 12 is delivered to predictive filter 400 by line 404,405.The output of predictive filter 400 is delivered to adder 13 by line 410 as first input.Second output of dispenser is delivered to first in first out (FIFO) as input.Deliver to adder 13 from the output of FIFO as second input.The output of adder 13 is delivered to outlet selector (write signal generator) 15 by line 15.DRAM interface 12 is delivered in first output of outlet selector 15.Second output of outlet selector 15 is delivered to the read signal generator as first input.Second output of DRAM interface 12 is delivered to the read signal generator as second input.Video formatter (not drawing) is delivered in the output of read signal generator in Fig. 3.
In general, according to the present invention, predictive filter is in MPEG and H261 mode and do not use under the JPEG mode.Please remember that in the JPEG mode, temporal decoder just is sent to video formatter with data, it does not do the decoding of any essence, except the sort of decoding that spatial decoder is done.In the MPEG mode, forward direction and back forecast filter are equal to, and they carry out filtering to MPEG forward direction and back forecast piece respectively.Yet,, only use the forward prediction filter, because H.261 without back forecast in mode H.261.
Two predictive filters of the present invention come down to identical.Referring to Fig. 5, be the block diagram of predictive filter structure there.Each predictive filter is made up of the level Four of series connection.Data enter formatter 501, are placed among the form that carries out filtering easily.In next stage 502, the X-coordinate is carried out 1-D calculate.After dimension buffer (dimension buffer) level 503 is finished necessary transposition, the prediction of carrying out the Y-coordinate in level 504.How to predict and to illustrate in greater detail afterwards.Need which filtering operation, this is defined by compression standard.If H.261, filtering of being carried out and low pass filter similar.
Referring to Fig. 3, many standard operations requirement forecast filter can be reconfigured again so that or carry out MPEG or H.261 filtering, or do not carry out filtering in the JPEG mode.As other many reconfigurable aspects of three chip systems, predictive filter also is that the method with token is reconfigured.Token also is used for informing this particular job of address generator mode.Use this way, address generator just can provide the address of desired data to predictive filter, and these addresses difference between MPEG and JPEG is very big.
According to the present invention, the general construction of predictive filter is shown in Fig. 4.Forward direction and backward filter are together complete, and they are to MPEG forward direction and the filtering of back forecast piece.Have only forward-direction filter to be used in H.261 mode (the h261_on input of backward filter should be low forever, because H.261 stream does not comprise back forecast).Whole predictive filter piece is made up of the streamline of some two line interface levels.
With reference to figure 4, this illustrates the general structure of predictive filter system 400.This predictive filter system 400 comprises a plurality of predictive filters 401,402 and a predictive filter adder 403.Forward prediction filter 401 is identical with back forecast filter 402, they under the MPEG mode to forward direction and the filtering of back forecast piece.Under mode H.261, only use forward prediction filter 401, because H.261 standard can not be made back forecast.
Each predictive filter 401,402 is irrelevantly worked mutually, just handles these data in case valid data appear at input 404,405.The output of forward prediction filter 401 is sent to predictive filter adder 403 by line 406.The output of back forecast filter 402 is sent to predictive filter adder 403 by line 407.Other input is sent to predictive filter adder 403 by line 408,409.The output of predictive filter adder 403 is delivered on the line 410.Each bar of line 404 to 410 in the predictive filter system 400 can be two line interfaces.
The operation requirement forecast filter system 400 of multiple standards can be configured to carry out MPEG or H261 filtering.Can deliver to predictive filter system 400 to sign or other appropriate signals to carry out reconfiguring of system.Below will more go through the transmission that these are identified to item forecast filter 401,402 and arrive predictive filter adder 403.
Sign or signal that predictive filter adder 403 is configured have four.Wherein, fwd_ima_twin and fwd_p_num are by forward prediction filter 401, and bwd_ima_twin and bwd_p_num are by back forecast filter 402.
As later institute in greater detail, these signs of predictive filter adder 403 usefulness or signal make two state variable fwd_on and bwd_on effective or invalid.State variable fwd_on indicates whether to use forward prediction to predict pixel value in the current block.Equally, state variable bwd_on indicates whether to use back forecast to predict pixel value in the current block.
In the H261 operation, fully without back forecast, so bwd_on is always invalid.Therefore, predictive filter adder 403 is always ignored the output of back forecast filter 402.If state variable fwd_on is effective, the output of forward prediction filter 401 is just by predictive filter adder 403.If after this state variable fwd_on is invalid, current block is not predicted that then predictive filter adder 403 is not passed through the information from any filter of predictive filter 401,402.
In the MPEG operation, state variable fwd_on and bwd_on have four kinds of possibility situations.If two state variables are all invalid, then predictive filter adder 403 is not passed through the information from any one filter of predictive filter 401,402.
If effectively still state variable bwd_on is invalid for state variable fwd_on, then predictive filter adder 403 is by the output from forward prediction filter 401.
If effectively still state variable fwd_on is invalid for state variable bwd_on, then predictive filter adder 403 is by the output from back forecast filter 402.
If two state variables are all effective, then predictive filter adder 403 is sent the mean value that rounds towards the positive infinity direction of predictive filter 401,402 output.
As shown in Figure 5, each predictive filter 401,402 is made up of identical in fact structure.The input data enter the predictive filter formatter that these data is become the form of being convenient to filtering.Data are delivered to the first one-dimensional prediction filter 502 of carrying out one-dimensional prediction then.This prediction can be carried out in x direction or y direction.Data are delivered to the dimension buffer 503 that the data of further filtering are made in preparation then.
Then data are delivered to the second one-dimensional prediction filter 504 of carrying out one-dimensional prediction on the direction that is not subjected to 501 predictions of the first one-dimensional prediction filter.At last, data are exported.
Be convenience in order to illustrate, 502 pairs of x coordinates operations of following discussion supposition one-dimensional prediction filter, 504 pairs of y coordinates operations of one-dimensional prediction filter.Any one of one-dimensional prediction filter 502,504 can be to x coordinate or the operation of y coordinate.Therefore, those skilled in the art can recognize one-dimensional prediction filter the 502, the 504th from following explanation, how to operate.
With reference to figure 6, this illustrates the structure of one-dimensional prediction filter 502,504.The structure of each one-dimensional prediction filter 502,504 is all identical.They respectively comprise three registers 601,602,603 that receive data.Data in register 602 are delivered to multiplier 604.In summing circuit 605 result of multiplier 604 is added on the data in the register 601, its result delivers to register 606.
Data in the register 603 are delivered to multiplier 607, then the result are delivered to register 608.In summing circuit 609, the data in the register 606 are added on the data in the register 608, its result delivers to register 610.
In addition, three registers 611,612,613 pass through each one-dimensional prediction filter 502,504 to control information.All can be via two line interfaces by the data division of one-dimensional prediction filter 502,504 and the data of control register.In addition, the output of the input of register 601,602,603 and register 610 also can be two line interfaces.
Three information signals will be configured in work to indicate which kind of mode and which kind of by predictive filter system 400.First signal is the h261_on signal.If this signal is effective, then the H261 standard is in work.If this invalidating signal, then mpeg standard is in work.
The interpolation that second and the 3rd signal xdim and ydim are illustrated in the motion vector defined of a specific direction is with half-pixel or based on whole pixel.If xdim invalidating signal, the then integral multiple of a pixel of the motion vector of x direction regulation.If the xdim signal is effective, then the motion vector of x direction is stipulated the integral multiple of half-pixel.The ydim signal is stipulated identical biography breath on the y direction.
Because H.261 only allow motion vector to be accurate to integer pixel, so xdim and ydim signal are always invalid when the h261_on signal is effective.As shown in Figure 7, each piece 700 of eight row of eight pixels 701 of the predictive filter system 400 every row of output.In addition, as will be described to the function of one-dimensional prediction filter 502,504 under every kind of mode of operation, the size of exporting the required input block of the piece of eight pixels of eight row depends on whether xdim or ydim be effective.Say that in detail if the xdim signal is effective, then input block must have 9 pixels on the x direction; If the xdim invalidating signal, then input block must have 8 pixels on the x direction.If the ydim signal is effective, then input block must have 9 pixels on the y direction; If the ydim invalidating signal, then input block must have 8 pixels on the y direction.This is summarised in the following table.
H261_on xdim ydim function
0 0 0 Fi=xi
The piece of 001 MPEG8 * 9
The piece of 010 MPEG9 * 8
The piece of 011 MPEG9 * 9
100 H261 low pass filters
101 is illegal
110 is illegal
111 is illegal
The operation of each one-dimensional prediction filter 502,504 is because of MPEG and H.261 operation is different, below will describe according to every kind of mode of operation.Because H.261 operation is more complicated, so at first describe this operation.
Under mode H.261, each one-dimensional prediction filter 502,504 is realized following standard one-dimensional filtering device mode:
F
i=x
i(other situation)
Because xdim and ydim are invalid all the time under mode H.261, so input block is eight row, eight pixels of every row.Therefore, Fig. 7 has accurately represented input block and these two kinds of pieces of IOB of predictive filter system 400 under the H261 mode.
One dimension x coordinate predictive filter 502 equation (1) be applied to piece 700 each the row, 504 each row that this equation is applied to piece 700 of one dimension y coordinate predictive filter.Referring to Fig. 6, the pixel value x in the equation (1)
I-1, x
iAnd x
I+1Be respectively charged into register 601,602,603.
Pixel value x
iMultiply by two with multiplier 604, in summing circuit 605, be added to pixel value x then
I-1On, load register 606 as a result.Pixel value x in register 603
I+1Pass through multiplier 607 without changing ground, and load register 608.At last, in summing circuit 609, the numerical value in register 606 and 608 is added to together load register 610.
Above process is that the pixel in a delegation or the row scope realizes H.261 equation.For for the initial and last pixel in delegation or the row realizes H.261 equation, register 601 and 603 is resetted.Pixel value x
iFlow through register 602 and by multiplier 604 quadruplications.Its result without flowing through register 606 and 610, because summing circuit 605 and 609 is added to pixel value x to zero separately with changing
iOn.
Must be noted that the value that is drawn by above realization equals four times of one-dimensional filtering device equation institute requirement result.In order to keep the arithmetic accuracy, after carrying out x direction and y trend pass filtering, realize divided by 16 by moving right 4 at input to predictive filter adder 403.
In MPEG operating period, one-dimensional prediction filter 502,504 is carried out simple half-pix interpolation:
F
i=x
i(0≤i≤7, whole pixel)
For initial and last pixel in delegation or the row, the operation of one dimension predictive filter 502 is identical with the above-mentioned motion compensation with H.261 operating relevant integer pixel under the MPEG mode.For the MPEG mode with the half-pix operation, register 601 resets always, pixel value x
iLoad register 602, pixel value x
I+1Load register 603.Pixel value x in the register 602
iMultiply by 2 by multiplier 604, the pixel value x in the register 603
I+1Multiply by 2 by multiplier 607.These values are obtained to be four times in required result's value then mutually in summing circuit 609.H.261 as described in operating as above combination, this is revised at the input of row predictive filter adder 403.
In operation H.261, predictive filter formatter 501 guarantees that just data deliver to the first one-dimensional prediction filter 502 with proper order.This just needs three grades of shift registers, and its first order is received the input of register 603, and the input of register 602 is received in the second level, and the third level is received the input of register 601.
In the MPEG operation, operate more simple.For the half-pix interpolation, 501 needs secondarys of predictive filter formatter shift register.The first order is connected to the input of register 603, and the second level is connected to the input of register 602.For whole picture element interpolation, the input of register 602 delivered to current pixel value by 501 need of predictive filter formatter.
Under mode H.261, between one dimension x coordinate predictive filter 502 and one dimension y coordinate predictive filter 504, dimension buffer 503 buffered datas make that being one group with three vertical pixels delivers to one dimension y coordinate predictive filter 504 to each group.Therefore in predictive filter system 400, do not carry out matrix transpose operation.Dimension buffer 503 must be enough greatly to keep two row pixel values of eight pixels of every row.From the order of the pixel of dimension buffer 503 output shown in the following table.
Clock input pixel output pixel clock input pixel output pixel
1 0 55a 17 16 7
2 1 56 18 17 F(0,8,16)b
3 2 57 19 18 F(1,9,17)
4 3 58 20 19 F(2,10,18)
5 4 59 21 20 F(3,11,19)
6 5 60 22 21 F(4,12,20)
7 6 61 23 22 F(5,13,21)
8 7 62 24 23 F(6,14,22)
9 8 63 25 24 F(7,15,23)
10 9 0 26 25 F(8,16,24)
11 10 1 27 26 F(9,17,25)
12 11 2 28 27 F(10,18,26)
13 12 3 29 28 F(11,19,27)
14 13 4 30 29 F(12,20,28)
15 14 5 31 30 F(13,21,29)
16 15 6 32 31 F(14,22,30)
Illustrate:
A. last column of lastblock pixel is not if perhaps have lastrow (perhaps if block and piece
Between the gap long) time invalid data.
B.F (x) is illustrated in the function in the filter equation H.261.
In the MPEP operation, one dimension y coordinate predictive filter 504 once only needs two pixels.So, 503 one-row pixels values that need eight pixels of buffering of dimension buffer.
It should be noted that after data are passed through one dimension x coordinate predictive filter 502 in delegation, just to have only eight pixels, because filtering operation has become the line translation of nine pixels the row of eight pixels.The pixel of " losing " replaces with the gap in data flow.When carrying out the half-pix interpolation, one dimension x coordinate predictive filter 502 inserts a gap at the end of each eight pixel column; One dimension y coordinate predictive filter 504 inserts eight gaps at one end.
In MPEG operating period, can be according to early frame, a later frame or the two on average predict.Prediction according to frame formation early is called forward prediction, and the prediction that forms according to later frame is called back forecast.Actually predictive filter adder 403 is determined forward prediction that the logarithm value forecasting institutes are using, back forecast, or the two all uses.Predictive filter adder 403 is by the mean value that rounds towards the positive infinity direction of forward prediction value or back forecast value or these two then.
State variable fwd_on and bwd_on determine whether to use forward direction or back forecast value respectively.At any time, these two state variables or all effective or all invalid or one of them is effective.If when starting or because do not have valid data the gap to occur and exist at the input of predictive filter adder 403, then predictive filter adder 403 enters that not have state variable be effective state.
Predictive filter adder 403 makes state variable fwd_on and bwd_on effective or invalid according to four signs or signal.These signs or signal are fwd_ima_twin, fwd_p_num, bwd_ima_twin and bwd_p_num, and they are essential, because the sequence of back forecast and forward prediction piece can not appear at the input of row predictive filter adder 403 in order.
Determine as follows by the prediction mode that state variable fwd_on and bwd_on represent:
(1) if exist forward prediction piece and fwd_ima_twin effective, then this forward prediction piece stops and arrives up to the set of back forecast piece with bwd_ima_twm.Then make state variable fwd_on and bwd_on effective, predictive filter adder 403 is asked the mean value of forward prediction piece and back forecast piece.
(2) same, if exist back forecast piece and bwd_ina_twin effective, then this back forecast piece stops and arrives up to the set of forward prediction piece with fwd_ima_twin.Then make state variable fwd_on and bwd_on effective, predictive filter adder 403 is asked the mean value of forward prediction piece and back forecast piece.
(3) if but exist forward prediction piece fwd_ima_twin invalid, then check fwd_p_num.Fwd_p_num is the variable of two bits.If fwd_p_num equals to add one from the number of last time, then make state variable fwd_on effectively, state variable bwd_on is invalid.Predictive filter adder 403 output forward prediction pieces.
(4) if but exist back forecast piece bwd_ima_twin invalid, then check bwd_p_num.As fwd_p_num, bwd_p_num is the variable of two bits.If bwd_p_num equals to add one from the number of last time prediction, then make state variable bwd_on effectively, state variable fwd_on is invalid.Predictive filter adder 403 output back forecast pieces.
Prediction mode can only change between each piece 700.When this condition appears at and starts and signal fwd_lst_byte and/or bwd_lst_byte effectively after.These signals are indicated the last byte of current prediction piece.If current block 700 uses forward prediction, then only check fwd_lst_byte; If it uses back forecast, then only check bwd_lst_byte; If it is bi-directional predicted that its uses, then fwd_lst_byte and bwd_lst_byte the two all check.
Signal ima_twin and p_num do not transmit along the line identical with the prediction blocks of data in forward direction and the backward filter 401,402.Its reason comprises:
(1) signal ima_twin and p_num only just check when fwd_lst_byte and/or bwd_lst_byte are effective.This has just saved in each of predictive filter 401,402 on the line of 25 three bits and has communicated by letter.
(2) signal ima_twin and p_num remain valid in monoblock, and therefore signal ima_twin and p_num are effective when fwd_lst_byte and/or bwd_lst_byte arrival predictive filter adder 403.
(3) before a clock cycle of prediction blocks of data, check signal ima_twin and p_num signal.
When the ED that before ED, detects from predictive filter system 400 from FIFO, from surplus continuation of the data of FIFO unchangeably from 13 outputs of prediction adder.On the other hand, if recently the data from FIFO are long from the data of predictive filter system 400, then the data that are input to prediction adder 13 from FIFO are stopped up to accepting and abandon whole excessive datas from predictive filter system 400.
Though with reference to preferred embodiment and remodeling thereof the present invention has been done to illustrate especially and describe, those skilled in the art can understand and can not break away from the spirit and scope of the present invention making all changes aspect form and the details.
Claims (8)
1. circuit of handling video information comprises:
The first and second predictive filter circuit, be used for the parallel processing video information, wherein said information is encoded according to a standard of selecting from a plurality of compression standards, and wherein said each predictive filter circuit is identical in fact and be to come internal configurations according to the requirement of the compression standard of described selection; And
Control signal, it has the state that representative is used for disposing the described selection compression standard that described first and second circuit use, to allow to handle the vision signal of encoding according to this standard.
2. circuit as claimed in claim 1, wherein:
The described first predictive filter circuit comprises the forward prediction filter; And
The described second predictive filter circuit comprises the back forecast filter.
3. filter circuit that is used to carry out video decompression comprises:
The predictive filter formatter that comprises a plurality of multi-stage shift registers with the predesigned order dateout;
Effectively be connected to the first one-dimensional prediction filter of described predictive filter formatter with line;
Effectively be connected to the dimension buffer of the described first one-dimensional prediction filter with line; And
Effectively be connected to the second one-dimensional prediction filter of described dimension buffer with line.
4. filter circuit as claimed in claim 3, wherein each described effective connecting line comprises two line interfaces.
5. as claim 3 or 4 described filter circuits, wherein:
The described first one-dimensional prediction filter comprises one dimension x coordinate predictive filter; The described second one-dimensional prediction filter comprises one dimension y coordinate predictive filter.
6. as any described filter circuit of above claim, wherein:
The described first one-dimensional prediction filter comprises one dimension x coordinate predictive filter; And
The described second one-dimensional prediction filter comprises one dimension y coordinate predictive filter.
7. as any described filter circuit of above claim, wherein each described one-dimensional prediction filter further comprises:
First register;
Second register;
Effectively be connected to first multiplier of described second register with line;
Effectively be connected to described first register and effectively be connected to first summing circuit of described first multiplier with line with line;
Effectively be connected to the 3rd register of described first summing circuit with line;
The 4th register;
Effectively be connected to second multiplier of described the 4th register with line;
Effectively be connected to the 5th register of described second multiplier with line;
Effectively be connected to described the 3rd register and effectively be connected to second summing circuit of described the 5th register with line with line; And
Effectively be connected to the 6th register of described second summing circuit with line.
8. as any described filter circuit in the above claim, wherein said video information is encoded according to mpeg standard.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB9405914A GB9405914D0 (en) | 1994-03-24 | 1994-03-24 | Video decompression |
| GB9405914.4 | 1995-02-28 | ||
| GB9504047.3 | 1995-02-28 | ||
| GB9504047A GB2288521B (en) | 1994-03-24 | 1995-02-28 | Reconfigurable process stage |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN95103246A Division CN1137212A (en) | 1994-03-24 | 1995-03-24 | Treating stage capable of reconfigurating |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1235483A true CN1235483A (en) | 1999-11-17 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN95103246A Pending CN1137212A (en) | 1994-03-24 | 1995-03-24 | Treating stage capable of reconfigurating |
| CN98103849A Pending CN1235483A (en) | 1994-03-24 | 1998-02-16 | Prediction filter |
Family Applications Before (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN95103246A Pending CN1137212A (en) | 1994-03-24 | 1995-03-24 | Treating stage capable of reconfigurating |
Country Status (5)
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| JP (4) | JP3302527B2 (en) |
| KR (1) | KR100291532B1 (en) |
| CN (2) | CN1137212A (en) |
| CA (3) | CA2145219C (en) |
| GB (1) | GB2288521B (en) |
Families Citing this family (20)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2794601B1 (en) * | 1999-06-02 | 2001-07-27 | Dassault Automatismes | COMMUNICATION DEVICE FOR COLLECTIVE INFORMATION RECEPTION, IN PARTICULAR OF DIGITAL TELEVISION IMAGES AND / OR MULTIMEDIA DATA |
| EP1148727A1 (en) * | 2000-04-05 | 2001-10-24 | THOMSON multimedia | Method and device for decoding a digital video stream in a digital video system using dummy header insertion |
| KR100354768B1 (en) | 2000-07-06 | 2002-10-05 | 삼성전자 주식회사 | Video codec system, method for processing data between the system and host system and encoding/decoding control method in the system |
| US8284844B2 (en) | 2002-04-01 | 2012-10-09 | Broadcom Corporation | Video decoding system supporting multiple standards |
| KR100722428B1 (en) * | 2005-02-07 | 2007-05-29 | 재단법인서울대학교산학협력재단 | Resource Sharing and Pipelining in Coarse-Grained Reconfigurable Architecture |
| US7873105B2 (en) | 2005-04-01 | 2011-01-18 | Broadcom Corporation | Hardware implementation of optimized single inverse quantization engine for a plurality of standards |
| KR100711088B1 (en) * | 2005-04-13 | 2007-04-24 | 광주과학기술원 | Integer Transform Device for Moving Picture Encoder |
| KR100718135B1 (en) | 2005-08-24 | 2007-05-14 | 삼성전자주식회사 | apparatus and method for video prediction for multi-formet codec and the video encoding/decoding apparatus and method thereof. |
| KR101354659B1 (en) * | 2006-11-08 | 2014-01-28 | 삼성전자주식회사 | Method and apparatus for motion compensation supporting multicodec |
| JP5698428B2 (en) * | 2006-11-08 | 2015-04-08 | 三星電子株式会社Ｓａｍｓｕｎｇ Ｅｌｅｃｔｒｏｎｉｃｓ Ｃｏ．，Ｌｔｄ． | Motion compensation method, recording medium, and motion compensation device |
| KR101553648B1 (en) | 2009-02-13 | 2015-09-17 | 삼성전자 주식회사 | A processor with reconfigurable architecture |
| BR112012024462A2 (en) * | 2010-04-02 | 2016-05-31 | Fujitsu Ltd | orthogonal coverage code (occ) apparatus and method, and occ mapping apparatus and method |
| US8413166B2 (en) * | 2011-08-18 | 2013-04-02 | International Business Machines Corporation | Multithreaded physics engine with impulse propagation |
| US10219006B2 (en) * | 2013-01-04 | 2019-02-26 | Sony Corporation | JCTVC-L0226: VPS and VPS_extension updates |
| US9395990B2 (en) * | 2013-06-28 | 2016-07-19 | Intel Corporation | Mode dependent partial width load to wider register processors, methods, and systems |
| JP6223323B2 (en) * | 2014-12-12 | 2017-11-01 | Ｎｔｔエレクトロニクス株式会社 | Decimal pixel generation method |
| CN107735953B (en) * | 2015-07-03 | 2023-04-14 | 英特尔公司 | Apparatus and method for data compression in a wearable device |
| CN107729989B (en) * | 2017-07-20 | 2020-12-29 | 安徽寒武纪信息科技有限公司 | Device and method for executing artificial neural network forward operation |
| CN109901044B (en) * | 2017-12-07 | 2021-11-12 | 英业达科技有限公司 | Central processing unit differential test system of multiple circuit boards and method thereof |
| CN113591795B (en) * | 2021-08-19 | 2023-08-08 | 西南石油大学 | Lightweight face detection method and system based on mixed attention characteristic pyramid structure |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US4680581A (en) * | 1985-03-28 | 1987-07-14 | Honeywell Inc. | Local area network special function frames |
| DE69229338T2 (en) * | 1992-06-30 | 1999-12-16 | Discovision Ass | Data pipeline system |
| US5325092A (en) * | 1992-07-07 | 1994-06-28 | Ricoh Company, Ltd. | Huffman decoder architecture for high speed operation and reduced memory |
| US5298896A (en) * | 1993-03-15 | 1994-03-29 | Bell Communications Research, Inc. | Method and system for high order conditional entropy coding |
| US5699460A (en) * | 1993-04-27 | 1997-12-16 | Array Microsystems | Image compression coprocessor with data flow control and multiple processing units |
-
1995
- 1995-02-28 GB GB9504047A patent/GB2288521B/en not_active Expired - Lifetime
- 1995-03-22 CA CA002145219A patent/CA2145219C/en not_active Expired - Fee Related
- 1995-03-22 CA CA002145549A patent/CA2145549C/en not_active Expired - Lifetime
- 1995-03-23 CA CA002145426A patent/CA2145426A1/en not_active Abandoned
- 1995-03-23 KR KR1019950006172A patent/KR100291532B1/en not_active IP Right Cessation
- 1995-03-24 CN CN95103246A patent/CN1137212A/en active Pending
- 1995-03-24 JP JP09001095A patent/JP3302527B2/en not_active Expired - Lifetime
- 1995-09-13 JP JP7266757A patent/JPH08116260A/en active Pending
- 1995-09-13 JP JP7266747A patent/JPH0918871A/en active Pending
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1998
- 1998-02-16 CN CN98103849A patent/CN1235483A/en active Pending
- 1998-10-06 JP JP10318260A patent/JPH11266460A/en active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| CA2145426A1 (en) | 1995-09-25 |
| GB2288521A8 (en) | 1996-04-15 |
| GB2288521A (en) | 1995-10-18 |
| JPH08116260A (en) | 1996-05-07 |
| KR100291532B1 (en) | 2001-06-01 |
| CA2145549A1 (en) | 1995-09-25 |
| JPH11266460A (en) | 1999-09-28 |
| CA2145219C (en) | 2001-11-27 |
| GB2288521B (en) | 1998-10-14 |
| CN1137212A (en) | 1996-12-04 |
| JPH0918871A (en) | 1997-01-17 |
| GB9504047D0 (en) | 1995-04-19 |
| KR950033896A (en) | 1995-12-26 |
| JP3302527B2 (en) | 2002-07-15 |
| CA2145219A1 (en) | 1995-09-25 |
| CA2145549C (en) | 2001-02-20 |
| JPH0870453A (en) | 1996-03-12 |
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