GB2246472A - Cooling semiconductor devices - Google Patents
Cooling semiconductor devices Download PDFInfo
- Publication number
- GB2246472A GB2246472A GB9117667A GB9117667A GB2246472A GB 2246472 A GB2246472 A GB 2246472A GB 9117667 A GB9117667 A GB 9117667A GB 9117667 A GB9117667 A GB 9117667A GB 2246472 A GB2246472 A GB 2246472A
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- Prior art keywords
- heat
- thermally conductive
- chip
- semiconductor
- elements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85909—Post-treatment of the connector or wire bonding area
- H01L2224/8592—Applying permanent coating, e.g. protective coating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01014—Silicon [Si]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01039—Yttrium [Y]
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- H01L2924/01057—Lanthanum [La]
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- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12041—LED
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12042—LASER
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
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- H01L2924/14—Integrated circuits
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
Abstract
A semiconductor device comprises a semiconductor chip 21 including a substrate and a plurality of heat emissive elements formed on a surface portion thereof. The semiconductor chip 21 has a thermally conductive layer 23 formed on the chip so as to be in the proximity of the elements in order to conduct and dissipate heat produced by the elements. A thermally conductive plate 22 is provided adjacent the chip 21 and a heat discharging fin 24 is attached to the opposite side of the plate 22 from the chip 21. A second thermally conductive plate 26 and a cooling fin 27 are also provided. In a modification the device is mounted in a duct supplied with cooling fluid. <IMAGE>
Description
CoOY#ING SEMICONDUCTOR DEVICES
This invention relates to-cooling semiconductor devices, and more particularly to an improvement using an arrangement suitable for heat discharge and cooling of the semiconductor device itself for purposes of establishing an ultra-high speed, ultra-high integrated electronic circuit.
Incorporation of semiconductor integrated circuits into an integrated circuit has been developed to meet requirements of a ultra-high speed and a ultra-high density. However, a limit of heat discharge now prevents a further integration density of integrated circuits which consume large power for high speed operations.
A logic circuit, for example, among presently used semiconductor integrated circuits, has the integration rate of 1500 gates per chip approximately. Its power consumption per gate is about 1mW, and heat of about lw is generated per chip. This amount of heat is near the limit of heat charge by normal air-cooling, and it is difficult to further develop such integration by merely diminishing the sizes of elements.
In contrast, power consumption per chip is largely increased due to requirements of increasing the efficiency and the speed of a semiconductor integrated circuit. Large part of the consumed power is changed to heat, and the heat increases the temperature of the entire chip and invites deterioration of the characteristic and the reliability of the element. Since the heating generating portion is a very small operative region and the operation speed is very high, local and transient changes in the temperature are serious problems. Therefore, an existing heat discharging or radiating circuit designed for dealing with static, large regions is not sufficient at all, and the industry desires a high speed heat flow circuit suitable for dynamic, very small regions as well, considering transient conditions of the element during operation.
The problem of heat discharge of an existing semiconductor element is explained below, referring to drawings.
Figures 6 through 10 show existing MOS FET elements using silicon (Si).
The MOS FET element of Figure 6 has a typical structure. Since the structure is symmetrical, Figure 6 shows a quarter of one MOS FET element. Reference numeral 1 denotes a substrate made from p-Si, for example. Numeral 2 refers to a channel, and 3 to a gate electrode made from polycrystalline Si. Numeral ts denotes a gate insulating layer made from, for example, silicon oxide SiO2, and numeral 5 designates a source or drain made from, for example, n Si. Numeral 6 indicates a wiring made from, for example, Al. Numeral 7 designates an insulating layer made from, for example, SIC2.
Numeral 8 denotes an insulating layer made frcm, for example, SiC2. In this typical arrangement, the gate length is 1.3um, and the gate width is 5m. The driving pulse current may be in a standard form of clock frequency 5mHz and pulse width 100n sec (100 nanoseconds).
The thickness of the channel under the gate is about 8nm. The aforementioned pulse current causes generation of Joule heat of heat generating rate 2.9mW near the channel. The initial temperature of the entire element is 20 C, and the surface of the insulating layer 8 discharges heat due to natural convection (heat transfer coefficient 10 3W/cm2"C), Figure 7 shows how the temperature T changes with time around the channel of the MOS FET element. In response to ON and OFF changes of a pulse current, the temperature around the channel exhibits a transient change of n sec. order in a local region of m order.
Figure 8. shows a temperature distribution of an X- plan view of Figure 9 ' at the time 100n sec. later than application of the pulse current, i.e. just after the pulse current is cut off.
The temperature increase of the channel 2 at this time is about t C. However, considering that a significantly large temperature gradient as much as 100"C/Ism approximately is produced in the depth direction (Y direction) in the gate insulating layer 4 and that temperature changes are responsive every several nanoseconds, the resulting local transient heat stress is very large.
Figure 9 shows a temperature distribution of the X-Y plan view at the time 110n-sec. later than application of the pulse current, i.e. 10n sec. later than the pulse current is cut off.
After the pulse current is cut off, the temperature near the channel suddenly drops. Thus in the conventional arrangement of MOS FET element, locally, transiently large temperature changes occur near the channel, and a new heat flow circuit arrangement is required to remove this.
Figures 11 through 15 conventional SOI (silicon on insulator) arrangements for MOS FET elements.
In the MOS FET element having the SOI arrangement of Figure 11, numeral 9 denotes an insulating layer for the SOT arrangement which may be, for example, a SiC2 layer of thickness 2 > m. Numeral 10 designates a semiconductor active layer for the SOI arrangement which may be a typical p-Si layer of thickness 0.3'jim and area 5 x 7# m2 as illustrated. The remainder arrangement is similar to the MOS FET element of Figure 6. To the element of
Figure t1 is fed a pulse current similar to that in the example of Figures 6 through 10.
Figure 12 shows changes in the temperature with time around the silicon active layer and the channel of the aforegoing element. Also in this case, the temperature around the channel 2 exhibits a locally, transiently violent change in response to ON and OFF changes of the pulse current.
Figure 13 shows a temperature distribution of a portion shown in Figure 15 at the time 100n sec. later than application of the pulse current, i.e. just after the pulse current is cut Qff. In this SOl-arranged MOS
FET element, the temperature around the channel 2 is elevated much higher than the above-indicated MOS FET element on the Si substrate, because the heat conduction rate of the insulating layer (ski2) 9 is smaller by two digits or so than Si, heat discharge to the substrate is prevented, and the heat remains in the silicon active layer 10.
The temperature of the channel 2 is about 300C, 100n sec. later than application of the pulse, and it is higher by 60C approximately than the MOS FET element on the Si substrate. Further, in the with of the gate insulating layer 9, a temperature gradient of about 1700C/m is produced in the Y direction, that is, a larger heat stress than the case of the MOS FET element on the Si substrate is generated.
Figure 14 shows a temperature distribution of an X-Y plane portion also shown in Figure 15 at the time 1SOn sec. la-ter than application of the pulse current, i.e. 50n sec. later than the pulse current is cut off.
As compared to Figure 10 , heat remains.
Therefore, in case of the SOI arrangement, heat discharge from the channel 2 to the Si substrate is.
prevented by the insulating layer 9, and a new heat flow circuit arrangement is required to remove the heat
It is therefore an object of one embodiment of the invetlt i^n to provide a selonductor device having a heat flow circuit capable of removing heat from semiconductor elements.
The present invention provides a semiconductor device canprisina a semiconductor chip including a substrate and a plurality of heat emissive semiconductor elements formed on the surface portion of said substrate' said semiconductor chip containing a thermally conductive layer so formed on said chip as to cover said elements and as to be at least locally in proximity of said elements in order to conduct and spread heat flow produced from said elements by a heat flow circuit having said thermally conductive layer; a first thermally conductive plate provided with said chip; and a heat discharging fin attached to the opposite side of said plate to said chip.
Even if the temperature is increased transiently and locally in a heat generating element, the heat is immediately removed by the heat flow circuit including the layer of good thermal conductivity and good ' electrical conductivity material.
Examples of the invention will now be described with reference to the drawings, in which:
Figures 1 is a schematic view of a semiconductor device having heat generating elements;
Figure 2 is a schematic view of a semiconductor device having heat generating elements;
Figure 3 is a schematic view of a semiconductor device having heat generating elements;
Figures 4 and 5 are schematic views of two embodiments of the present invention;
Figure 6 through 10 are views for explaining problems of a conventional MOS FET element;
Figure 11 through 15 are views for explaining problems of a conventional SOI-arranged MOS FET element;
Figure 1 shows a planar type heat flow circuit as a local, transient heat flow circuit throughout the entire chip.In the same drawing, a heat generating element 15 is provided on a substrate 14, and a layer 16 formed of material having a good thermal conductivity and good electrical insulation properties is provided to cover them. The substrate 14 may be of Si, GaAs, InP, A1203 or any other material suitable for forming the heat generating element 15. In this case, the heat generating element 15 may be any semiconductor element such as MOS type transistor, bipolar type transistor, semiconductor laser, light emitting diode, etc. which has a property of a local, transient heat generating source.
The layer 16 may be of any material which has a heat conduction ratio equivalent to a metal and which is an insulator. For example, A1N, BN or the like is preferable. Locally, transiently variable heat generated around the heat generating element 15 is averaged by the planar type heat flow circuit including the layer 16, heat stress is removed, and at the same time, a heat discharge circuit or a cooling circuit (both not shown) provided on the layer 16 efficiently discharges heat to the exterior before the heat extends to the entire chip.
The above-indicated method can also be used in a device in which the heat generating element or the semiconductor chip has a three-dimensional multi-layer structure.
Figure 2 shows a metal-wiring-combined heat flow circuit including the same substrate 14 and heat generating element 15 as those in Figure 1. Locally, transiently variable heat generated around the heat generating element 15 is pumped out by a metal wiring 17. Numeral 18 designates an insulating layer made from a material having good thermal conductivity and good electrical insulation properties. Therefore, in this case, heat is pumped up from the heat generating element 15 by the metal wiring 17, it is subsequently averaged by the layer 16, and it is efficiently discharged to the exterior by a heat discharge circuit or a cooling circuit (both not shown) provided on the layer 16.
Figure 3 shows a through-hole type heat flow circuit. On the substrate 14 is provided a semiconductor element 15 which generates heat according to its purposes.
The substrate 14 may be of any material such as Si, GaAs,
InP, A12O3, SiO2 or the like which is suitable for forming the heat generating element 15. In this case, the heat generating element 15 may be any semiconductor element such as MOS type transistor, bipolar type transistor, semiconductor laser, light emitting diode, etc. which has a property of a local, transient heat generating source.
Although the heat flow circuit is readily configured into a planar type in the arrangement of Figure 1, the periphery of the heat generating element normally has undulations due to the presence of a multi-layer wiring of a mesa construction and this prevents direct provision of such a planar thermally conductive layer.
Therefore, a through hole is formed in the insulating layer 18 up to a portion near the heat generating element, and a thermally conductive layer 19 is formed in the hole. The thermally conductive layer 19 may be of a metal unless it degrades the electric characteristic of the heat generating element 15. In most cases, the layer 19 in the form of such a thermally conductive and electrically conductive layer is designed more easily, and maybe configured to directly contact the heat generating element 15. The thermally conductive and electrically insulating layer can be made from A1N, BN, etc. for example.
In the example of Figure 3, a further through hole is provided in the substrate, and a thermally conductive layer 20 is formed therein, so that heat is removed from the substrate side as well. However, the device is effective, with the through hole type heat flow circuit 19 or 20 alone.
The thermally conductive layer 20 may be of a metal unless it degrades the electric characteristic of the heat generating element 15. In most cases, the layer 20 in the form of a thermally conductive and electrically insulating layer is designed more easily, and may be configured to directly contact the heat generating element 15. The thermally conductive and electrically insulating layer can be made of A1N, BN, etc. for example.
A heat discharge circuit or a cooling circuit (both not shown), which is provided next to the layers 19 and 20, efficiently discharges the heat to the exterior before the heat extends to the entire chip.
Figure 4 shows one embodiment of the present invention which uses a heat discharge circuit in the form of an air cooling fin.
A chip 21 includes the aforementioned heat flow circuit, and the heat generating element in the chip is a semiconductor element such as MOS type transistor, bipolar type transistor, semiconductor laser, light emitting diode, etc. which generates heat locally and transiently due to its high speed operation. In order to connect the chip 21 to a heat radiating fin 24, it is designed to remove heat from both the front and back sides of the chip. One side of the chip is attached to a thermally conductive plate 22 (preferably of an electrical insulator such as A1N, BN, etc. in most cases, or an Al or Cu plate, etc. if a metal is employable), and heat is transmitted to the heat radiating fin 22. The other side of the chip is covered by the thermally conductive layer 23 (of A1N, BN, etc. for example) to fill a gap between the thermally conductive plate 26 and itself, and heat is transmitted to a heat radiating fin 27.
Numeral 25 designates a mount board. Since the local, transient heat generated in the chip is discharged to the exterior in this fashion before the heat extends in the transversal direction of the chip, high speed operation is stabilised.
Figure 5 shows another heat discharge or cooling circuit. As is used in the arrangement of Figure 4, numeral 21 refers to a chip 22 to a thermally conductive plate, 23 to a thermally conductive layer, 24 and 27 to heat radiating fins, and 25 to a mount board. In this embodiment, coolant 28 flows along a coolant circulating tube 29. The coolant 28 may be'any material suitable for cooling, such as Freon, water, etc.
Thus this embodiment can efficiently remove from the chip a much more amount of heat than in the air cooling, and ensures a more stable high speed operation.
As described above, where a semiconductor element itself or a semiconductor chip includes a heat flow circuit which is responsive transiently and capable of removing heat from small regions, the integrating density of electronic circuits is increased, high speed operation is stabilised, and functions of the semiconductor element are remarkably enhanced.
Claims (4)
1. A semiconductor device comprising a semiconductor chip including a substrate and a plurality of heat emissive semiconductor elements formed on the surface portion of said substrate; said semiconductor chip containing thermally conductive layer so formed on said chip as to cover said elements and as to be at least locally in proximity of said elements in order to conduct and spread heat flow produced from said elements by a heat flow circuit having said thermally conductive layer; a first thermally conductive plate provided with said chip; and a heat discharging fin attached to the opposite side of said plate to said chip.
2. A semiconductor device according to Claim 1 wherein said chip attached to said thermally conductive plate is covered by said thermally conductive layer.
3. A semiconductor device according to Claim 2 which further includes a second thermally conductive plate so provided as to contact with said thermally conductive layer, and a heat discharging fin attached to the opposite side face of said second thermally conductive plate to the face contacting with the thermally conductive layer.
4. A semiconductor device device as hereinbefore described with reference to either of Figures 4 or 5 of the drawings.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB9117667A GB2246472A (en) | 1988-08-23 | 1991-08-15 | Cooling semiconductor devices |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20976488A JPH0258254A (en) | 1988-08-23 | 1988-08-23 | Semiconductor element |
| JP63209765A JPH07120735B2 (en) | 1988-08-23 | 1988-08-23 | Semiconductor chip |
| GB9117667A GB2246472A (en) | 1988-08-23 | 1991-08-15 | Cooling semiconductor devices |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| GB9117667D0 GB9117667D0 (en) | 1991-10-02 |
| GB2246472A true GB2246472A (en) | 1992-01-29 |
Family
ID=27265827
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB9117667A Withdrawn GB2246472A (en) | 1988-08-23 | 1991-08-15 | Cooling semiconductor devices |
Country Status (1)
| Country | Link |
|---|---|
| GB (1) | GB2246472A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2279807A (en) * | 1993-07-06 | 1995-01-11 | Hewlett Packard Co | A heat sink assembly for a multi-chip module |
| EP0786806A1 (en) * | 1996-01-23 | 1997-07-30 | Montpellier Technologies | High I/O density package for high power wire-bonded IC chips and method for making the same |
| US6180436B1 (en) * | 1998-05-04 | 2001-01-30 | Delco Electronics Corporation | Method for removing heat from a flip chip semiconductor device |
| US6607942B1 (en) * | 2001-07-26 | 2003-08-19 | Taiwan Semiconductor Manufacturing Company | Method of fabricating as grooved heat spreader for stress reduction in an IC package |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1587865A (en) * | 1976-12-06 | 1981-04-08 | Ibm | Electrical components |
| WO1983002527A1 (en) * | 1982-01-07 | 1983-07-21 | Ncr Co | Holding device for an integrated circuit chip |
| US4561011A (en) * | 1982-10-05 | 1985-12-24 | Mitsubishi Denki Kabushiki Kaisha | Dimensionally stable semiconductor device |
| EP0224141A2 (en) * | 1985-11-21 | 1987-06-03 | General Electric Company | Improved semiconductor power devices |
| US4715430A (en) * | 1986-10-27 | 1987-12-29 | International Business Machines Corporation | Environmentally secure and thermally efficient heat sink assembly |
| EP0295387A2 (en) * | 1987-06-15 | 1988-12-21 | International Business Machines Corporation | Package for heat dissipation of electronic components |
| US4825284A (en) * | 1985-12-11 | 1989-04-25 | Hitachi, Ltd. | Semiconductor resin package structure |
-
1991
- 1991-08-15 GB GB9117667A patent/GB2246472A/en not_active Withdrawn
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1587865A (en) * | 1976-12-06 | 1981-04-08 | Ibm | Electrical components |
| WO1983002527A1 (en) * | 1982-01-07 | 1983-07-21 | Ncr Co | Holding device for an integrated circuit chip |
| US4561011A (en) * | 1982-10-05 | 1985-12-24 | Mitsubishi Denki Kabushiki Kaisha | Dimensionally stable semiconductor device |
| EP0224141A2 (en) * | 1985-11-21 | 1987-06-03 | General Electric Company | Improved semiconductor power devices |
| US4825284A (en) * | 1985-12-11 | 1989-04-25 | Hitachi, Ltd. | Semiconductor resin package structure |
| US4715430A (en) * | 1986-10-27 | 1987-12-29 | International Business Machines Corporation | Environmentally secure and thermally efficient heat sink assembly |
| EP0295387A2 (en) * | 1987-06-15 | 1988-12-21 | International Business Machines Corporation | Package for heat dissipation of electronic components |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2279807A (en) * | 1993-07-06 | 1995-01-11 | Hewlett Packard Co | A heat sink assembly for a multi-chip module |
| US5396403A (en) * | 1993-07-06 | 1995-03-07 | Hewlett-Packard Company | Heat sink assembly with thermally-conductive plate for a plurality of integrated circuits on a substrate |
| GB2279807B (en) * | 1993-07-06 | 1997-05-21 | Hewlett Packard Co | A heat sink assembly for a multi-chip module |
| EP0786806A1 (en) * | 1996-01-23 | 1997-07-30 | Montpellier Technologies | High I/O density package for high power wire-bonded IC chips and method for making the same |
| US6180436B1 (en) * | 1998-05-04 | 2001-01-30 | Delco Electronics Corporation | Method for removing heat from a flip chip semiconductor device |
| US6607942B1 (en) * | 2001-07-26 | 2003-08-19 | Taiwan Semiconductor Manufacturing Company | Method of fabricating as grooved heat spreader for stress reduction in an IC package |
Also Published As
| Publication number | Publication date |
|---|---|
| GB9117667D0 (en) | 1991-10-02 |
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| WAP | Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1) |