GB2223620A

GB2223620A - Audio message storing circuit and control method therefor

Info

Publication number: GB2223620A
Application number: GB8919558A
Authority: GB
Inventors: Yong Kyo Oh
Original assignee: Gold Star Co Ltd
Current assignee: LG Electronics Inc
Priority date: 1988-08-30
Filing date: 1989-08-30
Publication date: 1990-04-11
Anticipated expiration: 2009-08-30
Also published as: JPH0734277B2; KR900003837A; DE3928664C2; DE3928664A1; JPH02126452A; GB2223620B; GB8919558D0

Abstract

An audio message storing circuit and control method therefor in a video cassette recorder capable of recording audio information simultaneously with a timer program and outputting said stored audio information at the programmed time by means of a speaker. The circuit comprises: key matrix (1), timer microcomputer (2), communication processor (3), microphone (4), analog/digital converter (5), RAM (6), gate and hold circuit (7), digital/analog converter (8), low band pass filter (9), amplifier (10), and speaker (11). The control method comprises storing audio information in the RAM after converting to a digital signal, setting a timer program, reading out the stored information sequentially and then converting to analog signal and outputting through the speaker at the programmed time. <IMAGE>

Description

AUDIO MESSAGE STORING CIRCUIT AND CONTROL METHOD THEREFOR The present invention relates to a video cassette recorder, and more particularly to an audio message storing circuit and control method therefor in which a user may record directly audio information and may output at a desired time.

In general, a video cassette recorder is designed to play back a recorded tape, and to record other video signals onto tape.

Recently, the manufacturing technique of a video cassette recorder has developed and allows recording the content of a broadcast program not presently being viewed, and is provided with a timer program recording function by which a time to record may be set in advance and automatically the recording is carried out at said set time. The recorder may also be provided with the function of setting a number of time bands and automatically executing the video recording in the sequence of said set time program.

More convenience to the user is provided if an audio signal of a user can be stored by the video cassette recorder, and output at a program recording time. Nevertheless, such functions are not provided in the conventional video cassette recorder.

Therefore, it is an object of the present invention to provide an audio message storing circuit and control method therefor in which a timer program is set at the same time as audio information of a user is stored into a memory, and the stored audio information is output from a speaker at said program set time.

Such object of the present invention is accomplished by setting a timer program, converting audio information of a user which is input from a microphone into a digital signal and storing it in a memory, reading out said digital signal stored in the memory at said program set time, holding said digital audio signal and converting it to analog signal, and passing the audio signal converted to the analog signal through a low pass filter and then amplifying it and outputting through a speaker.

The foregoing and other objects as well as advantages of the present invention will become clear by the following description of an embodiment of the invention with reference to the accompanying drawings.

Figure 1 is a block diagram illustrating an audio message storing circuit of the present invention, Figures 2A and 2B are wave form charts illustrating the output wave form representing the operation of each related portion of Figure 1, Figure 3 is a flow chart for controlling a timer microcomputer of Figure 1, and Figure 4 is a flow chart for controlling a transmitting processor of Figure 1.

Referring to Figure 1, an audio message storing circuit of this embodiment comprises a key matrix 1 for executing a key input, a timer microcomputer 2 for executing various controls upon the input of the key signals of said key matrix 1, a communication processor 3 for executing control of writing and reading of audio signal data upon the control of said timer microcomputer 2, a microphone 4 for converting the audio signal into an electric signal, an analog/digital converter 5 for converting the output of the microphone 4 into a digital signal of 8 bits under the control of the communication processor 3, and applying the digital signal of 8 bits to the communication processor 3, a RAM 6 for storing the audio signal data being input from said analog/digital converter 5 at the communication processor 3, a gate and hold circuit 7 for transmitting the audio signal data read out of the RAM 6 upon the control of the communication processor 3, a digital/analog converter 8 for converting the output signal of the gate and hold circuit 7 into analog signal, a low pass filter 9 for passing only signals of a low frequency band from the output signals of the digital/analog converter 8, an amplifier 10 for amplifying the output signal of the low band pass filter 9, and a speaker 11 for outputting the output signal of said amplifier 10 into an audio signal.The key matrix 1 includes a slide switch SW1 for switching the system to a program state or a normal state, a program number key SW2 for increasing the program number, an hour key SW3 and a minute key SW4 for setting the time, a memory key SW5 for instructing the recording of the audio signal data, and a transmission message key SW6 for instructing the transmission of the audio signal data.

Figures 2A and 2B are wave form charts of the output wave forms illustrating the operation of each related portion of Figure 1, in which Figure 2A shows wave form charts of the outputs of the timer microcomputer 2 and communication processor 3 at the time of recording the audio signal data to RAM 6, and Figure 2B shows wave form charts of the outputs of the timer microcomputer 2 and communication processor 3 at the time of reading out the audio signal data from RAM 6. Figure 3 is a flow chart of the control of the timer microcomputer 2 in response to the key input of the key matrix 1, and Figure 4 is a flow chart of the control of the communication processor 3 in response to the timer microcomputer 2.

The operation and effect of the present embodiment will be desribed in detail with reference to Figures 1 to 4 as follows The timer microcomputer 2 outputs a scan signal at the scan signal output terminals Scl and Sc2 and searches signals of the input terminals I1 to I4, so that the key signals of the key matrix 1 are detected.

The setting of key matrix 1 is examined by the timer microcomputer 2 in this manner and control is executed as in the flow chart of Figure 3. That is, when the program switch SW1 is shorted to the program terminal P and the transmission key SW6 is not set, the microcomputer 2 responds by entering the message setting mode.

When the program key SW2 is pressed in this state, the timer microcomputer 2 increases the program number PN by "1", and at that time the timer program is set at the timer microcomputer 2 in accordance with operation of the hour key SW3 and minute key SW4. When the memory key SW5 is pressed in order to write in audio signal data in this state, the timer microcomputer 2 detects the pressed state of the memory key SW5. According to this, as shown in Figure 2A, the address signal in accordance with said program number PN is output to its address signal terminal AD1, at the same time, a high potential signal is output to the communication processor signal terminal CSl and input control signal terminal IN.

Accordingly, at this moment, the communication processor 3 receives and writes the audio signal data as in flow chart of Figure 4. That is, at this moment, the communication processor 3 sets a predetermined time (TC: for example, 5 seconds) to its interior time counter and thereafter the address signal according to the address signal output from said timer microcomputer 2 is output to the address signal terminal AD2 designating the start address of RAM 6, and a high potential signal is output to the control signal terminal C1 as shown in Figure 2A to operate the analog/digital converter 5. As a result, the output audio signal of the microphone 4 is converted into a digital signal of 8 bits at the analog-digital converter 5 and is applied to the data terminal (Data 1) of the communication processor 3.At this moment, the communication processor 3 sequentially receives the signals applied to its data terminal (Data 1), for example, it receives three data signals DA1, DA2 and DA3 sequentially and determines the differences of DA1 and DA2, and of DA2 and DA3 respectively, and the two difference signals are converted respectively into 4 bits code and these are combined to form 8 bits code data. The 8 bits of code data are output to the data terminal (Data 2) and applied to RAM 6. Furthermore, at this moment, a high potential signal as shown in Figure 2A is output from said communication processor 3 to the control signal terminal C2. At the same time, the write control signal of low potential is output to the read/write control signal terminal R/W and the 8 bits code data output to the data terminal (Data 2) are written to the designated address of said RAM 6.Thereafter, the communication processor 3 outputs a low potential signal to the control signal terminal C2, and the address signal being output to the address signal terminal AD2 is increased by "1". Thereafter, the digital signals are received at the analog/digital converter 5 by the method as aforementioned and converted to 8 bits code data and then written in again to the designated address of RAM 6 and the operation as above is repeated during the predetermined time period. Therefore, the audio signal being input through the microphone 4 during the predetermined time period TC is converted sequentially to 8 bits code data and written in to the designated address of RAM 6.

When a predetermined time counting TC is completed by the communication processor 3, a high potential signal of the time count completion signal is output and applied to the terminal CP1 of the timer microcomputer. The timer microcomputer 2 thereby outputs a low potential signal to its control signal terminal CS1 and to the input control signal terminal IN as shown in Figure 2A and Figure 3, and ends the write control operation of the audio signal data.

On the other hand, when the transmissions message key is set, the timer microcomputer 2 executes the transmission control operation of the audio signal data as shown in the flow chart of Figure 3. That is, at this moment, the timer microcomputer 2 sets the program address PAD to "0", at the same time, sets the number of the transmission MSC to "0", and thereafter determines whether or not the present time is equal to the programmed time in accordance with said program address PAD.

If it is not equal, it increases said program address PAD by "1", and then determines again whether or not the present time is equal to the programmed time in accordance with the program address PAD.

These processes are executed repeatedly until the program address PAD becomes "8". On the other hand, when the present time is equal to the programmed time in accordance with the program address PAD, it outputs said program address PAD to its address signal terminal AD1, and at the same time, outputs a high potential signal to its communication processor control signal terminal CS1 and to the output control signal terminal OUT as shown in Figure 2B. Therefore, at this moment, the communication processor 3 reads out the audio signal data written in RAM 6 and starts to transmit.At this moment, the communication processor 3 sets a predetermined time period (TC: for example, 5 seconds) to its interior counter, and then outputs from its address signal terminal AD2 the address signal in accordance with the address signal being output from the address signal terminal AD1 of said timer microcomputer 2, thereby designating the address of RAM 6, and thereafter outputs a high potential signal to the control signal terminal C2 as shown in Figure 2B, and reads out the 8 bits code data written in the designated address of said RAM 6. Thereafter it outputs a low potential signal to its control signal terminal C2 as shown in Figure 2B.

As the 8 bits code data read out from the communication processor 3 are the combination of each of two 4 bit data signals the data read is divided into two and then changed to the difference of the previous 8 bits signal and converted to two 8 bits data ODA1 and ODA2. Thereafter, the communication processor 3 outputs 8 bits data ODA1 as shown in Figure 2B, at the same time, outputting the high potential signal to its control signal terminal C3. As a result, said 8 bits data ODA1 is input to the gate and hold circuit 7 and applied to the digital/analog converter 8. Thereafter, the communication processor 3 outputs the low potential signal to its control signal terminal C3 and outputs again 8 bits data ODA1, at the same time, outputting a high potential signal to its control signal terminal C3.Thereby, said 8 bits data ODA2 are input to the gate and hold circuit 7 and applied to the digital/analog converter 8.

Thereafter, the communication processor 3 increases the address signal being output to its address signal terminal AD2 by "1" and executes said process repeatedly during said established predetermined time period TC. As aforementioned, the data signal applied to the digital/analog converter 8 is converted into the analog signal and is output to the speaker 11 through the low band pass filter 9 and amplifier 10.

Further, when the predetermined time period TC is completed by the count at said communication professor 3, a high potential signal to the count completion signal is output and applied to the terminal CP1 of the timer microcomputer 2. As a result, the timer microcomputer 2 increases the number of the transmission MSC by "1", at the same time, outputting a low potential signal to its control signal terminal CS1 as shown in Figure 2B.

Thereafter, the timer microcomputer 2 determines whether or not said transmission number MSC is "2". When it is not "2", said timer microcomputer 2 outputs again the program address PAD to its address signal terminal AD1 as in the above-described explanation, at the same time, outputting again a high potential signal to its control signal terminal CS1 and to the output control signal terminal OUT. Therefore, at this moment, the communication processor 3 reads out again the 8 bits of data from the RAM 6 and transmits through the gate and hold circuit 7. Thus, when the communication processor 3 completes the count for the predetermined time period TC, a high potential signal of the count completion signal is output and applied to the terminal CP1 of the timer microcomputer 2.

Therefore, at this moment, the timer microcomputer 2 increases the transmission number MSC by "1", at the same time, outputting a low potential signal to its chip selection signal terminal CS1. Thereafter, the timer microcomputer 2 determines whether or not said transmission number of times MSC is "2", and when it is "2" executes repeatedly the process and increases said program address PAD by "1".

As described in detail above, according to the present example, the timer program is set, and at the same time, audio information of a user previously stored in a memory is output at said established program time. In this way, a user can store the desired audio information in conformity with the programmed recording time of the video cassette recorder.

There is advantage in that another useful function is thereby provided in addition to the conventional timer recording program.

Claims

CLAIMS:

1. Video recording apparatus including an audio message storage circuit which apparatus comprises a timer device for presetting a timer program for operating the apparatus, a microphone for receiving audio signals, a digital to analog converter to convert said audio signals to digital signals, a processor connected to a RAM and to said timer device for controlling writing into said RAM of said digital signals to store said digital signals, to read stored data from the RAM at times determined by said timer device and a speaker unit coupled through converter circuitry to said RAM to produce an audible output dependent on the data read from said RAM.

2. A circuit for storing an audio message, for use with a video cassette recorder, which comprises a key matrix for executing a key input, a timer microcomputer for executing control by receiving the input of a key signal of said key matrix, a communication processor for executing control of writing and reading of the audio signal data upon control of said timer microcomputer, a microphone for converting audio signals into electric signals, an analog/digital converter for converting the output signal of said microphone into 8 bits digital signal upon the control of said communication processor, and applying the 8 bits digital signal to said communication processor, a RAM for storing the audio signal when converted into said digital signal, a gate and hold circuit for transmitting audio signal data read from said RAM under the control of said communication processor, a digital/analog converter for converting the output signal of said gate and hold circuit into analog signal, a low band pass filter for passing only low band frequencies in the output signals of said digital/analog converter, an amplifier for amplifying the output signal of said low band pass filter, and a speaker for outputting the output of said amplifier into an audio signal.

3. A method for controlling storing of audio message comprising: a process which searches the key input of a key matrix at the timer microcomputer, and entering the message setting mode when a slide switch is located at the program position, increasing the program number by "1" at every setting time of a program number key at this message setting mode state, setting the program time of said program number by the setting of an hour key and a minute key, and thereafter outputting the address signal in accordance with said program number by the setting of the memory key, at the same time, outputting the communication processor control signal and the input control signal;; a process which enters the message transmission mode when the transmissions message key is set, when the present time is equal to the programmed time according to the program address at this state, outputting said program address, at the same time, outputting the communication processor control signal and the output control signal;; a process which enters the recording mode and setting a predetermined time when the communication processor control signal and the input control signal are output from said timer microcomputer and thereafter designating the start address of RAM by the address signal in accordance with the address signal output from said timer microcomputer, at the same time, applying the driving control signal to the analog/digital converter and receiving 3 times the input of 8 bits digital signal from said analog/digital converter and converting to two of 4 bits code and then combining to the 8 bits code data, and thereafter applying the driving signal and the record control signal to said RAM and writing in said 8 bits code data to said designated address, and then increasing the address of said RAM by lt until it is said predetermined time and executing repeatedly said process, at the same time, applying the count completion signal to said timer microcomputer when it is said predetermined time; and a process which enters the transmission mode and setting the predetermined time at said communication processor when the communication processor control signal and the output control signal are output from said timer microcomputer, and thereafter designating the start address of RAM by the address signal according to the program address signal output from said timer microcomputer, at the same time, applying the driving control signal to said RAM, reading out the 8 bits code data stored in said designated address, dividing said 8 bits code data into two of 4 bits code data and then converting respectively into the original 8 bits data, transmitting sequentially said two 8 bits data by applying the driving control signal to the gate and hold circuit, and thereafter when increasing the address of said RAM by "1" until it is said predetermined time, executing repeatedly said process, at the same time, applying the count completion signal to said timer microcomputer when it is said predetermined time.

4. A circuit for use with a video recorder which circuit is substantially as hereinbefore desribed with reference to the accompanying drawings.