GB2184574A - Using 8-bit modules in a 16-bit microprocessor system - Google Patents
Using 8-bit modules in a 16-bit microprocessor system Download PDFInfo
- Publication number
- GB2184574A GB2184574A GB08531407A GB8531407A GB2184574A GB 2184574 A GB2184574 A GB 2184574A GB 08531407 A GB08531407 A GB 08531407A GB 8531407 A GB8531407 A GB 8531407A GB 2184574 A GB2184574 A GB 2184574A
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- bit
- outputs
- address
- microprocessor system
- control
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- 238000000034 method Methods 0.000 claims abstract description 20
- 239000000872 buffer Substances 0.000 claims description 79
- 230000002457 bidirectional effect Effects 0.000 claims description 40
- 238000012986 modification Methods 0.000 claims description 12
- 230000004048 modification Effects 0.000 claims description 12
- 238000002360 preparation method Methods 0.000 claims description 2
- 238000013461 design Methods 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 241000272470 Circus Species 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4009—Coupling between buses with data restructuring
- G06F13/4018—Coupling between buses with data restructuring with data-width conversion
Abstract
A problem is the connection of a 16-bit microprocessor system (1) to 8-bit modules (5) so as to enable the performance of byte and word exchange operations and to facilitate the design of the software, by allowing use of instructions not restricted by the bit type of the modules. The problem is solved by a connection method where the 16-bit microprocessor system (1) in the case of word (2-byte) exchange is set in a waiting state during which time two writing or reading operations are performed. This enables the two bytes to be subsequently written in the 8-bit module (5). In word reading the least significant byte is stored in an additional register (7), the second byte is fed directly from the 8-bit module (5), and the 16-bit microprocessor system (1) reads the two bytes (the word) at the end of the second operation. <IMAGE>
Description
SPECIFICATION
A method and a device for the connection of a 16-bit microprocessor system with 8-bit modules
This invention relates to a method and a device for the connection of a 1 6-bit microprocessor system with 8-bit modules, finding application in 16-bit computers and microprocessor systems.
There is a well-known method disclosed in US Patent 4447878 for the connection of a 16-bit microprocessor system with 8-bit modules, wherein the 16-bit microprocessor system exchanges with the 8bit modules one byteforeach exchange operation. In the beginning ofthe operation the 16-bit microprocessor system sets the address and the exchange control signals to the 8-bit module, which fixes the state of the 16-bit microprocessor system when the exchangetimeislongerthanthedurationoftheex- change operation. The 16-bit microprocessor system, if required to exchange one word (2 bytes) by the 8-bit m module, performs two subsequent in- structions which effect two byte exchange operations.
It is a disadvantage ofthis method thatthe amount of information exchanged between the 1 6-bit microprocessor system and the 8-bit module is restricted by the number of digits ofthe 8-bit module and not by the 1 6-bit microprocessor system. Another disadvantage ofthe method is the low exchange speed between the 16-bit microprocessor system and the 8-bit module.
There is a well-known device forth connection of a 1 6-bit microprocessor system and 8-bit modules disclosed in US Patent 4 447 878, wherein the primary data inputs and outputs ofthe 16-bit micro processor system are connected to one half of the data inputs and outputs of a bidirectional data buffer, and the secondary data inputs and outputs are con nected to one or another half of the data inputs and outputs of a bidirectional data buffer. The address outputs of the 16-bit microprocessor system are connected to the inputs of a unidirectional address buffer the outputs of which are connected to the address inputs of the 8-bit modules.The data inputs and outputs of the 8-bit modules are connected to the other half of the data inputs and outputs of the bidirectional primary data buffer and one half of the data inputs and outputs of a bidirectional switching buffer, the other half of the data inputs and outputs being connected to the secondary data inputs and outputs of the 1 6bit microprocessor system.
In the case of byte exchange and even byte
address operations the 16-bit microprocessor system data inputs and outputs are directly coupled to the 8-bit module data inputs and outputs by
means ofthe primary bidirectional data buffer. In the case of byte exchange and odd byte address oper ations,the secondary data inputs and outputs ofthe 16-bit microprocessor system are connected to the 8-bit module data inputs and outputs by means of the bidirectional switching buffer.Forword exchange (2 byte) operations the primary 1 6-bit micro
processor system data inputs and outputs are coupled by means of the bidirectional primary data bufferto the 8-bit module data inputs and outputs, and the secondary 16-bit microprocessor system data inputs and outputs are connected only to the 16-bit modules in the system by means ofthe bidirectional secondary data buffer. In each ofthe above cases the address fed to the 16-bit microprocessor system address outputs is fed without any changetothe8-bit module address inputs by means ofthe unidirectional address buffer.
It is a disadvantage ofthe device that in (2-byte) word data exchange operations the 8-bit module data inputs and outputs should be evenly connected to the primary and secondary 16-bit microprocessor system inputs and outputs, which is in fact a firm connection ofthe 8-bit modules to addresses of even orodd boundary. A change of the address decoding circuits in the functionally compatible modules or the software of the 16-bit microprocessor systems is required to surmount the limitation appearing in the case of word exchanges.
It is a disadvantage both of the method and the de vicethattheycontain a limitationforthe utlization of firm (unchangeable) functionally compatible 8-bit modules in the 16-bit microprocessor system only for data byte exchange operations.
A preferred method and embodiment according to the invention may provide a conection of a 16-bit microprocessor system and 8-bit modules which could enablethe performance of byte exchange operations and word (2-byte) data exchanges at higher speed, and simplified software ofthe 16-bit microprocessor system, using the available circuits offunctionally compatible 8-bit modules.
According to a first aspect of the invention there is provided a method for the connection of a 16-bit microprocessor system to 8-bit modules wherein, in the case of word exchange operations, the 1 6-bit microprocessor system sets the address and the signals controlling the exchangetothe 8-bit modulefixing the state of the 1 6-bit microprocessor system, and wherein the state fixing time of the 1 6-bit microprocessor system is equal tothetimeforthe performance of one byte exchange operation with the 8-bit module, and atthe end of a first byte exchange operation the address is modified, and in a word reading operation performed bythe 16-bit microprocessor system the data read by the 8-bit module is stored, preparations are made for the commence ment of the second byte exchange operation, and the primary data inputs and outputs of the 1 6-bit microprocessor system are switched to the secondary, and at the beginning of the second byte exchange operation the 16-bit microprocessor system is taken out of its fixed state and the second byte exchange operation to the 8-bit module, and the performance ofthe whole word exchange operation by the 16-bit microprocessor system, are completed.
According to a second aspect of the invention there is provided a device for the connection of a 16bit microprocessor system to 8-bit modules, which is adapted and arranged for carrying out the method of the preceding paragraph.
This device may comprise a 16-bit microprocessor system having primary data inputs and outputs connected to one half of the data inputs and outputs of a bidirectional primary data buffer, secondary data inputs and outputs connected to one half of the data inputs and outputs of a bidirectional secondary data buffer, and address outputs connected to address inputs of a unidirectional address buffer the outputs of which are connected to address inputs of 8-bit modules having data inputs and outputs connected to the other half of the data inputs and outputs of a bidirectional primary data buffertheto one half ofthe data inputs and outputs of a bidirectional switching buffer, the other half of the data inputs and outputs of which are connected to the secondary data inputs and outputs of the 16-bit microprocessor system, wherein the primary data inputs of the 1 6-bit microprocessor system are connected to buffer register data outputs, the data inputs of which are connected to the one half of the data outputs of the bidirectional primary data buffer, the control output of the 16-bit microprocessor system being connected to a control input ofthe end cycle of a byte exchange control circuit the wait periods setting output of which is connected to the control input of the 1 6-bit microprocessor system, the data buffer control outputs of the control circuit being connected to the control inputs ofthe bidirectional primary data buffer, the buffer register, the bidirectional switching buffer and the bidirectional secondary data buffer, and the control outputforthe control circuit modification is con nected to a modification circu it the address input of which is connected to the address outputs of the 16bit microprocessor system, and its address output being connected to the address inputs ofthe unidirectional address buffer, the outputs of which are connected to the address input of the control circuit, the output controlling the address buffer of which is connected to the control input ofthe unidirectional address buffer, and its data input and output being connected to the control input and output ofthe 8-bit modules.
In a development the control circuit has a byte exchange twin cycle control unit, the control outputs of which are connected to a wait periods setting unit,a data buffer control unit and an address circuit control unit, the control input of the byte exchange twin cycle control unit being the control input of the byte exchange twin cycle of the control circuit, and in addition its input/output is the data input and output ofthe control circuit, the output ofthe wait periods setting unit being the outputforthe setting of wait periods of the control circuit, the data buffer control outputs of which are the outputs ofthe data buffer control unit, the address input of which is the address address circuits control unit being the control outputforthe control circuit modification, the other output ofthe address circuit control unit being the control output of the address buffer.
A preferred method and embodiment ofthis invention may provide the connection of 8-bitfunc- tionally compatible modules to the 16-bit microprocessor system giving the performance of operations demanding both byte exchanges and word data (2 byte) exchanges with the 8-bit modules.
Furthermore, no changes need be required either in the circuits ofthe functionally compatible 8-bit modules or in the software of the 16-bit microprocessor system.
Another advantage of a preferred method and em bodimentmaybethatwhenthe 16-bit microprocessor system exchanges one word (2 bytes) with the 8-bit module a word-exchange instruction is performed instead of the performance of two byte exchange instructions, and forthetirnetwo operations for byte exchange are performed on the 8-bit module, the 16-bit system performs one word data exchange operation. This results in higher speed ex- changes between the 16-bit microprocessor system and the 8-bit module and the simplification ofthe system software.
For a better understanding ofthe invention and to show how it may be put into effect, reference will now be made by way of example to the accompanying drawings in which:
Figure lisa block diagram including a device for connecting a 16-bit microprocessor system to 8-bit modules; and
Figure2 is a block diagram of the control circuit of
Figure 1.
In a device for connecting a 16-bit microprocessor system to 8-bit modules, the primary data inputs and outputs of a 16-bit microprocessor system 1 are connected to one half of the data inputs and outputs of a bidirectional primary data buffer 2, and its secondary data inputs and outputs are connected to one half of the data inputs and outputs of a secondary data buffer 3. The address outputs of the 1 6-bit microprocessor system 1 are connected to the address inputs of a unidirectional address buffer4,the outputs of which are connected to address inputs of 8-bit modules 5.The data inputs and outputs of the 8-bit modules 5 areconnectedtothe other half ofthe data inputs and outputs of the bidirectional primary data buffer 2, and to one half of data inputs and outputs of a bidirectional switching buffer 6, the other half of the data inputs and outputs of which are connected tothesecondaryinputsandoutputsofthe 16-bitmicroprocessor system 1.
The primary data inputs ofthe 16-bit microprocessor system 1 are connected to the data outputs of a buffer register 7, the data inputs of which are connected to one half of the data outputs of the bidirectional primary data buffer 2. The control output of the 1 6-bit microprocessor system 1 is connected to a control input of a byte exchange twin cycle of a control circuit 8, the wait period setting output of which is connected to the control input of the 16-bit microprocessor system 1. The control circuit 8 data buffer control outputs are connected to the control inputs ofthe bidirectional primary data buffer 2, the buffer register 7, the switching bidirectional buffer 6 and the bidirectional secondary data buffer 3. The control circuit8 modification control output is connected to a modification circuit 9, the address input of which is connected to the address outputs ofthe 16-bitmicroprocessorsystem 1, and its address output is connected to the address inputs ofthe unidirectional address buffer4. The out putsoftheunidirectional addressbuffer4arecon- nected to the address input of the control circuit 8, the address buffer control output of which is connected to the control input of the unidirectional address buffer4, and its data input and output are connected to the control input and outputofthe 8-bit modules 5.
As can be seen from Figure 2, the control circuit 8 includes a byte exchange twin cycle control unit 10 the control outputs of which are connected to a wait ing periods setting unit 11, to a data buffer control unit 12 and to an address circuit control unit 13. The control input ofthe byte exchange twin cycle control unit loins the control input ofthe byte exchange twin cycle of the control circuit 8, and its input/output is the data input/output ofthe same circuit 8. Thewait periods setting unit output 11 is the output of wait periods setting of the control circuits, and the control unit outputs of the data buffers 12 are the outputs for controlling the data buffers, and its address input is the address input ofthe control circuit 8.The one output of the address circuit control unit 13 is the control modification output, and its other output is the output of the address buffer of the control circuit 8.
This is how the deviceforthe connection ofthe 16-bit microprocessor system to the 8-bit modules, in accordance with this method, operates. The byte exchange twin cycle control unit 10 follows andre- cognises the type of the instruction fed by the 1 6-bit microprocessor system 1. For instructions demand ing byte exchangethe wait periods setting unit 1 1 is notenergized. The same is alsotrueforthe address circuits control unit 13. The address fed across the address outputs of the 1 6-bit microprocessor system 1 is transmitted with no change across the unilateral address buffer 4 to the address inputs of the 8-bit modules 5. The modification circuit 9 makes no active operations.
The data buffer control u nit 12 controls the pri mary bidirectional data buffer 2, the bidirectional switching data buffer 6 and the secondary bidirectional data buffer 3. When a byte address is read, the primary data inputs of the 16-bit microprocessor system 1 are connected by means of the primary bidirectional data buffrer 2 to the data inputs and outputs ofthe 8-bit modules 5. In the case of byte odd address to the data inputs and outputs of the 8-bit modules Sthe secondary data inputs and outputs of the 16-bit microprocessor system 1 are connected by means ofthe bidirectional switching buffer 6.
The byte exchange twin cycle control unit 10 sensesthe conditions forthe loading of waiting per iodsrequired bythe8-bitmodules5orthel6-bit microprocessor system 1 for the materialization of a single byte exchange cycle and organises,with no change, the performance ofthe required amount of wait periods.
For instructions demanding word exchange (2 bytes) the byte exchange twin cycle control unit 10 energisesthewait periods setting unit 11 which sets the 16-bit microprocessor system 1 into a state of waiting. This state continues for as many periods as are requiredforthe performance oftheadditional, second, cycle of byte exchange. Simultaneously the conditions for setting wait periods required by the 8-bit modules 5 or the 16-bit microprocessor system 1 are being watched forthe performance of a single byte exchange cycle and the required amount of wait periods are performed with no change.
The byte exchange twin cycle control unit 10 performs its functions by means of the data buffer control unit 12 and the address circuit control unit 13.
Two byte exchange cycles are performed in the direction set by the supplied instruction.
In the first cycle, the address fed to the address outputsofthe 16-bitmicroprocessorsystem 1 is transmitted with no change across the unidirectional address buffer 4to the address inputs ofthe 8-bit modules 5. In the case of a recording instruction the data buffercontrol unitl2securesthefeeding ofthe existing byte across the primary data outputs of the 1 6-bit microprocessor system 1 to the data inputs of the 8-bit modules 5 across the primary bidirectional data buffer 2.
In the case of a reading instruction the data buffer control unit 12 secures the storing ofthe byte data found at the data outputs ofthe 8-bit modules Sin the buffer register 7 after it has let it across the primary bidirectional data buffer 2. The control circuit8 guaranteesthestrictobservanceofthetime schedule and the time limitationscharacteristicfor the exchange cycle between the 16-bit microprocessor system 1 and the 8-bit modules 5.
The second exchange cycle is fully controlled by the byte exchange twin cycle control unit 10. The modification of the address in the modification circuit9 occurs in this cycle and this guarantees the selection and servicing ofthe second byte ofthe word. The modified address is fed across the unidirectional address buffer 4 to the address inputs of the 8-bit modules 5. When there is an instruction for recording the data buffer control unit 12 secures the byte transmission which is across the secondary data outputs of the 16-bit microprocessor system 1 to the data inputs ofthe 8-bit modules 5 across the bidirectional switching buffer6.
In the case of a reading instruction the data buffer control unit 12 guarantees the feeding of the byte across the data outputs of the 8-bit modules 5 to the secondary data inputs ofthe 1 6-bit microprocessor system 1 across the bidirectional switching buffer 6.
Simultaneously the buffer register 7 issues the stored data byte in itduringthefirstexchangecycleto the free primary data inputs of the 1 6-bit microprocessor system 1.
Thus, at the end ofthe second cycle, the 1 6-bit microprocessor system 1, after being changed from the state of waiting by means of the wait periods setting unit 11, can receive the address word (2 bytes). The exchange with the 1 6-bit microprocessor system 1 by the 8-bitfunctionally compatible modules 5 is made only by bytes regardless ofthe requirements ofthe instruction performed for byte or word exchange.
There is provided a method and a deviceforthe connection of a 16-bit microprocessor system (1) to 8-bit modules (5) which finds application in 16-bit computers and microprocessor systems.
Aproblem isto devise a method and a devicefor the connection of a 16-bit microprocessor system (1 ) to 8-bit modules (5) which would enable the performance of byte and word exchange operations. This shall facilitate the design of the software, as the type of the instructions made shall not be restricted bythe bittype ofthe modules.
The problem is solved by a connection method where the 16-bit microprocessor system (1 ) in the case of word exchange is set in a waiting state during whichtimetworecording or reading operations are performed. This enables the two word bytes to be subsequently recorded in the 8-bit module (5). In word reading the least significant byte is recorded into an additional register, and the second byte is fed directly from the 8-bit module (5), and the 1 6-bit mic roprocessorsystem (1) readsthetwo bytes (the word) at the end of the second operation.
It is an advantage ofthis procedure that the instruction type used by the 1 6-bit microprocessor system (1) does not depend on the bit type of the modules used for its communication.
Claims (6)
1. A method for the connection of a 1 6-bit micro processorsystem to 8-bit modules wherein, in the case of word exchange operations, the 1 6-bit microprocessor system sets the address and the signals controlling the exchange to the 8-bit modulefixing the state of the 16-bit microprocessor system, and wherein the state fixing time of the 1 6-bit microprocessor system is equal to the time for the performance of one byte exchange operation with the 8-bit module, and atthe end of a first byte exchange operation the address is modified, and in a word reading operation performed by#the 16-bit micro- processor system the data read by the 8-bit module is stored, preparations are made for the commencement ofthe second byte exchange operation, the the primary data inputs and outputs ofthe 16-bit microprocessor system are switched to the secondary, and at the beginning ofthe second byte exchange operation the 16-bit microprocessor system is taken out of its fixed state and the second byte exchange operation to the 8-bit module, and the performance of the whole word exchange operation by the 16-bit microprocessor system, are completed.
2. A device forthe connection of a 1 6-bit microprocessor system to 8-bit modules,which is adapted and arranged for carrying outthe method according to claim 1.
3. A device forthe connection of a 1 6-bit microprocessor system to 8-bit modules in accordance with claim 2, comprising a 1 6-bit microprocessor system having primary data inputs and outputs connected to one half of the data inputs and outputs of a bidirectional primary data buffer, secondary data inputs and outputs connected to one half of the data inputs and outputs of a bidirectional secondary data buffer, and address outputs connected to address inputs of a unidirectional address buffer the outputs of which are connected to address inputs of 8-bit modules having data inputs and outputs connected to the other half of the data inputs and outputs of the bidirectional primary data buffer and to one half of the data inputs and outputs of the bidirectional switching buffer, the other half ofthe data inputs and outputs of which are connected to the secondary data inputs and outputs of the 1 6-bit microprocessor system, wherein the primary data inputs of the 16-bit microprocessor system are connected to buffer reg ster data outputs, the data inputs of which are con nected to the one half ofthe data outputs of the bidirectional primary data buffer, the control output of the 16-bit microprocessor system being connected to a control input ofthe end cycle of a byte exchange control circuitthewait periods setting output of which is connected to the control input of the 1 6-bit microprocessor system, the data buffer control outputs of the control circuit being connected to the control inputs of the bidirectional primary data buffer, the buffer register, the bidirectional switching buffer and the bidirectional secondary data buffer, and the control outputforthe control circuit modification is connected to a modification circuitthe address input of which is connected to the address outputs of the 16-bit microprocessor system, and its address output being connected to the address inputs ofthe unidirectional address buffer, the outputs of which are connected to the address input of the control circuit, the output controlling the address buffer of which is connected to the control input ofthe unidirectional address buffer, and its data input and output being connected to the control input and output of the 8-bit modules.
4. A device according to claim 3, wherein the control circuit has a byte exchange twin cycle control unit, the control outputs of which are connected to a wait periods setting unit, a data buffer control unit and an address circuit control unit, the control input of the byte exchange twin cycle control unit being the control input of the byte exchange twin cycle of the control circuit, and in addition its input/output is the data input and output of the control circuit, the output of the wait periods setting unit being the outputforthe setting of wait periods of the control ci rcu it, the data buffer control outputs of which are the outputs of the data buffer control unit, the address input of which is the address input ofthe control circuit, the one output of the address circuits control unit being the control outputforthe control circuit modification, the other output of the address circuit control unit being the control output of the address buffer.
5. A method for the connection of a 1 6-bit microprocessor system to 8-bit modules, substantially as hereinbefore described with reference to Figures 1 and 2 of the accompanying drawings.
6. A device for the connection of a 1 6-bit microprocessor system to 8-bit modules, substantially as hereinbefore described with reference to Figures 1 and 2 ofthe accompanying drawings.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| BG8465418A BG44516A1 (en) | 1984-05-08 | 1984-05-08 | Device for connecting of 16- digits microprocessor system with 8- digits modules |
| DE19853545472 DE3545472A1 (en) | 1984-05-08 | 1985-12-20 | METHOD AND DEVICE FOR CONNECTING A 16-DIGIT MICROPROCESSOR SYSTEM TO 8-DIGIT MODULES |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| GB8531407D0 GB8531407D0 (en) | 1986-02-05 |
| GB2184574A true GB2184574A (en) | 1987-06-24 |
Family
ID=25663323
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB08531407A Withdrawn GB2184574A (en) | 1984-05-08 | 1985-12-20 | Using 8-bit modules in a 16-bit microprocessor system |
Country Status (4)
| Country | Link |
|---|---|
| BG (1) | BG44516A1 (en) |
| CU (1) | CU21985A1 (en) |
| DE (1) | DE3545472A1 (en) |
| GB (1) | GB2184574A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2202351A (en) * | 1987-03-19 | 1988-09-21 | Ciitt | Plural bit-width microprocessor system |
-
1984
- 1984-05-08 BG BG8465418A patent/BG44516A1/en unknown
-
1985
- 1985-12-05 CU CU8523A patent/CU21985A1/en unknown
- 1985-12-20 GB GB08531407A patent/GB2184574A/en not_active Withdrawn
- 1985-12-20 DE DE19853545472 patent/DE3545472A1/en not_active Withdrawn
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2202351A (en) * | 1987-03-19 | 1988-09-21 | Ciitt | Plural bit-width microprocessor system |
| DE3809234A1 (en) * | 1987-03-19 | 1988-10-06 | Ciitt | 16-BIT MICROPROCESSOR SYSTEM |
Also Published As
| Publication number | Publication date |
|---|---|
| GB8531407D0 (en) | 1986-02-05 |
| CU21985A1 (en) | 1992-06-05 |
| DE3545472A1 (en) | 1987-07-23 |
| BG44516A1 (en) | 1988-12-15 |
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|---|---|---|---|
| WAP | Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1) |